1 /**
2 ******************************************************************************
3 * @file stm32g4xx_hal_adc.c
4 * @author MCD Application Team
5 * @brief This file provides firmware functions to manage the following
6 * functionalities of the Analog to Digital Converter (ADC)
7 * peripheral:
8 * + Initialization and de-initialization functions
9 * + Peripheral Control functions
10 * + Peripheral State functions
11 * Other functions (extended functions) are available in file
12 * "stm32g4xx_hal_adc_ex.c".
13 *
14 ******************************************************************************
15 * @attention
16 *
17 * Copyright (c) 2019 STMicroelectronics.
18 * All rights reserved.
19 *
20 * This software is licensed under terms that can be found in the LICENSE file
21 * in the root directory of this software component.
22 * If no LICENSE file comes with this software, it is provided AS-IS.
23 *
24 ******************************************************************************
25 @verbatim
26 ==============================================================================
27 ##### ADC peripheral features #####
28 ==============================================================================
29 [..]
30 (+) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution.
31
32 (+) Interrupt generation at the end of regular conversion and in case of
33 analog watchdog or overrun events.
34
35 (+) Single and continuous conversion modes.
36
37 (+) Scan mode for conversion of several channels sequentially.
38
39 (+) Data alignment with in-built data coherency.
40
41 (+) Programmable sampling time (channel wise)
42
43 (+) External trigger (timer or EXTI) with configurable polarity
44
45 (+) DMA request generation for transfer of conversions data of regular group.
46
47 (+) Configurable delay between conversions in Dual interleaved mode.
48
49 (+) ADC channels selectable single/differential input.
50
51 (+) ADC offset shared on 4 offset instances.
52 (+) ADC gain compensation
53
54 (+) ADC calibration
55
56 (+) ADC conversion of regular group.
57
58 (+) ADC supply requirements: 1.62 V to 3.6 V.
59
60 (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to
61 Vdda or to an external voltage reference).
62
63
64 ##### How to use this driver #####
65 ==============================================================================
66 [..]
67
68 *** Configuration of top level parameters related to ADC ***
69 ============================================================
70 [..]
71
72 (#) Enable the ADC interface
73 (++) As prerequisite, ADC clock must be configured at RCC top level.
74
75 (++) Two clock settings are mandatory:
76 (+++) ADC clock (core clock, also possibly conversion clock).
77
78 (+++) ADC clock (conversions clock).
79 Two possible clock sources: synchronous clock derived from AHB clock
80 or asynchronous clock derived from system clock or PLL (output divider P)
81 running up to 75MHz.
82
83 (+++) Example:
84 Into HAL_ADC_MspInit() (recommended code location) or with
85 other device clock parameters configuration:
86 (+++) __HAL_RCC_ADC_CLK_ENABLE(); (mandatory)
87
88 RCC_ADCCLKSOURCE_PLL enable: (optional: if asynchronous clock selected)
89 (+++) RCC_PeriphClkInitTypeDef RCC_PeriphClkInit;
90 (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
91 (+++) PeriphClkInit.AdcClockSelection = RCC_ADCCLKSOURCE_PLL;
92 (+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);
93
94 (++) ADC clock source and clock prescaler are configured at ADC level with
95 parameter "ClockPrescaler" using function HAL_ADC_Init().
96
97 (#) ADC pins configuration
98 (++) Enable the clock for the ADC GPIOs
99 using macro __HAL_RCC_GPIOx_CLK_ENABLE()
100 (++) Configure these ADC pins in analog mode
101 using function HAL_GPIO_Init()
102
103 (#) Optionally, in case of usage of ADC with interruptions:
104 (++) Configure the NVIC for ADC
105 using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
106 (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
107 into the function of corresponding ADC interruption vector
108 ADCx_IRQHandler().
109
110 (#) Optionally, in case of usage of DMA:
111 (++) Configure the DMA (DMA channel, mode normal or circular, ...)
112 using function HAL_DMA_Init().
113 (++) Configure the NVIC for DMA
114 using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
115 (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
116 into the function of corresponding DMA interruption vector
117 DMAx_Channelx_IRQHandler().
118
119 *** Configuration of ADC, group regular, channels parameters ***
120 ================================================================
121 [..]
122
123 (#) Configure the ADC parameters (resolution, data alignment, ...)
124 and regular group parameters (conversion trigger, sequencer, ...)
125 using function HAL_ADC_Init().
126
127 (#) Configure the channels for regular group parameters (channel number,
128 channel rank into sequencer, ..., into regular group)
129 using function HAL_ADC_ConfigChannel().
130
131 (#) Optionally, configure the analog watchdog parameters (channels
132 monitored, thresholds, ...)
133 using function HAL_ADC_AnalogWDGConfig().
134
135 *** Execution of ADC conversions ***
136 ====================================
137 [..]
138
139 (#) Optionally, perform an automatic ADC calibration to improve the
140 conversion accuracy
141 using function HAL_ADCEx_Calibration_Start().
142
143 (#) ADC driver can be used among three modes: polling, interruption,
144 transfer by DMA.
145
146 (++) ADC conversion by polling:
147 (+++) Activate the ADC peripheral and start conversions
148 using function HAL_ADC_Start()
149 (+++) Wait for ADC conversion completion
150 using function HAL_ADC_PollForConversion()
151 (+++) Retrieve conversion results
152 using function HAL_ADC_GetValue()
153 (+++) Stop conversion and disable the ADC peripheral
154 using function HAL_ADC_Stop()
155
156 (++) ADC conversion by interruption:
157 (+++) Activate the ADC peripheral and start conversions
158 using function HAL_ADC_Start_IT()
159 (+++) Wait for ADC conversion completion by call of function
160 HAL_ADC_ConvCpltCallback()
161 (this function must be implemented in user program)
162 (+++) Retrieve conversion results
163 using function HAL_ADC_GetValue()
164 (+++) Stop conversion and disable the ADC peripheral
165 using function HAL_ADC_Stop_IT()
166
167 (++) ADC conversion with transfer by DMA:
168 (+++) Activate the ADC peripheral and start conversions
169 using function HAL_ADC_Start_DMA()
170 (+++) Wait for ADC conversion completion by call of function
171 HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback()
172 (these functions must be implemented in user program)
173 (+++) Conversion results are automatically transferred by DMA into
174 destination variable address.
175 (+++) Stop conversion and disable the ADC peripheral
176 using function HAL_ADC_Stop_DMA()
177
178 [..]
179
180 (@) Callback functions must be implemented in user program:
181 (+@) HAL_ADC_ErrorCallback()
182 (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog)
183 (+@) HAL_ADC_ConvCpltCallback()
184 (+@) HAL_ADC_ConvHalfCpltCallback
185
186 *** Deinitialization of ADC ***
187 ============================================================
188 [..]
189
190 (#) Disable the ADC interface
191 (++) ADC clock can be hard reset and disabled at RCC top level.
192 (++) Hard reset of ADC peripherals
193 using macro __ADCx_FORCE_RESET(), __ADCx_RELEASE_RESET().
194 (++) ADC clock disable
195 using the equivalent macro/functions as configuration step.
196 (+++) Example:
197 Into HAL_ADC_MspDeInit() (recommended code location) or with
198 other device clock parameters configuration:
199 (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI14;
200 (+++) RCC_OscInitStructure.HSI14State = RCC_HSI14_OFF; (if not used for system clock)
201 (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure);
202
203 (#) ADC pins configuration
204 (++) Disable the clock for the ADC GPIOs
205 using macro __HAL_RCC_GPIOx_CLK_DISABLE()
206
207 (#) Optionally, in case of usage of ADC with interruptions:
208 (++) Disable the NVIC for ADC
209 using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
210
211 (#) Optionally, in case of usage of DMA:
212 (++) Deinitialize the DMA
213 using function HAL_DMA_Init().
214 (++) Disable the NVIC for DMA
215 using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
216
217 [..]
218
219 *** Callback registration ***
220 =============================================
221 [..]
222
223 The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1,
224 allows the user to configure dynamically the driver callbacks.
225 Use Functions HAL_ADC_RegisterCallback()
226 to register an interrupt callback.
227 [..]
228
229 Function HAL_ADC_RegisterCallback() allows to register following callbacks:
230 (+) ConvCpltCallback : ADC conversion complete callback
231 (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback
232 (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback
233 (+) ErrorCallback : ADC error callback
234 (+) InjectedConvCpltCallback : ADC group injected conversion complete callback
235 (+) InjectedQueueOverflowCallback : ADC group injected context queue overflow callback
236 (+) LevelOutOfWindow2Callback : ADC analog watchdog 2 callback
237 (+) LevelOutOfWindow3Callback : ADC analog watchdog 3 callback
238 (+) EndOfSamplingCallback : ADC end of sampling callback
239 (+) MspInitCallback : ADC Msp Init callback
240 (+) MspDeInitCallback : ADC Msp DeInit callback
241 This function takes as parameters the HAL peripheral handle, the Callback ID
242 and a pointer to the user callback function.
243 [..]
244
245 Use function HAL_ADC_UnRegisterCallback to reset a callback to the default
246 weak function.
247 [..]
248
249 HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle,
250 and the Callback ID.
251 This function allows to reset following callbacks:
252 (+) ConvCpltCallback : ADC conversion complete callback
253 (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback
254 (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback
255 (+) ErrorCallback : ADC error callback
256 (+) InjectedConvCpltCallback : ADC group injected conversion complete callback
257 (+) InjectedQueueOverflowCallback : ADC group injected context queue overflow callback
258 (+) LevelOutOfWindow2Callback : ADC analog watchdog 2 callback
259 (+) LevelOutOfWindow3Callback : ADC analog watchdog 3 callback
260 (+) EndOfSamplingCallback : ADC end of sampling callback
261 (+) MspInitCallback : ADC Msp Init callback
262 (+) MspDeInitCallback : ADC Msp DeInit callback
263 [..]
264
265 By default, after the HAL_ADC_Init() and when the state is HAL_ADC_STATE_RESET
266 all callbacks are set to the corresponding weak functions:
267 examples HAL_ADC_ConvCpltCallback(), HAL_ADC_ErrorCallback().
268 Exception done for MspInit and MspDeInit functions that are
269 reset to the legacy weak functions in the HAL_ADC_Init()/ HAL_ADC_DeInit() only when
270 these callbacks are null (not registered beforehand).
271 [..]
272
273 If MspInit or MspDeInit are not null, the HAL_ADC_Init()/ HAL_ADC_DeInit()
274 keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
275 [..]
276
277 Callbacks can be registered/unregistered in HAL_ADC_STATE_READY state only.
278 Exception done MspInit/MspDeInit functions that can be registered/unregistered
279 in HAL_ADC_STATE_READY or HAL_ADC_STATE_RESET state,
280 thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
281 [..]
282
283 Then, the user first registers the MspInit/MspDeInit user callbacks
284 using HAL_ADC_RegisterCallback() before calling HAL_ADC_DeInit()
285 or HAL_ADC_Init() function.
286 [..]
287
288 When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or
289 not defined, the callback registration feature is not available and all callbacks
290 are set to the corresponding weak functions.
291
292 @endverbatim
293 ******************************************************************************
294 */
295
296 /* Includes ------------------------------------------------------------------*/
297 #include "stm32g4xx_hal.h"
298
299 /** @addtogroup STM32G4xx_HAL_Driver
300 * @{
301 */
302
303 /** @defgroup ADC ADC
304 * @brief ADC HAL module driver
305 * @{
306 */
307
308 #ifdef HAL_ADC_MODULE_ENABLED
309
310 /* Private typedef -----------------------------------------------------------*/
311 /* Private define ------------------------------------------------------------*/
312
313 /** @defgroup ADC_Private_Constants ADC Private Constants
314 * @{
315 */
316
317 #define ADC_CFGR_FIELDS_1 ((ADC_CFGR_RES | ADC_CFGR_ALIGN |\
318 ADC_CFGR_CONT | ADC_CFGR_OVRMOD |\
319 ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM |\
320 ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL)) /*!< ADC_CFGR fields of parameters that can be updated when no regular conversion is on-going */
321
322 /* Timeout values for ADC operations (enable settling time, */
323 /* disable settling time, ...). */
324 /* Values defined to be higher than worst cases: low clock frequency, */
325 /* maximum prescalers. */
326 #define ADC_ENABLE_TIMEOUT (2UL) /*!< ADC enable time-out value */
327 #define ADC_DISABLE_TIMEOUT (2UL) /*!< ADC disable time-out value */
328
329 /* Timeout to wait for current conversion on going to be completed. */
330 /* Timeout fixed to longest ADC conversion possible, for 1 channel: */
331 /* - maximum sampling time (640.5 adc_clk) */
332 /* - ADC resolution (Tsar 12 bits= 12.5 adc_clk) */
333 /* - System clock / ADC clock <= 4096 (hypothesis of maximum clock ratio) */
334 /* - ADC oversampling ratio 256 */
335 /* Calculation: 653 * 4096 * 256 CPU clock cycles max */
336 /* Unit: cycles of CPU clock. */
337 #define ADC_CONVERSION_TIME_MAX_CPU_CYCLES (653UL * 4096UL * 256UL) /*!< ADC conversion completion time-out value */
338
339
340 /**
341 * @}
342 */
343
344 /* Private macro -------------------------------------------------------------*/
345 /* Private variables ---------------------------------------------------------*/
346 /* Private function prototypes -----------------------------------------------*/
347 /* Exported functions --------------------------------------------------------*/
348
349 /** @defgroup ADC_Exported_Functions ADC Exported Functions
350 * @{
351 */
352
353 /** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions
354 * @brief ADC Initialization and Configuration functions
355 *
356 @verbatim
357 ===============================================================================
358 ##### Initialization and de-initialization functions #####
359 ===============================================================================
360 [..] This section provides functions allowing to:
361 (+) Initialize and configure the ADC.
362 (+) De-initialize the ADC.
363 @endverbatim
364 * @{
365 */
366
367 /**
368 * @brief Initialize the ADC peripheral and regular group according to
369 * parameters specified in structure "ADC_InitTypeDef".
370 * @note As prerequisite, ADC clock must be configured at RCC top level
371 * (refer to description of RCC configuration for ADC
372 * in header of this file).
373 * @note Possibility to update parameters on the fly:
374 * This function initializes the ADC MSP (HAL_ADC_MspInit()) only when
375 * coming from ADC state reset. Following calls to this function can
376 * be used to reconfigure some parameters of ADC_InitTypeDef
377 * structure on the fly, without modifying MSP configuration. If ADC
378 * MSP has to be modified again, HAL_ADC_DeInit() must be called
379 * before HAL_ADC_Init().
380 * The setting of these parameters is conditioned to ADC state.
381 * For parameters constraints, see comments of structure
382 * "ADC_InitTypeDef".
383 * @note This function configures the ADC within 2 scopes: scope of entire
384 * ADC and scope of regular group. For parameters details, see comments
385 * of structure "ADC_InitTypeDef".
386 * @note Parameters related to common ADC registers (ADC clock mode) are set
387 * only if all ADCs are disabled.
388 * If this is not the case, these common parameters setting are
389 * bypassed without error reporting: it can be the intended behaviour in
390 * case of update of a parameter of ADC_InitTypeDef on the fly,
391 * without disabling the other ADCs.
392 * @param hadc ADC handle
393 * @retval HAL status
394 */
HAL_ADC_Init(ADC_HandleTypeDef * hadc)395 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc)
396 {
397 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
398 uint32_t tmpCFGR;
399 uint32_t tmp_adc_reg_is_conversion_on_going;
400 __IO uint32_t wait_loop_index = 0UL;
401 uint32_t tmp_adc_is_conversion_on_going_regular;
402 uint32_t tmp_adc_is_conversion_on_going_injected;
403
404 /* Check ADC handle */
405 if (hadc == NULL)
406 {
407 return HAL_ERROR;
408 }
409
410 /* Check the parameters */
411 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
412 assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler));
413 assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution));
414 assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign));
415 assert_param(IS_ADC_GAIN_COMPENSATION(hadc->Init.GainCompensation));
416 assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
417 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
418 assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
419 assert_param(IS_ADC_EXTTRIG(hadc, hadc->Init.ExternalTrigConv));
420 assert_param(IS_ADC_SAMPLINGMODE(hadc->Init.SamplingMode));
421 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
422 assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
423 assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun));
424 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait));
425 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OversamplingMode));
426
427 if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
428 {
429 assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
430 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
431
432 if (hadc->Init.DiscontinuousConvMode == ENABLE)
433 {
434 assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion));
435 }
436 }
437
438 /* DISCEN and CONT bits cannot be set at the same time */
439 assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (hadc->Init.ContinuousConvMode == ENABLE)));
440
441 /* Actions performed only if ADC is coming from state reset: */
442 /* - Initialization of ADC MSP */
443 if (hadc->State == HAL_ADC_STATE_RESET)
444 {
445 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
446 /* Init the ADC Callback settings */
447 hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback; /* Legacy weak callback */
448 hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback; /* Legacy weak callback */
449 hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback; /* Legacy weak callback */
450 hadc->ErrorCallback = HAL_ADC_ErrorCallback; /* Legacy weak callback */
451 hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback; /* Legacy weak callback */
452 hadc->InjectedQueueOverflowCallback = HAL_ADCEx_InjectedQueueOverflowCallback; /* Legacy weak callback */
453 hadc->LevelOutOfWindow2Callback = HAL_ADCEx_LevelOutOfWindow2Callback; /* Legacy weak callback */
454 hadc->LevelOutOfWindow3Callback = HAL_ADCEx_LevelOutOfWindow3Callback; /* Legacy weak callback */
455 hadc->EndOfSamplingCallback = HAL_ADCEx_EndOfSamplingCallback; /* Legacy weak callback */
456
457 if (hadc->MspInitCallback == NULL)
458 {
459 hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */
460 }
461
462 /* Init the low level hardware */
463 hadc->MspInitCallback(hadc);
464 #else
465 /* Init the low level hardware */
466 HAL_ADC_MspInit(hadc);
467 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
468
469 /* Set ADC error code to none */
470 ADC_CLEAR_ERRORCODE(hadc);
471
472 /* Initialize Lock */
473 hadc->Lock = HAL_UNLOCKED;
474 }
475
476 /* - Exit from deep-power-down mode and ADC voltage regulator enable */
477 if (LL_ADC_IsDeepPowerDownEnabled(hadc->Instance) != 0UL)
478 {
479 /* Disable ADC deep power down mode */
480 LL_ADC_DisableDeepPowerDown(hadc->Instance);
481
482 /* System was in deep power down mode, calibration must
483 be relaunched or a previously saved calibration factor
484 re-applied once the ADC voltage regulator is enabled */
485 }
486
487 if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL)
488 {
489 /* Enable ADC internal voltage regulator */
490 LL_ADC_EnableInternalRegulator(hadc->Instance);
491
492 /* Note: Variable divided by 2 to compensate partially */
493 /* CPU processing cycles, scaling in us split to not */
494 /* exceed 32 bits register capacity and handle low frequency. */
495 wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
496 while (wait_loop_index != 0UL)
497 {
498 wait_loop_index--;
499 }
500 }
501
502 /* Verification that ADC voltage regulator is correctly enabled, whether */
503 /* or not ADC is coming from state reset (if any potential problem of */
504 /* clocking, voltage regulator would not be enabled). */
505 if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL)
506 {
507 /* Update ADC state machine to error */
508 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
509
510 /* Set ADC error code to ADC peripheral internal error */
511 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
512
513 tmp_hal_status = HAL_ERROR;
514 }
515
516 /* Configuration of ADC parameters if previous preliminary actions are */
517 /* correctly completed and if there is no conversion on going on regular */
518 /* group (ADC may already be enabled at this point if HAL_ADC_Init() is */
519 /* called to update a parameter on the fly). */
520 tmp_adc_reg_is_conversion_on_going = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
521
522 if (((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
523 && (tmp_adc_reg_is_conversion_on_going == 0UL)
524 )
525 {
526 /* Set ADC state */
527 ADC_STATE_CLR_SET(hadc->State,
528 HAL_ADC_STATE_REG_BUSY,
529 HAL_ADC_STATE_BUSY_INTERNAL);
530
531 /* Configuration of common ADC parameters */
532
533 /* Parameters update conditioned to ADC state: */
534 /* Parameters that can be updated only when ADC is disabled: */
535 /* - clock configuration */
536 if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
537 {
538 if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
539 {
540 /* Reset configuration of ADC common register CCR: */
541 /* */
542 /* - ADC clock mode and ACC prescaler (CKMODE and PRESC bits)are set */
543 /* according to adc->Init.ClockPrescaler. It selects the clock */
544 /* source and sets the clock division factor. */
545 /* */
546 /* Some parameters of this register are not reset, since they are set */
547 /* by other functions and must be kept in case of usage of this */
548 /* function on the fly (update of a parameter of ADC_InitTypeDef */
549 /* without needing to reconfigure all other ADC groups/channels */
550 /* parameters): */
551 /* - when multimode feature is available, multimode-related */
552 /* parameters: MDMA, DMACFG, DELAY, DUAL (set by API */
553 /* HAL_ADCEx_MultiModeConfigChannel() ) */
554 /* - internal measurement paths: Vbat, temperature sensor, Vref */
555 /* (set into HAL_ADC_ConfigChannel() or */
556 /* HAL_ADCEx_InjectedConfigChannel() ) */
557 LL_ADC_SetCommonClock(__LL_ADC_COMMON_INSTANCE(hadc->Instance), hadc->Init.ClockPrescaler);
558 }
559 }
560
561 /* Configuration of ADC: */
562 /* - resolution Init.Resolution */
563 /* - data alignment Init.DataAlign */
564 /* - external trigger to start conversion Init.ExternalTrigConv */
565 /* - external trigger polarity Init.ExternalTrigConvEdge */
566 /* - continuous conversion mode Init.ContinuousConvMode */
567 /* - overrun Init.Overrun */
568 /* - discontinuous mode Init.DiscontinuousConvMode */
569 /* - discontinuous mode channel count Init.NbrOfDiscConversion */
570 tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
571 hadc->Init.Overrun |
572 hadc->Init.DataAlign |
573 hadc->Init.Resolution |
574 ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode));
575
576 if (hadc->Init.DiscontinuousConvMode == ENABLE)
577 {
578 tmpCFGR |= ADC_CFGR_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion);
579 }
580
581 /* Enable external trigger if trigger selection is different of software */
582 /* start. */
583 /* Note: This configuration keeps the hardware feature of parameter */
584 /* ExternalTrigConvEdge "trigger edge none" equivalent to */
585 /* software start. */
586 if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
587 {
588 tmpCFGR |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL)
589 | hadc->Init.ExternalTrigConvEdge
590 );
591 }
592
593 /* Update Configuration Register CFGR */
594 MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmpCFGR);
595
596 /* Configuration of sampling mode */
597 MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_BULB | ADC_CFGR2_SMPTRIG, hadc->Init.SamplingMode);
598
599 /* Parameters update conditioned to ADC state: */
600 /* Parameters that can be updated when ADC is disabled or enabled without */
601 /* conversion on going on regular and injected groups: */
602 /* - Gain Compensation Init.GainCompensation */
603 /* - DMA continuous request Init.DMAContinuousRequests */
604 /* - LowPowerAutoWait feature Init.LowPowerAutoWait */
605 /* - Oversampling parameters Init.Oversampling */
606 tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
607 tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
608 if ((tmp_adc_is_conversion_on_going_regular == 0UL)
609 && (tmp_adc_is_conversion_on_going_injected == 0UL)
610 )
611 {
612 tmpCFGR = (ADC_CFGR_DFSDM(hadc) |
613 ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) |
614 ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests));
615
616 MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmpCFGR);
617
618 if (hadc->Init.GainCompensation != 0UL)
619 {
620 SET_BIT(hadc->Instance->CFGR2, ADC_CFGR2_GCOMP);
621 MODIFY_REG(hadc->Instance->GCOMP, ADC_GCOMP_GCOMPCOEFF, hadc->Init.GainCompensation);
622 }
623 else
624 {
625 CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_GCOMP);
626 MODIFY_REG(hadc->Instance->GCOMP, ADC_GCOMP_GCOMPCOEFF, 0UL);
627 }
628
629 if (hadc->Init.OversamplingMode == ENABLE)
630 {
631 assert_param(IS_ADC_OVERSAMPLING_RATIO(hadc->Init.Oversampling.Ratio));
632 assert_param(IS_ADC_RIGHT_BIT_SHIFT(hadc->Init.Oversampling.RightBitShift));
633 assert_param(IS_ADC_TRIGGERED_OVERSAMPLING_MODE(hadc->Init.Oversampling.TriggeredMode));
634 assert_param(IS_ADC_REGOVERSAMPLING_MODE(hadc->Init.Oversampling.OversamplingStopReset));
635
636 /* Configuration of Oversampler: */
637 /* - Oversampling Ratio */
638 /* - Right bit shift */
639 /* - Triggered mode */
640 /* - Oversampling mode (continued/resumed) */
641 MODIFY_REG(hadc->Instance->CFGR2,
642 ADC_CFGR2_OVSR |
643 ADC_CFGR2_OVSS |
644 ADC_CFGR2_TROVS |
645 ADC_CFGR2_ROVSM,
646 ADC_CFGR2_ROVSE |
647 hadc->Init.Oversampling.Ratio |
648 hadc->Init.Oversampling.RightBitShift |
649 hadc->Init.Oversampling.TriggeredMode |
650 hadc->Init.Oversampling.OversamplingStopReset
651 );
652 }
653 else
654 {
655 /* Disable ADC oversampling scope on ADC group regular */
656 CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE);
657 }
658
659 }
660
661 /* Configuration of regular group sequencer: */
662 /* - if scan mode is disabled, regular channels sequence length is set to */
663 /* 0x00: 1 channel converted (channel on regular rank 1) */
664 /* Parameter "NbrOfConversion" is discarded. */
665 /* Note: Scan mode is not present by hardware on this device, but */
666 /* emulated by software for alignment over all STM32 devices. */
667 /* - if scan mode is enabled, regular channels sequence length is set to */
668 /* parameter "NbrOfConversion". */
669
670 if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE)
671 {
672 /* Set number of ranks in regular group sequencer */
673 MODIFY_REG(hadc->Instance->SQR1, ADC_SQR1_L, (hadc->Init.NbrOfConversion - (uint8_t)1));
674 }
675 else
676 {
677 CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L);
678 }
679
680 /* Initialize the ADC state */
681 /* Clear HAL_ADC_STATE_BUSY_INTERNAL bit, set HAL_ADC_STATE_READY bit */
682 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY);
683 }
684 else
685 {
686 /* Update ADC state machine to error */
687 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
688
689 tmp_hal_status = HAL_ERROR;
690 }
691
692 /* Return function status */
693 return tmp_hal_status;
694 }
695
696 /**
697 * @brief Deinitialize the ADC peripheral registers to their default reset
698 * values, with deinitialization of the ADC MSP.
699 * @note For devices with several ADCs: reset of ADC common registers is done
700 * only if all ADCs sharing the same common group are disabled.
701 * (function "HAL_ADC_MspDeInit()" is also called under the same conditions:
702 * all ADC instances use the same core clock at RCC level, disabling
703 * the core clock reset all ADC instances).
704 * If this is not the case, reset of these common parameters reset is
705 * bypassed without error reporting: it can be the intended behavior in
706 * case of reset of a single ADC while the other ADCs sharing the same
707 * common group is still running.
708 * @note By default, HAL_ADC_DeInit() set ADC in mode deep power-down:
709 * this saves more power by reducing leakage currents
710 * and is particularly interesting before entering MCU low-power modes.
711 * @param hadc ADC handle
712 * @retval HAL status
713 */
HAL_ADC_DeInit(ADC_HandleTypeDef * hadc)714 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc)
715 {
716 HAL_StatusTypeDef tmp_hal_status;
717
718 /* Check ADC handle */
719 if (hadc == NULL)
720 {
721 return HAL_ERROR;
722 }
723
724 /* Check the parameters */
725 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
726
727 /* Set ADC state */
728 SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
729
730 /* Stop potential conversion on going */
731 tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
732
733 /* Disable ADC peripheral if conversions are effectively stopped */
734 /* Flush register JSQR: reset the queue sequencer when injected */
735 /* queue sequencer is enabled and ADC disabled. */
736 /* The software and hardware triggers of the injected sequence are both */
737 /* internally disabled just after the completion of the last valid */
738 /* injected sequence. */
739 SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQM);
740
741 /* Disable ADC peripheral if conversions are effectively stopped */
742 if (tmp_hal_status == HAL_OK)
743 {
744 /* Disable the ADC peripheral */
745 tmp_hal_status = ADC_Disable(hadc);
746
747 /* Check if ADC is effectively disabled */
748 if (tmp_hal_status == HAL_OK)
749 {
750 /* Change ADC state */
751 hadc->State = HAL_ADC_STATE_READY;
752 }
753 }
754
755 /* Note: HAL ADC deInit is done independently of ADC conversion stop */
756 /* and disable return status. In case of status fail, attempt to */
757 /* perform deinitialization anyway and it is up user code in */
758 /* in HAL_ADC_MspDeInit() to reset the ADC peripheral using */
759 /* system RCC hard reset. */
760
761 /* ========== Reset ADC registers ========== */
762 /* Reset register IER */
763 __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_AWD3 | ADC_IT_AWD2 | ADC_IT_AWD1 |
764 ADC_IT_JQOVF | ADC_IT_OVR |
765 ADC_IT_JEOS | ADC_IT_JEOC |
766 ADC_IT_EOS | ADC_IT_EOC |
767 ADC_IT_EOSMP | ADC_IT_RDY));
768
769 /* Reset register ISR */
770 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD3 | ADC_FLAG_AWD2 | ADC_FLAG_AWD1 |
771 ADC_FLAG_JQOVF | ADC_FLAG_OVR |
772 ADC_FLAG_JEOS | ADC_FLAG_JEOC |
773 ADC_FLAG_EOS | ADC_FLAG_EOC |
774 ADC_FLAG_EOSMP | ADC_FLAG_RDY));
775
776 /* Reset register CR */
777 /* Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART,
778 ADC_CR_ADCAL, ADC_CR_ADDIS and ADC_CR_ADEN are in access mode "read-set":
779 no direct reset applicable.
780 Update CR register to reset value where doable by software */
781 CLEAR_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN | ADC_CR_ADCALDIF);
782 SET_BIT(hadc->Instance->CR, ADC_CR_DEEPPWD);
783
784 /* Reset register CFGR */
785 CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_FIELDS);
786 SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS);
787
788 /* Reset register CFGR2 */
789 CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSM | ADC_CFGR2_TROVS | ADC_CFGR2_OVSS |
790 ADC_CFGR2_OVSR | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE);
791
792 /* Reset register SMPR1 */
793 CLEAR_BIT(hadc->Instance->SMPR1, ADC_SMPR1_FIELDS);
794
795 /* Reset register SMPR2 */
796 CLEAR_BIT(hadc->Instance->SMPR2, ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | ADC_SMPR2_SMP16 |
797 ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | ADC_SMPR2_SMP13 |
798 ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | ADC_SMPR2_SMP10);
799
800 /* Reset register TR1 */
801 CLEAR_BIT(hadc->Instance->TR1, ADC_TR1_HT1 | ADC_TR1_LT1);
802
803 /* Reset register TR2 */
804 CLEAR_BIT(hadc->Instance->TR2, ADC_TR2_HT2 | ADC_TR2_LT2);
805
806 /* Reset register TR3 */
807 CLEAR_BIT(hadc->Instance->TR3, ADC_TR3_HT3 | ADC_TR3_LT3);
808
809 /* Reset register SQR1 */
810 CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2 |
811 ADC_SQR1_SQ1 | ADC_SQR1_L);
812
813 /* Reset register SQR2 */
814 CLEAR_BIT(hadc->Instance->SQR2, ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7 |
815 ADC_SQR2_SQ6 | ADC_SQR2_SQ5);
816
817 /* Reset register SQR3 */
818 CLEAR_BIT(hadc->Instance->SQR3, ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12 |
819 ADC_SQR3_SQ11 | ADC_SQR3_SQ10);
820
821 /* Reset register SQR4 */
822 CLEAR_BIT(hadc->Instance->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15);
823
824 /* Register JSQR was reset when the ADC was disabled */
825
826 /* Reset register DR */
827 /* bits in access mode read only, no direct reset applicable*/
828
829 /* Reset register OFR1 */
830 CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1);
831 /* Reset register OFR2 */
832 CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_OFFSET2_EN | ADC_OFR2_OFFSET2_CH | ADC_OFR2_OFFSET2);
833 /* Reset register OFR3 */
834 CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_OFFSET3_EN | ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3);
835 /* Reset register OFR4 */
836 CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_OFFSET4_EN | ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4);
837
838 /* Reset registers JDR1, JDR2, JDR3, JDR4 */
839 /* bits in access mode read only, no direct reset applicable*/
840
841 /* Reset register AWD2CR */
842 CLEAR_BIT(hadc->Instance->AWD2CR, ADC_AWD2CR_AWD2CH);
843
844 /* Reset register AWD3CR */
845 CLEAR_BIT(hadc->Instance->AWD3CR, ADC_AWD3CR_AWD3CH);
846
847 /* Reset register DIFSEL */
848 CLEAR_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_DIFSEL);
849
850 /* Reset register CALFACT */
851 CLEAR_BIT(hadc->Instance->CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S);
852
853
854 /* ========== Reset common ADC registers ========== */
855
856 /* Software is allowed to change common parameters only when all the other
857 ADCs are disabled. */
858 if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
859 {
860 /* Reset configuration of ADC common register CCR:
861 - clock mode: CKMODE, PRESCEN
862 - multimode related parameters (when this feature is available): MDMA,
863 DMACFG, DELAY, DUAL (set by HAL_ADCEx_MultiModeConfigChannel() API)
864 - internal measurement paths: Vbat, temperature sensor, Vref (set into
865 HAL_ADC_ConfigChannel() or HAL_ADCEx_InjectedConfigChannel() )
866 */
867 ADC_CLEAR_COMMON_CONTROL_REGISTER(hadc);
868
869 /* ========== Hard reset ADC peripheral ========== */
870 /* Performs a global reset of the entire ADC peripherals instances */
871 /* sharing the same common ADC instance: ADC state is forced to */
872 /* a similar state as after device power-on. */
873 /* Note: A possible implementation is to add RCC bus reset of ADC */
874 /* (for example, using macro */
875 /* __HAL_RCC_ADC..._FORCE_RESET()/..._RELEASE_RESET()/..._CLK_DISABLE()) */
876 /* in function "void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc)": */
877 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
878 if (hadc->MspDeInitCallback == NULL)
879 {
880 hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */
881 }
882
883 /* DeInit the low level hardware */
884 hadc->MspDeInitCallback(hadc);
885 #else
886 /* DeInit the low level hardware */
887 HAL_ADC_MspDeInit(hadc);
888 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
889 }
890
891 /* Set ADC error code to none */
892 ADC_CLEAR_ERRORCODE(hadc);
893
894 /* Reset injected channel configuration parameters */
895 hadc->InjectionConfig.ContextQueue = 0;
896 hadc->InjectionConfig.ChannelCount = 0;
897
898 /* Set ADC state */
899 hadc->State = HAL_ADC_STATE_RESET;
900
901 /* Process unlocked */
902 __HAL_UNLOCK(hadc);
903
904 /* Return function status */
905 return tmp_hal_status;
906 }
907
908 /**
909 * @brief Initialize the ADC MSP.
910 * @param hadc ADC handle
911 * @retval None
912 */
HAL_ADC_MspInit(ADC_HandleTypeDef * hadc)913 __weak void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc)
914 {
915 /* Prevent unused argument(s) compilation warning */
916 UNUSED(hadc);
917
918 /* NOTE : This function should not be modified. When the callback is needed,
919 function HAL_ADC_MspInit must be implemented in the user file.
920 */
921 }
922
923 /**
924 * @brief DeInitialize the ADC MSP.
925 * @param hadc ADC handle
926 * @note All ADC instances use the same core clock at RCC level, disabling
927 * the core clock reset all ADC instances).
928 * @retval None
929 */
HAL_ADC_MspDeInit(ADC_HandleTypeDef * hadc)930 __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc)
931 {
932 /* Prevent unused argument(s) compilation warning */
933 UNUSED(hadc);
934
935 /* NOTE : This function should not be modified. When the callback is needed,
936 function HAL_ADC_MspDeInit must be implemented in the user file.
937 */
938 }
939
940 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
941 /**
942 * @brief Register a User ADC Callback
943 * To be used instead of the weak predefined callback
944 * @param hadc Pointer to a ADC_HandleTypeDef structure that contains
945 * the configuration information for the specified ADC.
946 * @param CallbackID ID of the callback to be registered
947 * This parameter can be one of the following values:
948 * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID
949 * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion DMA half-transfer callback ID
950 * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID
951 * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID
952 * @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID
953 * @arg @ref HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID ADC group injected context queue overflow callback ID
954 * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID ADC analog watchdog 2 callback ID
955 * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID ADC analog watchdog 3 callback ID
956 * @arg @ref HAL_ADC_END_OF_SAMPLING_CB_ID ADC end of sampling callback ID
957 * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID
958 * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID
959 * @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID
960 * @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID
961 * @param pCallback pointer to the Callback function
962 * @retval HAL status
963 */
HAL_ADC_RegisterCallback(ADC_HandleTypeDef * hadc,HAL_ADC_CallbackIDTypeDef CallbackID,pADC_CallbackTypeDef pCallback)964 HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID,
965 pADC_CallbackTypeDef pCallback)
966 {
967 HAL_StatusTypeDef status = HAL_OK;
968
969 if (pCallback == NULL)
970 {
971 /* Update the error code */
972 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
973
974 return HAL_ERROR;
975 }
976
977 if ((hadc->State & HAL_ADC_STATE_READY) != 0UL)
978 {
979 switch (CallbackID)
980 {
981 case HAL_ADC_CONVERSION_COMPLETE_CB_ID :
982 hadc->ConvCpltCallback = pCallback;
983 break;
984
985 case HAL_ADC_CONVERSION_HALF_CB_ID :
986 hadc->ConvHalfCpltCallback = pCallback;
987 break;
988
989 case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID :
990 hadc->LevelOutOfWindowCallback = pCallback;
991 break;
992
993 case HAL_ADC_ERROR_CB_ID :
994 hadc->ErrorCallback = pCallback;
995 break;
996
997 case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID :
998 hadc->InjectedConvCpltCallback = pCallback;
999 break;
1000
1001 case HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID :
1002 hadc->InjectedQueueOverflowCallback = pCallback;
1003 break;
1004
1005 case HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID :
1006 hadc->LevelOutOfWindow2Callback = pCallback;
1007 break;
1008
1009 case HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID :
1010 hadc->LevelOutOfWindow3Callback = pCallback;
1011 break;
1012
1013 case HAL_ADC_END_OF_SAMPLING_CB_ID :
1014 hadc->EndOfSamplingCallback = pCallback;
1015 break;
1016
1017 case HAL_ADC_MSPINIT_CB_ID :
1018 hadc->MspInitCallback = pCallback;
1019 break;
1020
1021 case HAL_ADC_MSPDEINIT_CB_ID :
1022 hadc->MspDeInitCallback = pCallback;
1023 break;
1024
1025 default :
1026 /* Update the error code */
1027 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
1028
1029 /* Return error status */
1030 status = HAL_ERROR;
1031 break;
1032 }
1033 }
1034 else if (HAL_ADC_STATE_RESET == hadc->State)
1035 {
1036 switch (CallbackID)
1037 {
1038 case HAL_ADC_MSPINIT_CB_ID :
1039 hadc->MspInitCallback = pCallback;
1040 break;
1041
1042 case HAL_ADC_MSPDEINIT_CB_ID :
1043 hadc->MspDeInitCallback = pCallback;
1044 break;
1045
1046 default :
1047 /* Update the error code */
1048 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
1049
1050 /* Return error status */
1051 status = HAL_ERROR;
1052 break;
1053 }
1054 }
1055 else
1056 {
1057 /* Update the error code */
1058 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
1059
1060 /* Return error status */
1061 status = HAL_ERROR;
1062 }
1063
1064 return status;
1065 }
1066
1067 /**
1068 * @brief Unregister a ADC Callback
1069 * ADC callback is redirected to the weak predefined callback
1070 * @param hadc Pointer to a ADC_HandleTypeDef structure that contains
1071 * the configuration information for the specified ADC.
1072 * @param CallbackID ID of the callback to be unregistered
1073 * This parameter can be one of the following values:
1074 * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID
1075 * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion DMA half-transfer callback ID
1076 * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID
1077 * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID
1078 * @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID
1079 * @arg @ref HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID ADC group injected context queue overflow callback ID
1080 * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID ADC analog watchdog 2 callback ID
1081 * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID ADC analog watchdog 3 callback ID
1082 * @arg @ref HAL_ADC_END_OF_SAMPLING_CB_ID ADC end of sampling callback ID
1083 * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID
1084 * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID
1085 * @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID
1086 * @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID
1087 * @retval HAL status
1088 */
HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef * hadc,HAL_ADC_CallbackIDTypeDef CallbackID)1089 HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID)
1090 {
1091 HAL_StatusTypeDef status = HAL_OK;
1092
1093 if ((hadc->State & HAL_ADC_STATE_READY) != 0UL)
1094 {
1095 switch (CallbackID)
1096 {
1097 case HAL_ADC_CONVERSION_COMPLETE_CB_ID :
1098 hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback;
1099 break;
1100
1101 case HAL_ADC_CONVERSION_HALF_CB_ID :
1102 hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback;
1103 break;
1104
1105 case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID :
1106 hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback;
1107 break;
1108
1109 case HAL_ADC_ERROR_CB_ID :
1110 hadc->ErrorCallback = HAL_ADC_ErrorCallback;
1111 break;
1112
1113 case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID :
1114 hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback;
1115 break;
1116
1117 case HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID :
1118 hadc->InjectedQueueOverflowCallback = HAL_ADCEx_InjectedQueueOverflowCallback;
1119 break;
1120
1121 case HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID :
1122 hadc->LevelOutOfWindow2Callback = HAL_ADCEx_LevelOutOfWindow2Callback;
1123 break;
1124
1125 case HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID :
1126 hadc->LevelOutOfWindow3Callback = HAL_ADCEx_LevelOutOfWindow3Callback;
1127 break;
1128
1129 case HAL_ADC_END_OF_SAMPLING_CB_ID :
1130 hadc->EndOfSamplingCallback = HAL_ADCEx_EndOfSamplingCallback;
1131 break;
1132
1133 case HAL_ADC_MSPINIT_CB_ID :
1134 hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */
1135 break;
1136
1137 case HAL_ADC_MSPDEINIT_CB_ID :
1138 hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */
1139 break;
1140
1141 default :
1142 /* Update the error code */
1143 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
1144
1145 /* Return error status */
1146 status = HAL_ERROR;
1147 break;
1148 }
1149 }
1150 else if (HAL_ADC_STATE_RESET == hadc->State)
1151 {
1152 switch (CallbackID)
1153 {
1154 case HAL_ADC_MSPINIT_CB_ID :
1155 hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */
1156 break;
1157
1158 case HAL_ADC_MSPDEINIT_CB_ID :
1159 hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */
1160 break;
1161
1162 default :
1163 /* Update the error code */
1164 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
1165
1166 /* Return error status */
1167 status = HAL_ERROR;
1168 break;
1169 }
1170 }
1171 else
1172 {
1173 /* Update the error code */
1174 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
1175
1176 /* Return error status */
1177 status = HAL_ERROR;
1178 }
1179
1180 return status;
1181 }
1182
1183 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
1184
1185 /**
1186 * @}
1187 */
1188
1189 /** @defgroup ADC_Exported_Functions_Group2 ADC Input and Output operation functions
1190 * @brief ADC IO operation functions
1191 *
1192 @verbatim
1193 ===============================================================================
1194 ##### IO operation functions #####
1195 ===============================================================================
1196 [..] This section provides functions allowing to:
1197 (+) Start conversion of regular group.
1198 (+) Stop conversion of regular group.
1199 (+) Poll for conversion complete on regular group.
1200 (+) Poll for conversion event.
1201 (+) Get result of regular channel conversion.
1202 (+) Start conversion of regular group and enable interruptions.
1203 (+) Stop conversion of regular group and disable interruptions.
1204 (+) Handle ADC interrupt request
1205 (+) Start conversion of regular group and enable DMA transfer.
1206 (+) Stop conversion of regular group and disable ADC DMA transfer.
1207 @endverbatim
1208 * @{
1209 */
1210
1211 /**
1212 * @brief Enable ADC, start conversion of regular group.
1213 * @note Interruptions enabled in this function: None.
1214 * @note Case of multimode enabled (when multimode feature is available):
1215 * if ADC is Slave, ADC is enabled but conversion is not started,
1216 * if ADC is master, ADC is enabled and multimode conversion is started.
1217 * @param hadc ADC handle
1218 * @retval HAL status
1219 */
HAL_ADC_Start(ADC_HandleTypeDef * hadc)1220 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc)
1221 {
1222 HAL_StatusTypeDef tmp_hal_status;
1223 #if defined(ADC_MULTIMODE_SUPPORT)
1224 const ADC_TypeDef *tmpADC_Master;
1225 uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
1226 #endif
1227
1228 /* Check the parameters */
1229 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1230
1231 /* Perform ADC enable and conversion start if no conversion is on going */
1232 if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
1233 {
1234 /* Process locked */
1235 __HAL_LOCK(hadc);
1236
1237 /* Enable the ADC peripheral */
1238 tmp_hal_status = ADC_Enable(hadc);
1239
1240 /* Start conversion if ADC is effectively enabled */
1241 if (tmp_hal_status == HAL_OK)
1242 {
1243 /* Set ADC state */
1244 /* - Clear state bitfield related to regular group conversion results */
1245 /* - Set state bitfield related to regular operation */
1246 ADC_STATE_CLR_SET(hadc->State,
1247 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
1248 HAL_ADC_STATE_REG_BUSY);
1249
1250 #if defined(ADC_MULTIMODE_SUPPORT)
1251 /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
1252 - if ADC instance is master or if multimode feature is not available
1253 - if multimode setting is disabled (ADC instance slave in independent mode) */
1254 if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
1255 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
1256 )
1257 {
1258 CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
1259 }
1260 #endif
1261
1262 /* Set ADC error code */
1263 /* Check if a conversion is on going on ADC group injected */
1264 if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
1265 {
1266 /* Reset ADC error code fields related to regular conversions only */
1267 CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
1268 }
1269 else
1270 {
1271 /* Reset all ADC error code fields */
1272 ADC_CLEAR_ERRORCODE(hadc);
1273 }
1274
1275 /* Clear ADC group regular conversion flag and overrun flag */
1276 /* (To ensure of no unknown state from potential previous ADC operations) */
1277 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
1278
1279 /* Process unlocked */
1280 /* Unlock before starting ADC conversions: in case of potential */
1281 /* interruption, to let the process to ADC IRQ Handler. */
1282 __HAL_UNLOCK(hadc);
1283
1284 /* Enable conversion of regular group. */
1285 /* If software start has been selected, conversion starts immediately. */
1286 /* If external trigger has been selected, conversion will start at next */
1287 /* trigger event. */
1288 /* Case of multimode enabled (when multimode feature is available): */
1289 /* - if ADC is slave and dual regular conversions are enabled, ADC is */
1290 /* enabled only (conversion is not started), */
1291 /* - if ADC is master, ADC is enabled and conversion is started. */
1292 #if defined(ADC_MULTIMODE_SUPPORT)
1293 if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
1294 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
1295 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
1296 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
1297 )
1298 {
1299 /* ADC instance is not a multimode slave instance with multimode regular conversions enabled */
1300 if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != 0UL)
1301 {
1302 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
1303 }
1304
1305 /* Start ADC group regular conversion */
1306 LL_ADC_REG_StartConversion(hadc->Instance);
1307 }
1308 else
1309 {
1310 /* ADC instance is a multimode slave instance with multimode regular conversions enabled */
1311 SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
1312 /* if Master ADC JAUTO bit is set, update Slave State in setting
1313 HAL_ADC_STATE_INJ_BUSY bit and in resetting HAL_ADC_STATE_INJ_EOC bit */
1314 tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
1315 if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != 0UL)
1316 {
1317 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
1318 }
1319
1320 }
1321 #else
1322 if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != 0UL)
1323 {
1324 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
1325 }
1326
1327 /* Start ADC group regular conversion */
1328 LL_ADC_REG_StartConversion(hadc->Instance);
1329 #endif
1330 }
1331 else
1332 {
1333 /* Process unlocked */
1334 __HAL_UNLOCK(hadc);
1335 }
1336 }
1337 else
1338 {
1339 tmp_hal_status = HAL_BUSY;
1340 }
1341
1342 /* Return function status */
1343 return tmp_hal_status;
1344 }
1345
1346 /**
1347 * @brief Stop ADC conversion of regular group (and injected channels in
1348 * case of auto_injection mode), disable ADC peripheral.
1349 * @note: ADC peripheral disable is forcing stop of potential
1350 * conversion on injected group. If injected group is under use, it
1351 * should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
1352 * @param hadc ADC handle
1353 * @retval HAL status.
1354 */
HAL_ADC_Stop(ADC_HandleTypeDef * hadc)1355 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc)
1356 {
1357 HAL_StatusTypeDef tmp_hal_status;
1358
1359 /* Check the parameters */
1360 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1361
1362 /* Process locked */
1363 __HAL_LOCK(hadc);
1364
1365 /* 1. Stop potential conversion on going, on ADC groups regular and injected */
1366 tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
1367
1368 /* Disable ADC peripheral if conversions are effectively stopped */
1369 if (tmp_hal_status == HAL_OK)
1370 {
1371 /* 2. Disable the ADC peripheral */
1372 tmp_hal_status = ADC_Disable(hadc);
1373
1374 /* Check if ADC is effectively disabled */
1375 if (tmp_hal_status == HAL_OK)
1376 {
1377 /* Set ADC state */
1378 ADC_STATE_CLR_SET(hadc->State,
1379 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
1380 HAL_ADC_STATE_READY);
1381 }
1382 }
1383
1384 /* Process unlocked */
1385 __HAL_UNLOCK(hadc);
1386
1387 /* Return function status */
1388 return tmp_hal_status;
1389 }
1390
1391 /**
1392 * @brief Wait for regular group conversion to be completed.
1393 * @note ADC conversion flags EOS (end of sequence) and EOC (end of
1394 * conversion) are cleared by this function, with an exception:
1395 * if low power feature "LowPowerAutoWait" is enabled, flags are
1396 * not cleared to not interfere with this feature until data register
1397 * is read using function HAL_ADC_GetValue().
1398 * @note This function cannot be used in a particular setup: ADC configured
1399 * in DMA mode and polling for end of each conversion (ADC init
1400 * parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV).
1401 * In this case, DMA resets the flag EOC and polling cannot be
1402 * performed on each conversion. Nevertheless, polling can still
1403 * be performed on the complete sequence (ADC init
1404 * parameter "EOCSelection" set to ADC_EOC_SEQ_CONV).
1405 * @param hadc ADC handle
1406 * @param Timeout Timeout value in millisecond.
1407 * @retval HAL status
1408 */
HAL_ADC_PollForConversion(ADC_HandleTypeDef * hadc,uint32_t Timeout)1409 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout)
1410 {
1411 uint32_t tickstart;
1412 uint32_t tmp_Flag_End;
1413 uint32_t tmp_cfgr;
1414 #if defined(ADC_MULTIMODE_SUPPORT)
1415 const ADC_TypeDef *tmpADC_Master;
1416 uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
1417 #endif
1418
1419 /* Check the parameters */
1420 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1421
1422 /* If end of conversion selected to end of sequence conversions */
1423 if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
1424 {
1425 tmp_Flag_End = ADC_FLAG_EOS;
1426 }
1427 /* If end of conversion selected to end of unitary conversion */
1428 else /* ADC_EOC_SINGLE_CONV */
1429 {
1430 /* Verification that ADC configuration is compliant with polling for */
1431 /* each conversion: */
1432 /* Particular case is ADC configured in DMA mode and ADC sequencer with */
1433 /* several ranks and polling for end of each conversion. */
1434 /* For code simplicity sake, this particular case is generalized to */
1435 /* ADC configured in DMA mode and and polling for end of each conversion. */
1436 #if defined(ADC_MULTIMODE_SUPPORT)
1437 if ((tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
1438 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
1439 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
1440 )
1441 {
1442 /* Check ADC DMA mode in independent mode on ADC group regular */
1443 if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN) != 0UL)
1444 {
1445 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
1446 return HAL_ERROR;
1447 }
1448 else
1449 {
1450 tmp_Flag_End = (ADC_FLAG_EOC);
1451 }
1452 }
1453 else
1454 {
1455 /* Check ADC DMA mode in multimode on ADC group regular */
1456 if (LL_ADC_GetMultiDMATransfer(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) != LL_ADC_MULTI_REG_DMA_EACH_ADC)
1457 {
1458 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
1459 return HAL_ERROR;
1460 }
1461 else
1462 {
1463 tmp_Flag_End = (ADC_FLAG_EOC);
1464 }
1465 }
1466 #else
1467 /* Check ADC DMA mode */
1468 if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN) != 0UL)
1469 {
1470 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
1471 return HAL_ERROR;
1472 }
1473 else
1474 {
1475 tmp_Flag_End = (ADC_FLAG_EOC);
1476 }
1477 #endif
1478 }
1479
1480 /* Get tick count */
1481 tickstart = HAL_GetTick();
1482
1483 /* Wait until End of unitary conversion or sequence conversions flag is raised */
1484 while ((hadc->Instance->ISR & tmp_Flag_End) == 0UL)
1485 {
1486 /* Check if timeout is disabled (set to infinite wait) */
1487 if (Timeout != HAL_MAX_DELAY)
1488 {
1489 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
1490 {
1491 /* New check to avoid false timeout detection in case of preemption */
1492 if ((hadc->Instance->ISR & tmp_Flag_End) == 0UL)
1493 {
1494 /* Update ADC state machine to timeout */
1495 SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
1496
1497 /* Process unlocked */
1498 __HAL_UNLOCK(hadc);
1499
1500 return HAL_TIMEOUT;
1501 }
1502 }
1503 }
1504 }
1505
1506 /* Update ADC state machine */
1507 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
1508
1509 /* Determine whether any further conversion upcoming on group regular */
1510 /* by external trigger, continuous mode or scan sequence on going. */
1511 if ((LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL)
1512 && (hadc->Init.ContinuousConvMode == DISABLE)
1513 )
1514 {
1515 /* Check whether end of sequence is reached */
1516 if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS))
1517 {
1518 /* Set ADC state */
1519 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
1520
1521 if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL)
1522 {
1523 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
1524 }
1525 }
1526 }
1527
1528 /* Get relevant register CFGR in ADC instance of ADC master or slave */
1529 /* in function of multimode state (for devices with multimode */
1530 /* available). */
1531 #if defined(ADC_MULTIMODE_SUPPORT)
1532 if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
1533 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
1534 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
1535 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
1536 )
1537 {
1538 /* Retrieve handle ADC CFGR register */
1539 tmp_cfgr = READ_REG(hadc->Instance->CFGR);
1540 }
1541 else
1542 {
1543 /* Retrieve Master ADC CFGR register */
1544 tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
1545 tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
1546 }
1547 #else
1548 /* Retrieve handle ADC CFGR register */
1549 tmp_cfgr = READ_REG(hadc->Instance->CFGR);
1550 #endif
1551
1552 /* Clear polled flag */
1553 if (tmp_Flag_End == ADC_FLAG_EOS)
1554 {
1555 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOS);
1556 }
1557 else
1558 {
1559 /* Clear end of conversion EOC flag of regular group if low power feature */
1560 /* "LowPowerAutoWait " is disabled, to not interfere with this feature */
1561 /* until data register is read using function HAL_ADC_GetValue(). */
1562 if (READ_BIT(tmp_cfgr, ADC_CFGR_AUTDLY) == 0UL)
1563 {
1564 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS));
1565 }
1566 }
1567
1568 /* Return function status */
1569 return HAL_OK;
1570 }
1571
1572 /**
1573 * @brief Poll for ADC event.
1574 * @param hadc ADC handle
1575 * @param EventType the ADC event type.
1576 * This parameter can be one of the following values:
1577 * @arg @ref ADC_EOSMP_EVENT ADC End of Sampling event
1578 * @arg @ref ADC_AWD1_EVENT ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 devices)
1579 * @arg @ref ADC_AWD2_EVENT ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 families)
1580 * @arg @ref ADC_AWD3_EVENT ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 families)
1581 * @arg @ref ADC_OVR_EVENT ADC Overrun event
1582 * @arg @ref ADC_JQOVF_EVENT ADC Injected context queue overflow event
1583 * @param Timeout Timeout value in millisecond.
1584 * @note The relevant flag is cleared if found to be set, except for ADC_FLAG_OVR.
1585 * Indeed, the latter is reset only if hadc->Init.Overrun field is set
1586 * to ADC_OVR_DATA_OVERWRITTEN. Otherwise, data register may be potentially overwritten
1587 * by a new converted data as soon as OVR is cleared.
1588 * To reset OVR flag once the preserved data is retrieved, the user can resort
1589 * to macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
1590 * @retval HAL status
1591 */
HAL_ADC_PollForEvent(ADC_HandleTypeDef * hadc,uint32_t EventType,uint32_t Timeout)1592 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout)
1593 {
1594 uint32_t tickstart;
1595
1596 /* Check the parameters */
1597 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1598 assert_param(IS_ADC_EVENT_TYPE(EventType));
1599
1600 /* Get tick count */
1601 tickstart = HAL_GetTick();
1602
1603 /* Check selected event flag */
1604 while (__HAL_ADC_GET_FLAG(hadc, EventType) == 0UL)
1605 {
1606 /* Check if timeout is disabled (set to infinite wait) */
1607 if (Timeout != HAL_MAX_DELAY)
1608 {
1609 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
1610 {
1611 /* New check to avoid false timeout detection in case of preemption */
1612 if (__HAL_ADC_GET_FLAG(hadc, EventType) == 0UL)
1613 {
1614 /* Update ADC state machine to timeout */
1615 SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
1616
1617 /* Process unlocked */
1618 __HAL_UNLOCK(hadc);
1619
1620 return HAL_TIMEOUT;
1621 }
1622 }
1623 }
1624 }
1625
1626 switch (EventType)
1627 {
1628 /* End Of Sampling event */
1629 case ADC_EOSMP_EVENT:
1630 /* Set ADC state */
1631 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP);
1632
1633 /* Clear the End Of Sampling flag */
1634 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP);
1635
1636 break;
1637
1638 /* Analog watchdog (level out of window) event */
1639 /* Note: In case of several analog watchdog enabled, if needed to know */
1640 /* which one triggered and on which ADCx, test ADC state of analog watchdog */
1641 /* flags HAL_ADC_STATE_AWD1/2/3 using function "HAL_ADC_GetState()". */
1642 /* For example: */
1643 /* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) " */
1644 /* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD2) != 0UL) " */
1645 /* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD3) != 0UL) " */
1646
1647 /* Check analog watchdog 1 flag */
1648 case ADC_AWD_EVENT:
1649 /* Set ADC state */
1650 SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
1651
1652 /* Clear ADC analog watchdog flag */
1653 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
1654
1655 break;
1656
1657 /* Check analog watchdog 2 flag */
1658 case ADC_AWD2_EVENT:
1659 /* Set ADC state */
1660 SET_BIT(hadc->State, HAL_ADC_STATE_AWD2);
1661
1662 /* Clear ADC analog watchdog flag */
1663 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
1664
1665 break;
1666
1667 /* Check analog watchdog 3 flag */
1668 case ADC_AWD3_EVENT:
1669 /* Set ADC state */
1670 SET_BIT(hadc->State, HAL_ADC_STATE_AWD3);
1671
1672 /* Clear ADC analog watchdog flag */
1673 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
1674
1675 break;
1676
1677 /* Injected context queue overflow event */
1678 case ADC_JQOVF_EVENT:
1679 /* Set ADC state */
1680 SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
1681
1682 /* Set ADC error code to Injected context queue overflow */
1683 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
1684
1685 /* Clear ADC Injected context queue overflow flag */
1686 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF);
1687
1688 break;
1689
1690 /* Overrun event */
1691 default: /* Case ADC_OVR_EVENT */
1692 /* If overrun is set to overwrite previous data, overrun event is not */
1693 /* considered as an error. */
1694 /* (cf ref manual "Managing conversions without using the DMA and without */
1695 /* overrun ") */
1696 if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
1697 {
1698 /* Set ADC state */
1699 SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
1700
1701 /* Set ADC error code to overrun */
1702 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
1703 }
1704 else
1705 {
1706 /* Clear ADC Overrun flag only if Overrun is set to ADC_OVR_DATA_OVERWRITTEN
1707 otherwise, data register is potentially overwritten by new converted data as soon
1708 as OVR is cleared. */
1709 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
1710 }
1711 break;
1712 }
1713
1714 /* Return function status */
1715 return HAL_OK;
1716 }
1717
1718 /**
1719 * @brief Enable ADC, start conversion of regular group with interruption.
1720 * @note Interruptions enabled in this function according to initialization
1721 * setting : EOC (end of conversion), EOS (end of sequence),
1722 * OVR overrun.
1723 * Each of these interruptions has its dedicated callback function.
1724 * @note Case of multimode enabled (when multimode feature is available):
1725 * HAL_ADC_Start_IT() must be called for ADC Slave first, then for
1726 * ADC Master.
1727 * For ADC Slave, ADC is enabled only (conversion is not started).
1728 * For ADC Master, ADC is enabled and multimode conversion is started.
1729 * @note To guarantee a proper reset of all interruptions once all the needed
1730 * conversions are obtained, HAL_ADC_Stop_IT() must be called to ensure
1731 * a correct stop of the IT-based conversions.
1732 * @note By default, HAL_ADC_Start_IT() does not enable the End Of Sampling
1733 * interruption. If required (e.g. in case of oversampling with trigger
1734 * mode), the user must:
1735 * 1. first clear the EOSMP flag if set with macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP)
1736 * 2. then enable the EOSMP interrupt with macro __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOSMP)
1737 * before calling HAL_ADC_Start_IT().
1738 * @param hadc ADC handle
1739 * @retval HAL status
1740 */
HAL_ADC_Start_IT(ADC_HandleTypeDef * hadc)1741 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc)
1742 {
1743 HAL_StatusTypeDef tmp_hal_status;
1744 #if defined(ADC_MULTIMODE_SUPPORT)
1745 const ADC_TypeDef *tmpADC_Master;
1746 uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
1747 #endif
1748
1749 /* Check the parameters */
1750 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1751
1752 /* Perform ADC enable and conversion start if no conversion is on going */
1753 if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
1754 {
1755 /* Process locked */
1756 __HAL_LOCK(hadc);
1757
1758 /* Enable the ADC peripheral */
1759 tmp_hal_status = ADC_Enable(hadc);
1760
1761 /* Start conversion if ADC is effectively enabled */
1762 if (tmp_hal_status == HAL_OK)
1763 {
1764 /* Set ADC state */
1765 /* - Clear state bitfield related to regular group conversion results */
1766 /* - Set state bitfield related to regular operation */
1767 ADC_STATE_CLR_SET(hadc->State,
1768 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
1769 HAL_ADC_STATE_REG_BUSY);
1770
1771 #if defined(ADC_MULTIMODE_SUPPORT)
1772 /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
1773 - if ADC instance is master or if multimode feature is not available
1774 - if multimode setting is disabled (ADC instance slave in independent mode) */
1775 if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
1776 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
1777 )
1778 {
1779 CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
1780 }
1781 #endif
1782
1783 /* Set ADC error code */
1784 /* Check if a conversion is on going on ADC group injected */
1785 if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) != 0UL)
1786 {
1787 /* Reset ADC error code fields related to regular conversions only */
1788 CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
1789 }
1790 else
1791 {
1792 /* Reset all ADC error code fields */
1793 ADC_CLEAR_ERRORCODE(hadc);
1794 }
1795
1796 /* Clear ADC group regular conversion flag and overrun flag */
1797 /* (To ensure of no unknown state from potential previous ADC operations) */
1798 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
1799
1800 /* Process unlocked */
1801 /* Unlock before starting ADC conversions: in case of potential */
1802 /* interruption, to let the process to ADC IRQ Handler. */
1803 __HAL_UNLOCK(hadc);
1804
1805 /* Disable all interruptions before enabling the desired ones */
1806 __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
1807
1808 /* Enable ADC end of conversion interrupt */
1809 switch (hadc->Init.EOCSelection)
1810 {
1811 case ADC_EOC_SEQ_CONV:
1812 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOS);
1813 break;
1814 /* case ADC_EOC_SINGLE_CONV */
1815 default:
1816 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC);
1817 break;
1818 }
1819
1820 /* Enable ADC overrun interrupt */
1821 /* If hadc->Init.Overrun is set to ADC_OVR_DATA_PRESERVED, only then is
1822 ADC_IT_OVR enabled; otherwise data overwrite is considered as normal
1823 behavior and no CPU time is lost for a non-processed interruption */
1824 if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
1825 {
1826 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
1827 }
1828
1829 /* Enable conversion of regular group. */
1830 /* If software start has been selected, conversion starts immediately. */
1831 /* If external trigger has been selected, conversion will start at next */
1832 /* trigger event. */
1833 /* Case of multimode enabled (when multimode feature is available): */
1834 /* - if ADC is slave and dual regular conversions are enabled, ADC is */
1835 /* enabled only (conversion is not started), */
1836 /* - if ADC is master, ADC is enabled and conversion is started. */
1837 #if defined(ADC_MULTIMODE_SUPPORT)
1838 if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
1839 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
1840 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
1841 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
1842 )
1843 {
1844 /* ADC instance is not a multimode slave instance with multimode regular conversions enabled */
1845 if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != 0UL)
1846 {
1847 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
1848
1849 /* Enable as well injected interruptions in case
1850 HAL_ADCEx_InjectedStart_IT() has not been called beforehand. This
1851 allows to start regular and injected conversions when JAUTO is
1852 set with a single call to HAL_ADC_Start_IT() */
1853 switch (hadc->Init.EOCSelection)
1854 {
1855 case ADC_EOC_SEQ_CONV:
1856 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
1857 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
1858 break;
1859 /* case ADC_EOC_SINGLE_CONV */
1860 default:
1861 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
1862 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
1863 break;
1864 }
1865 }
1866
1867 /* Start ADC group regular conversion */
1868 LL_ADC_REG_StartConversion(hadc->Instance);
1869 }
1870 else
1871 {
1872 /* ADC instance is a multimode slave instance with multimode regular conversions enabled */
1873 SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
1874 /* if Master ADC JAUTO bit is set, Slave injected interruptions
1875 are enabled nevertheless (for same reason as above) */
1876 tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
1877 if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != 0UL)
1878 {
1879 /* First, update Slave State in setting HAL_ADC_STATE_INJ_BUSY bit
1880 and in resetting HAL_ADC_STATE_INJ_EOC bit */
1881 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
1882 /* Next, set Slave injected interruptions */
1883 switch (hadc->Init.EOCSelection)
1884 {
1885 case ADC_EOC_SEQ_CONV:
1886 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
1887 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
1888 break;
1889 /* case ADC_EOC_SINGLE_CONV */
1890 default:
1891 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
1892 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
1893 break;
1894 }
1895 }
1896 }
1897 #else
1898 /* ADC instance is not a multimode slave instance with multimode regular conversions enabled */
1899 if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != 0UL)
1900 {
1901 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
1902
1903 /* Enable as well injected interruptions in case
1904 HAL_ADCEx_InjectedStart_IT() has not been called beforehand. This
1905 allows to start regular and injected conversions when JAUTO is
1906 set with a single call to HAL_ADC_Start_IT() */
1907 switch (hadc->Init.EOCSelection)
1908 {
1909 case ADC_EOC_SEQ_CONV:
1910 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
1911 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
1912 break;
1913 /* case ADC_EOC_SINGLE_CONV */
1914 default:
1915 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
1916 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
1917 break;
1918 }
1919 }
1920
1921 /* Start ADC group regular conversion */
1922 LL_ADC_REG_StartConversion(hadc->Instance);
1923 #endif
1924 }
1925 else
1926 {
1927 /* Process unlocked */
1928 __HAL_UNLOCK(hadc);
1929 }
1930
1931 }
1932 else
1933 {
1934 tmp_hal_status = HAL_BUSY;
1935 }
1936
1937 /* Return function status */
1938 return tmp_hal_status;
1939 }
1940
1941 /**
1942 * @brief Stop ADC conversion of regular group (and injected group in
1943 * case of auto_injection mode), disable interrution of
1944 * end-of-conversion, disable ADC peripheral.
1945 * @param hadc ADC handle
1946 * @retval HAL status.
1947 */
HAL_ADC_Stop_IT(ADC_HandleTypeDef * hadc)1948 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc)
1949 {
1950 HAL_StatusTypeDef tmp_hal_status;
1951
1952 /* Check the parameters */
1953 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1954
1955 /* Process locked */
1956 __HAL_LOCK(hadc);
1957
1958 /* 1. Stop potential conversion on going, on ADC groups regular and injected */
1959 tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
1960
1961 /* Disable ADC peripheral if conversions are effectively stopped */
1962 if (tmp_hal_status == HAL_OK)
1963 {
1964 /* Disable ADC end of conversion interrupt for regular group */
1965 /* Disable ADC overrun interrupt */
1966 __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
1967
1968 /* 2. Disable the ADC peripheral */
1969 tmp_hal_status = ADC_Disable(hadc);
1970
1971 /* Check if ADC is effectively disabled */
1972 if (tmp_hal_status == HAL_OK)
1973 {
1974 /* Set ADC state */
1975 ADC_STATE_CLR_SET(hadc->State,
1976 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
1977 HAL_ADC_STATE_READY);
1978 }
1979 }
1980
1981 /* Process unlocked */
1982 __HAL_UNLOCK(hadc);
1983
1984 /* Return function status */
1985 return tmp_hal_status;
1986 }
1987
1988 /**
1989 * @brief Enable ADC, start conversion of regular group and transfer result through DMA.
1990 * @note Interruptions enabled in this function:
1991 * overrun (if applicable), DMA half transfer, DMA transfer complete.
1992 * Each of these interruptions has its dedicated callback function.
1993 * @note Case of multimode enabled (when multimode feature is available): HAL_ADC_Start_DMA()
1994 * is designed for single-ADC mode only. For multimode, the dedicated
1995 * HAL_ADCEx_MultiModeStart_DMA() function must be used.
1996 * @param hadc ADC handle
1997 * @param pData Destination Buffer address.
1998 * @param Length Number of data to be transferred from ADC peripheral to memory
1999 * @retval HAL status.
2000 */
HAL_ADC_Start_DMA(ADC_HandleTypeDef * hadc,uint32_t * pData,uint32_t Length)2001 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
2002 {
2003 HAL_StatusTypeDef tmp_hal_status;
2004 #if defined(ADC_MULTIMODE_SUPPORT)
2005 uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
2006 #endif
2007
2008 /* Check the parameters */
2009 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
2010
2011 /* Perform ADC enable and conversion start if no conversion is on going */
2012 if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
2013 {
2014 /* Process locked */
2015 __HAL_LOCK(hadc);
2016
2017 #if defined(ADC_MULTIMODE_SUPPORT)
2018 /* Ensure that multimode regular conversions are not enabled. */
2019 /* Otherwise, dedicated API HAL_ADCEx_MultiModeStart_DMA() must be used. */
2020 if ((ADC_IS_INDEPENDENT(hadc) != RESET)
2021 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
2022 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
2023 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
2024 )
2025 #endif /* ADC_MULTIMODE_SUPPORT */
2026 {
2027 /* Enable the ADC peripheral */
2028 tmp_hal_status = ADC_Enable(hadc);
2029
2030 /* Start conversion if ADC is effectively enabled */
2031 if (tmp_hal_status == HAL_OK)
2032 {
2033 /* Set ADC state */
2034 /* - Clear state bitfield related to regular group conversion results */
2035 /* - Set state bitfield related to regular operation */
2036 ADC_STATE_CLR_SET(hadc->State,
2037 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
2038 HAL_ADC_STATE_REG_BUSY);
2039
2040 #if defined(ADC_MULTIMODE_SUPPORT)
2041 /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
2042 - if ADC instance is master or if multimode feature is not available
2043 - if multimode setting is disabled (ADC instance slave in independent mode) */
2044 if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
2045 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
2046 )
2047 {
2048 CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
2049 }
2050 #endif
2051
2052 /* Check if a conversion is on going on ADC group injected */
2053 if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) != 0UL)
2054 {
2055 /* Reset ADC error code fields related to regular conversions only */
2056 CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
2057 }
2058 else
2059 {
2060 /* Reset all ADC error code fields */
2061 ADC_CLEAR_ERRORCODE(hadc);
2062 }
2063
2064 /* Set the DMA transfer complete callback */
2065 hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
2066
2067 /* Set the DMA half transfer complete callback */
2068 hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
2069
2070 /* Set the DMA error callback */
2071 hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
2072
2073
2074 /* Manage ADC and DMA start: ADC overrun interruption, DMA start, */
2075 /* ADC start (in case of SW start): */
2076
2077 /* Clear regular group conversion flag and overrun flag */
2078 /* (To ensure of no unknown state from potential previous ADC */
2079 /* operations) */
2080 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
2081
2082 /* Process unlocked */
2083 /* Unlock before starting ADC conversions: in case of potential */
2084 /* interruption, to let the process to ADC IRQ Handler. */
2085 __HAL_UNLOCK(hadc);
2086
2087 /* With DMA, overrun event is always considered as an error even if
2088 hadc->Init.Overrun is set to ADC_OVR_DATA_OVERWRITTEN. Therefore,
2089 ADC_IT_OVR is enabled. */
2090 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
2091
2092 /* Enable ADC DMA mode */
2093 SET_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN);
2094
2095 /* Start the DMA channel */
2096 tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
2097
2098 /* Enable conversion of regular group. */
2099 /* If software start has been selected, conversion starts immediately. */
2100 /* If external trigger has been selected, conversion will start at next */
2101 /* trigger event. */
2102 /* Start ADC group regular conversion */
2103 LL_ADC_REG_StartConversion(hadc->Instance);
2104 }
2105 else
2106 {
2107 /* Process unlocked */
2108 __HAL_UNLOCK(hadc);
2109 }
2110
2111 }
2112 #if defined(ADC_MULTIMODE_SUPPORT)
2113 else
2114 {
2115 tmp_hal_status = HAL_ERROR;
2116 /* Process unlocked */
2117 __HAL_UNLOCK(hadc);
2118 }
2119 #endif
2120 }
2121 else
2122 {
2123 tmp_hal_status = HAL_BUSY;
2124 }
2125
2126 /* Return function status */
2127 return tmp_hal_status;
2128 }
2129
2130 /**
2131 * @brief Stop ADC conversion of regular group (and injected group in
2132 * case of auto_injection mode), disable ADC DMA transfer, disable
2133 * ADC peripheral.
2134 * @note: ADC peripheral disable is forcing stop of potential
2135 * conversion on ADC group injected. If ADC group injected is under use, it
2136 * should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
2137 * @note Case of multimode enabled (when multimode feature is available):
2138 * HAL_ADC_Stop_DMA() function is dedicated to single-ADC mode only.
2139 * For multimode, the dedicated HAL_ADCEx_MultiModeStop_DMA() API must be used.
2140 * @param hadc ADC handle
2141 * @retval HAL status.
2142 */
HAL_ADC_Stop_DMA(ADC_HandleTypeDef * hadc)2143 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc)
2144 {
2145 HAL_StatusTypeDef tmp_hal_status;
2146
2147 /* Check the parameters */
2148 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
2149
2150 /* Process locked */
2151 __HAL_LOCK(hadc);
2152
2153 /* 1. Stop potential ADC group regular conversion on going */
2154 tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
2155
2156 /* Disable ADC peripheral if conversions are effectively stopped */
2157 if (tmp_hal_status == HAL_OK)
2158 {
2159 /* Disable ADC DMA (ADC DMA configuration of continuous requests is kept) */
2160 CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN);
2161
2162 /* Disable the DMA channel (in case of DMA in circular mode or stop */
2163 /* while DMA transfer is on going) */
2164 if (hadc->DMA_Handle->State == HAL_DMA_STATE_BUSY)
2165 {
2166 tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
2167
2168 /* Check if DMA channel effectively disabled */
2169 if (tmp_hal_status != HAL_OK)
2170 {
2171 /* Update ADC state machine to error */
2172 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
2173 }
2174 }
2175
2176 /* Disable ADC overrun interrupt */
2177 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
2178
2179 /* 2. Disable the ADC peripheral */
2180 /* Update "tmp_hal_status" only if DMA channel disabling passed, */
2181 /* to keep in memory a potential failing status. */
2182 if (tmp_hal_status == HAL_OK)
2183 {
2184 tmp_hal_status = ADC_Disable(hadc);
2185 }
2186 else
2187 {
2188 (void)ADC_Disable(hadc);
2189 }
2190
2191 /* Check if ADC is effectively disabled */
2192 if (tmp_hal_status == HAL_OK)
2193 {
2194 /* Set ADC state */
2195 ADC_STATE_CLR_SET(hadc->State,
2196 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
2197 HAL_ADC_STATE_READY);
2198 }
2199
2200 }
2201
2202 /* Process unlocked */
2203 __HAL_UNLOCK(hadc);
2204
2205 /* Return function status */
2206 return tmp_hal_status;
2207 }
2208
2209 /**
2210 * @brief Get ADC regular group conversion result.
2211 * @note Reading register DR automatically clears ADC flag EOC
2212 * (ADC group regular end of unitary conversion).
2213 * @note This function does not clear ADC flag EOS
2214 * (ADC group regular end of sequence conversion).
2215 * Occurrence of flag EOS rising:
2216 * - If sequencer is composed of 1 rank, flag EOS is equivalent
2217 * to flag EOC.
2218 * - If sequencer is composed of several ranks, during the scan
2219 * sequence flag EOC only is raised, at the end of the scan sequence
2220 * both flags EOC and EOS are raised.
2221 * To clear this flag, either use function:
2222 * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
2223 * model polling: @ref HAL_ADC_PollForConversion()
2224 * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS).
2225 * @param hadc ADC handle
2226 * @retval ADC group regular conversion data
2227 */
HAL_ADC_GetValue(ADC_HandleTypeDef * hadc)2228 uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc)
2229 {
2230 /* Check the parameters */
2231 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
2232
2233 /* Note: EOC flag is not cleared here by software because automatically */
2234 /* cleared by hardware when reading register DR. */
2235
2236 /* Return ADC converted value */
2237 return hadc->Instance->DR;
2238 }
2239
2240 /**
2241 * @brief Start ADC conversion sampling phase of regular group
2242 * @note: This function should only be called to start sampling when
2243 * - @ref ADC_SAMPLING_MODE_TRIGGER_CONTROLED sampling
2244 * mode has been selected
2245 * - @ref ADC_SOFTWARE_START has been selected as trigger source
2246 * @param hadc ADC handle
2247 * @retval HAL status.
2248 */
HAL_ADC_StartSampling(ADC_HandleTypeDef * hadc)2249 HAL_StatusTypeDef HAL_ADC_StartSampling(ADC_HandleTypeDef *hadc)
2250 {
2251 /* Check the parameters */
2252 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
2253
2254 /* Start sampling */
2255 SET_BIT(hadc->Instance->CFGR2, ADC_CFGR2_SWTRIG);
2256
2257 /* Return function status */
2258 return HAL_OK;
2259 }
2260
2261 /**
2262 * @brief Stop ADC conversion sampling phase of regular group and start conversion
2263 * @note: This function should only be called to stop sampling when
2264 * - @ref ADC_SAMPLING_MODE_TRIGGER_CONTROLED sampling
2265 * mode has been selected
2266 * - @ref ADC_SOFTWARE_START has been selected as trigger source
2267 * - after sampling has been started using @ref HAL_ADC_StartSampling.
2268 * @param hadc ADC handle
2269 * @retval HAL status.
2270 */
HAL_ADC_StopSampling(ADC_HandleTypeDef * hadc)2271 HAL_StatusTypeDef HAL_ADC_StopSampling(ADC_HandleTypeDef *hadc)
2272 {
2273 /* Check the parameters */
2274 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
2275
2276 /* Start sampling */
2277 CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_SWTRIG);
2278
2279 /* Return function status */
2280 return HAL_OK;
2281 }
2282
2283 /**
2284 * @brief Handle ADC interrupt request.
2285 * @param hadc ADC handle
2286 * @retval None
2287 */
HAL_ADC_IRQHandler(ADC_HandleTypeDef * hadc)2288 void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc)
2289 {
2290 uint32_t overrun_error = 0UL; /* flag set if overrun occurrence has to be considered as an error */
2291 uint32_t tmp_isr = hadc->Instance->ISR;
2292 uint32_t tmp_ier = hadc->Instance->IER;
2293 uint32_t tmp_adc_inj_is_trigger_source_sw_start;
2294 uint32_t tmp_adc_reg_is_trigger_source_sw_start;
2295 uint32_t tmp_cfgr;
2296 #if defined(ADC_MULTIMODE_SUPPORT)
2297 const ADC_TypeDef *tmpADC_Master;
2298 uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
2299 #endif
2300
2301 /* Check the parameters */
2302 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
2303 assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
2304
2305 /* ========== Check End of Sampling flag for ADC group regular ========== */
2306 if (((tmp_isr & ADC_FLAG_EOSMP) == ADC_FLAG_EOSMP) && ((tmp_ier & ADC_IT_EOSMP) == ADC_IT_EOSMP))
2307 {
2308 /* Update state machine on end of sampling status if not in error state */
2309 if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
2310 {
2311 /* Set ADC state */
2312 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP);
2313 }
2314
2315 /* End Of Sampling callback */
2316 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
2317 hadc->EndOfSamplingCallback(hadc);
2318 #else
2319 HAL_ADCEx_EndOfSamplingCallback(hadc);
2320 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
2321
2322 /* Clear regular group conversion flag */
2323 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP);
2324 }
2325
2326 /* ====== Check ADC group regular end of unitary conversion sequence conversions ===== */
2327 if ((((tmp_isr & ADC_FLAG_EOC) == ADC_FLAG_EOC) && ((tmp_ier & ADC_IT_EOC) == ADC_IT_EOC)) ||
2328 (((tmp_isr & ADC_FLAG_EOS) == ADC_FLAG_EOS) && ((tmp_ier & ADC_IT_EOS) == ADC_IT_EOS)))
2329 {
2330 /* Update state machine on conversion status if not in error state */
2331 if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
2332 {
2333 /* Set ADC state */
2334 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
2335 }
2336
2337 /* Determine whether any further conversion upcoming on group regular */
2338 /* by external trigger, continuous mode or scan sequence on going */
2339 /* to disable interruption. */
2340 if (LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL)
2341 {
2342 /* Get relevant register CFGR in ADC instance of ADC master or slave */
2343 /* in function of multimode state (for devices with multimode */
2344 /* available). */
2345 #if defined(ADC_MULTIMODE_SUPPORT)
2346 if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
2347 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
2348 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
2349 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
2350 )
2351 {
2352 /* check CONT bit directly in handle ADC CFGR register */
2353 tmp_cfgr = READ_REG(hadc->Instance->CFGR);
2354 }
2355 else
2356 {
2357 /* else need to check Master ADC CONT bit */
2358 tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
2359 tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
2360 }
2361 #else
2362 tmp_cfgr = READ_REG(hadc->Instance->CFGR);
2363 #endif
2364
2365 /* Carry on if continuous mode is disabled */
2366 if (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) != ADC_CFGR_CONT)
2367 {
2368 /* If End of Sequence is reached, disable interrupts */
2369 if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS))
2370 {
2371 /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */
2372 /* ADSTART==0 (no conversion on going) */
2373 if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
2374 {
2375 /* Disable ADC end of sequence conversion interrupt */
2376 /* Note: Overrun interrupt was enabled with EOC interrupt in */
2377 /* HAL_Start_IT(), but is not disabled here because can be used */
2378 /* by overrun IRQ process below. */
2379 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS);
2380
2381 /* Set ADC state */
2382 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
2383
2384 if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL)
2385 {
2386 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
2387 }
2388 }
2389 else
2390 {
2391 /* Change ADC state to error state */
2392 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
2393
2394 /* Set ADC error code to ADC peripheral internal error */
2395 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
2396 }
2397 }
2398 }
2399 }
2400
2401 /* Conversion complete callback */
2402 /* Note: Into callback function "HAL_ADC_ConvCpltCallback()", */
2403 /* to determine if conversion has been triggered from EOC or EOS, */
2404 /* possibility to use: */
2405 /* " if ( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) " */
2406 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
2407 hadc->ConvCpltCallback(hadc);
2408 #else
2409 HAL_ADC_ConvCpltCallback(hadc);
2410 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
2411
2412 /* Clear regular group conversion flag */
2413 /* Note: in case of overrun set to ADC_OVR_DATA_PRESERVED, end of */
2414 /* conversion flags clear induces the release of the preserved data.*/
2415 /* Therefore, if the preserved data value is needed, it must be */
2416 /* read preliminarily into HAL_ADC_ConvCpltCallback(). */
2417 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS));
2418 }
2419
2420 /* ====== Check ADC group injected end of unitary conversion sequence conversions ===== */
2421 if ((((tmp_isr & ADC_FLAG_JEOC) == ADC_FLAG_JEOC) && ((tmp_ier & ADC_IT_JEOC) == ADC_IT_JEOC)) ||
2422 (((tmp_isr & ADC_FLAG_JEOS) == ADC_FLAG_JEOS) && ((tmp_ier & ADC_IT_JEOS) == ADC_IT_JEOS)))
2423 {
2424 /* Update state machine on conversion status if not in error state */
2425 if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
2426 {
2427 /* Set ADC state */
2428 SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
2429 }
2430
2431 /* Retrieve ADC configuration */
2432 tmp_adc_inj_is_trigger_source_sw_start = LL_ADC_INJ_IsTriggerSourceSWStart(hadc->Instance);
2433 tmp_adc_reg_is_trigger_source_sw_start = LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance);
2434 /* Get relevant register CFGR in ADC instance of ADC master or slave */
2435 /* in function of multimode state (for devices with multimode */
2436 /* available). */
2437 #if defined(ADC_MULTIMODE_SUPPORT)
2438 if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
2439 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
2440 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT)
2441 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL)
2442 )
2443 {
2444 tmp_cfgr = READ_REG(hadc->Instance->CFGR);
2445 }
2446 else
2447 {
2448 tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
2449 tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
2450 }
2451 #else
2452 tmp_cfgr = READ_REG(hadc->Instance->CFGR);
2453 #endif
2454
2455 /* Disable interruption if no further conversion upcoming by injected */
2456 /* external trigger or by automatic injected conversion with regular */
2457 /* group having no further conversion upcoming (same conditions as */
2458 /* regular group interruption disabling above), */
2459 /* and if injected scan sequence is completed. */
2460 if (tmp_adc_inj_is_trigger_source_sw_start != 0UL)
2461 {
2462 if ((READ_BIT(tmp_cfgr, ADC_CFGR_JAUTO) == 0UL) ||
2463 ((tmp_adc_reg_is_trigger_source_sw_start != 0UL) &&
2464 (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) == 0UL)))
2465 {
2466 /* If End of Sequence is reached, disable interrupts */
2467 if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS))
2468 {
2469 /* Particular case if injected contexts queue is enabled: */
2470 /* when the last context has been fully processed, JSQR is reset */
2471 /* by the hardware. Even if no injected conversion is planned to come */
2472 /* (queue empty, triggers are ignored), it can start again */
2473 /* immediately after setting a new context (JADSTART is still set). */
2474 /* Therefore, state of HAL ADC injected group is kept to busy. */
2475 if (READ_BIT(tmp_cfgr, ADC_CFGR_JQM) == 0UL)
2476 {
2477 /* Allowed to modify bits ADC_IT_JEOC/ADC_IT_JEOS only if bit */
2478 /* JADSTART==0 (no conversion on going) */
2479 if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
2480 {
2481 /* Disable ADC end of sequence conversion interrupt */
2482 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS);
2483
2484 /* Set ADC state */
2485 CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
2486
2487 if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL)
2488 {
2489 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
2490 }
2491 }
2492 else
2493 {
2494 /* Update ADC state machine to error */
2495 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
2496
2497 /* Set ADC error code to ADC peripheral internal error */
2498 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
2499 }
2500 }
2501 }
2502 }
2503 }
2504
2505 /* Injected Conversion complete callback */
2506 /* Note: HAL_ADCEx_InjectedConvCpltCallback can resort to
2507 if (__HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOS)) or
2508 if (__HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOC)) to determine whether
2509 interruption has been triggered by end of conversion or end of
2510 sequence. */
2511 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
2512 hadc->InjectedConvCpltCallback(hadc);
2513 #else
2514 HAL_ADCEx_InjectedConvCpltCallback(hadc);
2515 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
2516
2517 /* Clear injected group conversion flag */
2518 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC | ADC_FLAG_JEOS);
2519 }
2520
2521 /* ========== Check Analog watchdog 1 flag ========== */
2522 if (((tmp_isr & ADC_FLAG_AWD1) == ADC_FLAG_AWD1) && ((tmp_ier & ADC_IT_AWD1) == ADC_IT_AWD1))
2523 {
2524 /* Set ADC state */
2525 SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
2526
2527 /* Level out of window 1 callback */
2528 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
2529 hadc->LevelOutOfWindowCallback(hadc);
2530 #else
2531 HAL_ADC_LevelOutOfWindowCallback(hadc);
2532 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
2533
2534 /* Clear ADC analog watchdog flag */
2535 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
2536 }
2537
2538 /* ========== Check analog watchdog 2 flag ========== */
2539 if (((tmp_isr & ADC_FLAG_AWD2) == ADC_FLAG_AWD2) && ((tmp_ier & ADC_IT_AWD2) == ADC_IT_AWD2))
2540 {
2541 /* Set ADC state */
2542 SET_BIT(hadc->State, HAL_ADC_STATE_AWD2);
2543
2544 /* Level out of window 2 callback */
2545 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
2546 hadc->LevelOutOfWindow2Callback(hadc);
2547 #else
2548 HAL_ADCEx_LevelOutOfWindow2Callback(hadc);
2549 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
2550
2551 /* Clear ADC analog watchdog flag */
2552 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
2553 }
2554
2555 /* ========== Check analog watchdog 3 flag ========== */
2556 if (((tmp_isr & ADC_FLAG_AWD3) == ADC_FLAG_AWD3) && ((tmp_ier & ADC_IT_AWD3) == ADC_IT_AWD3))
2557 {
2558 /* Set ADC state */
2559 SET_BIT(hadc->State, HAL_ADC_STATE_AWD3);
2560
2561 /* Level out of window 3 callback */
2562 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
2563 hadc->LevelOutOfWindow3Callback(hadc);
2564 #else
2565 HAL_ADCEx_LevelOutOfWindow3Callback(hadc);
2566 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
2567
2568 /* Clear ADC analog watchdog flag */
2569 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
2570 }
2571
2572 /* ========== Check Overrun flag ========== */
2573 if (((tmp_isr & ADC_FLAG_OVR) == ADC_FLAG_OVR) && ((tmp_ier & ADC_IT_OVR) == ADC_IT_OVR))
2574 {
2575 /* If overrun is set to overwrite previous data (default setting), */
2576 /* overrun event is not considered as an error. */
2577 /* (cf ref manual "Managing conversions without using the DMA and without */
2578 /* overrun ") */
2579 /* Exception for usage with DMA overrun event always considered as an */
2580 /* error. */
2581 if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
2582 {
2583 overrun_error = 1UL;
2584 }
2585 else
2586 {
2587 /* Check DMA configuration */
2588 #if defined(ADC_MULTIMODE_SUPPORT)
2589 if (tmp_multimode_config != LL_ADC_MULTI_INDEPENDENT)
2590 {
2591 /* Multimode (when feature is available) is enabled,
2592 Common Control Register MDMA bits must be checked. */
2593 if (LL_ADC_GetMultiDMATransfer(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) != LL_ADC_MULTI_REG_DMA_EACH_ADC)
2594 {
2595 overrun_error = 1UL;
2596 }
2597 }
2598 else
2599 #endif
2600 {
2601 /* Multimode not set or feature not available or ADC independent */
2602 if ((hadc->Instance->CFGR & ADC_CFGR_DMAEN) != 0UL)
2603 {
2604 overrun_error = 1UL;
2605 }
2606 }
2607 }
2608
2609 if (overrun_error == 1UL)
2610 {
2611 /* Change ADC state to error state */
2612 SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
2613
2614 /* Set ADC error code to overrun */
2615 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
2616
2617 /* Error callback */
2618 /* Note: In case of overrun, ADC conversion data is preserved until */
2619 /* flag OVR is reset. */
2620 /* Therefore, old ADC conversion data can be retrieved in */
2621 /* function "HAL_ADC_ErrorCallback()". */
2622 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
2623 hadc->ErrorCallback(hadc);
2624 #else
2625 HAL_ADC_ErrorCallback(hadc);
2626 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
2627 }
2628
2629 /* Clear ADC overrun flag */
2630 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
2631 }
2632
2633 /* ========== Check Injected context queue overflow flag ========== */
2634 if (((tmp_isr & ADC_FLAG_JQOVF) == ADC_FLAG_JQOVF) && ((tmp_ier & ADC_IT_JQOVF) == ADC_IT_JQOVF))
2635 {
2636 /* Change ADC state to overrun state */
2637 SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
2638
2639 /* Set ADC error code to Injected context queue overflow */
2640 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
2641
2642 /* Clear the Injected context queue overflow flag */
2643 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF);
2644
2645 /* Injected context queue overflow callback */
2646 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
2647 hadc->InjectedQueueOverflowCallback(hadc);
2648 #else
2649 HAL_ADCEx_InjectedQueueOverflowCallback(hadc);
2650 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
2651 }
2652
2653 }
2654
2655 /**
2656 * @brief Conversion complete callback in non-blocking mode.
2657 * @param hadc ADC handle
2658 * @retval None
2659 */
HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef * hadc)2660 __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc)
2661 {
2662 /* Prevent unused argument(s) compilation warning */
2663 UNUSED(hadc);
2664
2665 /* NOTE : This function should not be modified. When the callback is needed,
2666 function HAL_ADC_ConvCpltCallback must be implemented in the user file.
2667 */
2668 }
2669
2670 /**
2671 * @brief Conversion DMA half-transfer callback in non-blocking mode.
2672 * @param hadc ADC handle
2673 * @retval None
2674 */
HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef * hadc)2675 __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc)
2676 {
2677 /* Prevent unused argument(s) compilation warning */
2678 UNUSED(hadc);
2679
2680 /* NOTE : This function should not be modified. When the callback is needed,
2681 function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file.
2682 */
2683 }
2684
2685 /**
2686 * @brief Analog watchdog 1 callback in non-blocking mode.
2687 * @param hadc ADC handle
2688 * @retval None
2689 */
HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef * hadc)2690 __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc)
2691 {
2692 /* Prevent unused argument(s) compilation warning */
2693 UNUSED(hadc);
2694
2695 /* NOTE : This function should not be modified. When the callback is needed,
2696 function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file.
2697 */
2698 }
2699
2700 /**
2701 * @brief ADC error callback in non-blocking mode
2702 * (ADC conversion with interruption or transfer by DMA).
2703 * @note In case of error due to overrun when using ADC with DMA transfer
2704 * (HAL ADC handle parameter "ErrorCode" to state "HAL_ADC_ERROR_OVR"):
2705 * - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()".
2706 * - If needed, restart a new ADC conversion using function
2707 * "HAL_ADC_Start_DMA()"
2708 * (this function is also clearing overrun flag)
2709 * @param hadc ADC handle
2710 * @retval None
2711 */
HAL_ADC_ErrorCallback(ADC_HandleTypeDef * hadc)2712 __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
2713 {
2714 /* Prevent unused argument(s) compilation warning */
2715 UNUSED(hadc);
2716
2717 /* NOTE : This function should not be modified. When the callback is needed,
2718 function HAL_ADC_ErrorCallback must be implemented in the user file.
2719 */
2720 }
2721
2722 /**
2723 * @}
2724 */
2725
2726 /** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
2727 * @brief Peripheral Control functions
2728 *
2729 @verbatim
2730 ===============================================================================
2731 ##### Peripheral Control functions #####
2732 ===============================================================================
2733 [..] This section provides functions allowing to:
2734 (+) Configure channels on regular group
2735 (+) Configure the analog watchdog
2736
2737 @endverbatim
2738 * @{
2739 */
2740
2741 /**
2742 * @brief Configure a channel to be assigned to ADC group regular.
2743 * @note In case of usage of internal measurement channels:
2744 * Vbat/VrefInt/TempSensor.
2745 * These internal paths can be disabled using function
2746 * HAL_ADC_DeInit().
2747 * @note Possibility to update parameters on the fly:
2748 * This function initializes channel into ADC group regular,
2749 * following calls to this function can be used to reconfigure
2750 * some parameters of structure "ADC_ChannelConfTypeDef" on the fly,
2751 * without resetting the ADC.
2752 * The setting of these parameters is conditioned to ADC state:
2753 * Refer to comments of structure "ADC_ChannelConfTypeDef".
2754 * @param hadc ADC handle
2755 * @param sConfig Structure of ADC channel assigned to ADC group regular.
2756 * @retval HAL status
2757 */
HAL_ADC_ConfigChannel(ADC_HandleTypeDef * hadc,ADC_ChannelConfTypeDef * sConfig)2758 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *sConfig)
2759 {
2760 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
2761 uint32_t tmpOffsetShifted;
2762 uint32_t tmp_config_internal_channel;
2763 __IO uint32_t wait_loop_index = 0UL;
2764 uint32_t tmp_adc_is_conversion_on_going_regular;
2765 uint32_t tmp_adc_is_conversion_on_going_injected;
2766
2767 /* Check the parameters */
2768 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
2769 assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
2770 assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
2771 assert_param(IS_ADC_SINGLE_DIFFERENTIAL(sConfig->SingleDiff));
2772 assert_param(IS_ADC_OFFSET_NUMBER(sConfig->OffsetNumber));
2773 assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfig->Offset));
2774
2775 /* if ROVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is
2776 ignored (considered as reset) */
2777 assert_param(!((sConfig->OffsetNumber != ADC_OFFSET_NONE) && (hadc->Init.OversamplingMode == ENABLE)));
2778
2779 /* Verification of channel number */
2780 if (sConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED)
2781 {
2782 assert_param(IS_ADC_CHANNEL(hadc, sConfig->Channel));
2783 }
2784 else
2785 {
2786 assert_param(IS_ADC_DIFF_CHANNEL(hadc, sConfig->Channel));
2787 }
2788
2789 /* Process locked */
2790 __HAL_LOCK(hadc);
2791
2792 /* Parameters update conditioned to ADC state: */
2793 /* Parameters that can be updated when ADC is disabled or enabled without */
2794 /* conversion on going on regular group: */
2795 /* - Channel number */
2796 /* - Channel rank */
2797 if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
2798 {
2799 /* Set ADC group regular sequence: channel on the selected scan sequence rank */
2800 LL_ADC_REG_SetSequencerRanks(hadc->Instance, sConfig->Rank, sConfig->Channel);
2801
2802 /* Parameters update conditioned to ADC state: */
2803 /* Parameters that can be updated when ADC is disabled or enabled without */
2804 /* conversion on going on regular group: */
2805 /* - Channel sampling time */
2806 /* - Channel offset */
2807 tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
2808 tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
2809 if ((tmp_adc_is_conversion_on_going_regular == 0UL)
2810 && (tmp_adc_is_conversion_on_going_injected == 0UL)
2811 )
2812 {
2813 /* Manage specific case of sampling time 3.5 cycles replacing 2.5 cyles */
2814 if (sConfig->SamplingTime == ADC_SAMPLETIME_3CYCLES_5)
2815 {
2816 /* Set sampling time of the selected ADC channel */
2817 LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfig->Channel, LL_ADC_SAMPLINGTIME_2CYCLES_5);
2818
2819 /* Set ADC sampling time common configuration */
2820 LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5);
2821 }
2822 else
2823 {
2824 /* Set sampling time of the selected ADC channel */
2825 LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfig->Channel, sConfig->SamplingTime);
2826
2827 /* Set ADC sampling time common configuration */
2828 LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_DEFAULT);
2829 }
2830
2831 /* Configure the offset: offset enable/disable, channel, offset value */
2832
2833 /* Shift the offset with respect to the selected ADC resolution. */
2834 /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */
2835 tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)sConfig->Offset);
2836
2837 if (sConfig->OffsetNumber != ADC_OFFSET_NONE)
2838 {
2839 /* Set ADC selected offset number */
2840 LL_ADC_SetOffset(hadc->Instance, sConfig->OffsetNumber, sConfig->Channel, tmpOffsetShifted);
2841
2842 assert_param(IS_ADC_OFFSET_SIGN(sConfig->OffsetSign));
2843 assert_param(IS_FUNCTIONAL_STATE(sConfig->OffsetSaturation));
2844 /* Set ADC selected offset sign & saturation */
2845 LL_ADC_SetOffsetSign(hadc->Instance, sConfig->OffsetNumber, sConfig->OffsetSign);
2846 LL_ADC_SetOffsetSaturation(hadc->Instance, sConfig->OffsetNumber, (sConfig->OffsetSaturation == ENABLE) ? LL_ADC_OFFSET_SATURATION_ENABLE : LL_ADC_OFFSET_SATURATION_DISABLE);
2847 }
2848 else
2849 {
2850 /* Scan each offset register to check if the selected channel is targeted. */
2851 /* If this is the case, the corresponding offset number is disabled. */
2852 if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1))
2853 == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel))
2854 {
2855 LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_1, LL_ADC_OFFSET_DISABLE);
2856 }
2857 if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2))
2858 == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel))
2859 {
2860 LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_2, LL_ADC_OFFSET_DISABLE);
2861 }
2862 if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3))
2863 == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel))
2864 {
2865 LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_3, LL_ADC_OFFSET_DISABLE);
2866 }
2867 if (__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4))
2868 == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel))
2869 {
2870 LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_4, LL_ADC_OFFSET_DISABLE);
2871 }
2872 }
2873 }
2874
2875 /* Parameters update conditioned to ADC state: */
2876 /* Parameters that can be updated only when ADC is disabled: */
2877 /* - Single or differential mode */
2878 if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
2879 {
2880 /* Set mode single-ended or differential input of the selected ADC channel */
2881 LL_ADC_SetChannelSingleDiff(hadc->Instance, sConfig->Channel, sConfig->SingleDiff);
2882
2883 /* Configuration of differential mode */
2884 if (sConfig->SingleDiff == ADC_DIFFERENTIAL_ENDED)
2885 {
2886 /* Set sampling time of the selected ADC channel */
2887 /* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits range */
2888 LL_ADC_SetChannelSamplingTime(hadc->Instance,
2889 (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)sConfig->Channel) + 1UL) & 0x1FUL)),
2890 sConfig->SamplingTime);
2891 }
2892
2893 }
2894
2895 /* Management of internal measurement channels: Vbat/VrefInt/TempSensor. */
2896 /* If internal channel selected, enable dedicated internal buffers and */
2897 /* paths. */
2898 /* Note: these internal measurement paths can be disabled using */
2899 /* HAL_ADC_DeInit(). */
2900
2901 if (__LL_ADC_IS_CHANNEL_INTERNAL(sConfig->Channel))
2902 {
2903 tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
2904
2905 /* If the requested internal measurement path has already been enabled, */
2906 /* bypass the configuration processing. */
2907 if (((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR_ADC1) || (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR_ADC5))
2908 && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL))
2909 {
2910 if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc))
2911 {
2912 LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
2913 LL_ADC_PATH_INTERNAL_TEMPSENSOR | tmp_config_internal_channel);
2914
2915 /* Delay for temperature sensor stabilization time */
2916 /* Wait loop initialization and execution */
2917 /* Note: Variable divided by 2 to compensate partially */
2918 /* CPU processing cycles, scaling in us split to not */
2919 /* exceed 32 bits register capacity and handle low frequency. */
2920 wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
2921 while (wait_loop_index != 0UL)
2922 {
2923 wait_loop_index--;
2924 }
2925 }
2926 }
2927 else if ((sConfig->Channel == ADC_CHANNEL_VBAT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL))
2928 {
2929 if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc))
2930 {
2931 LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
2932 LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel);
2933 }
2934 }
2935 else if ((sConfig->Channel == ADC_CHANNEL_VREFINT)
2936 && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL))
2937 {
2938 if (ADC_VREFINT_INSTANCE(hadc))
2939 {
2940 LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance),
2941 LL_ADC_PATH_INTERNAL_VREFINT | tmp_config_internal_channel);
2942 }
2943 }
2944 else
2945 {
2946 /* nothing to do */
2947 }
2948 }
2949 }
2950
2951 /* If a conversion is on going on regular group, no update on regular */
2952 /* channel could be done on neither of the channel configuration structure */
2953 /* parameters. */
2954 else
2955 {
2956 /* Update ADC state machine to error */
2957 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
2958
2959 tmp_hal_status = HAL_ERROR;
2960 }
2961
2962 /* Process unlocked */
2963 __HAL_UNLOCK(hadc);
2964
2965 /* Return function status */
2966 return tmp_hal_status;
2967 }
2968
2969 /**
2970 * @brief Configure the analog watchdog.
2971 * @note Possibility to update parameters on the fly:
2972 * This function initializes the selected analog watchdog, successive
2973 * calls to this function can be used to reconfigure some parameters
2974 * of structure "ADC_AnalogWDGConfTypeDef" on the fly, without resetting
2975 * the ADC.
2976 * The setting of these parameters is conditioned to ADC state.
2977 * For parameters constraints, see comments of structure
2978 * "ADC_AnalogWDGConfTypeDef".
2979 * @note On this STM32 series, analog watchdog thresholds can be modified
2980 * while ADC conversion is on going.
2981 * In this case, some constraints must be taken into account:
2982 * the programmed threshold values are effective from the next
2983 * ADC EOC (end of unitary conversion).
2984 * Considering that registers write delay may happen due to
2985 * bus activity, this might cause an uncertainty on the
2986 * effective timing of the new programmed threshold values.
2987 * @param hadc ADC handle
2988 * @param AnalogWDGConfig Structure of ADC analog watchdog configuration
2989 * @retval HAL status
2990 */
HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef * hadc,ADC_AnalogWDGConfTypeDef * AnalogWDGConfig)2991 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *AnalogWDGConfig)
2992 {
2993 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
2994 uint32_t tmpAWDHighThresholdShifted;
2995 uint32_t tmpAWDLowThresholdShifted;
2996 uint32_t tmp_adc_is_conversion_on_going_regular;
2997 uint32_t tmp_adc_is_conversion_on_going_injected;
2998
2999 /* Check the parameters */
3000 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
3001 assert_param(IS_ADC_ANALOG_WATCHDOG_NUMBER(AnalogWDGConfig->WatchdogNumber));
3002 assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode));
3003 assert_param(IS_ADC_ANALOG_WATCHDOG_FILTERING_MODE(AnalogWDGConfig->FilteringConfig));
3004 assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
3005
3006 if ((AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) ||
3007 (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC) ||
3008 (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC))
3009 {
3010 assert_param(IS_ADC_CHANNEL(hadc, AnalogWDGConfig->Channel));
3011 }
3012
3013 /* Verify thresholds range */
3014 if (hadc->Init.OversamplingMode == ENABLE)
3015 {
3016 /* Case of oversampling enabled: depending on ratio and shift configuration,
3017 analog watchdog thresholds can be higher than ADC resolution.
3018 Verify if thresholds are within maximum thresholds range. */
3019 assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, AnalogWDGConfig->HighThreshold));
3020 assert_param(IS_ADC_RANGE(ADC_RESOLUTION_12B, AnalogWDGConfig->LowThreshold));
3021 }
3022 else
3023 {
3024 /* Verify if thresholds are within the selected ADC resolution */
3025 assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold));
3026 assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold));
3027 }
3028
3029 /* Process locked */
3030 __HAL_LOCK(hadc);
3031
3032 /* Parameters update conditioned to ADC state: */
3033 /* Parameters that can be updated when ADC is disabled or enabled without */
3034 /* conversion on going on ADC groups regular and injected: */
3035 /* - Analog watchdog channels */
3036 tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
3037 tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
3038 if ((tmp_adc_is_conversion_on_going_regular == 0UL)
3039 && (tmp_adc_is_conversion_on_going_injected == 0UL)
3040 )
3041 {
3042 /* Analog watchdog configuration */
3043 if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1)
3044 {
3045 /* Configuration of analog watchdog: */
3046 /* - Set the analog watchdog enable mode: one or overall group of */
3047 /* channels, on groups regular and-or injected. */
3048 switch (AnalogWDGConfig->WatchdogMode)
3049 {
3050 case ADC_ANALOGWATCHDOG_SINGLE_REG:
3051 LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel,
3052 LL_ADC_GROUP_REGULAR));
3053 break;
3054
3055 case ADC_ANALOGWATCHDOG_SINGLE_INJEC:
3056 LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel,
3057 LL_ADC_GROUP_INJECTED));
3058 break;
3059
3060 case ADC_ANALOGWATCHDOG_SINGLE_REGINJEC:
3061 LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel,
3062 LL_ADC_GROUP_REGULAR_INJECTED));
3063 break;
3064
3065 case ADC_ANALOGWATCHDOG_ALL_REG:
3066 LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_REG);
3067 break;
3068
3069 case ADC_ANALOGWATCHDOG_ALL_INJEC:
3070 LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_INJ);
3071 break;
3072
3073 case ADC_ANALOGWATCHDOG_ALL_REGINJEC:
3074 LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_REG_INJ);
3075 break;
3076
3077 default: /* ADC_ANALOGWATCHDOG_NONE */
3078 LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_DISABLE);
3079 break;
3080 }
3081
3082 /* Set the filtering configuration */
3083 MODIFY_REG(hadc->Instance->TR1,
3084 ADC_TR1_AWDFILT,
3085 AnalogWDGConfig->FilteringConfig);
3086
3087 /* Update state, clear previous result related to AWD1 */
3088 CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD1);
3089
3090 /* Clear flag ADC analog watchdog */
3091 /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */
3092 /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */
3093 /* (in case left enabled by previous ADC operations). */
3094 LL_ADC_ClearFlag_AWD1(hadc->Instance);
3095
3096 /* Configure ADC analog watchdog interrupt */
3097 if (AnalogWDGConfig->ITMode == ENABLE)
3098 {
3099 LL_ADC_EnableIT_AWD1(hadc->Instance);
3100 }
3101 else
3102 {
3103 LL_ADC_DisableIT_AWD1(hadc->Instance);
3104 }
3105 }
3106 /* Case of ADC_ANALOGWATCHDOG_2 or ADC_ANALOGWATCHDOG_3 */
3107 else
3108 {
3109 switch (AnalogWDGConfig->WatchdogMode)
3110 {
3111 case ADC_ANALOGWATCHDOG_SINGLE_REG:
3112 case ADC_ANALOGWATCHDOG_SINGLE_INJEC:
3113 case ADC_ANALOGWATCHDOG_SINGLE_REGINJEC:
3114 /* Update AWD by bitfield to keep the possibility to monitor */
3115 /* several channels by successive calls of this function. */
3116 if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
3117 {
3118 SET_BIT(hadc->Instance->AWD2CR, (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDGConfig->Channel) & 0x1FUL)));
3119 }
3120 else
3121 {
3122 SET_BIT(hadc->Instance->AWD3CR, (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDGConfig->Channel) & 0x1FUL)));
3123 }
3124 break;
3125
3126 case ADC_ANALOGWATCHDOG_ALL_REG:
3127 case ADC_ANALOGWATCHDOG_ALL_INJEC:
3128 case ADC_ANALOGWATCHDOG_ALL_REGINJEC:
3129 LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, AnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_ALL_CHANNELS_REG_INJ);
3130 break;
3131
3132 default: /* ADC_ANALOGWATCHDOG_NONE */
3133 LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, AnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_DISABLE);
3134 break;
3135 }
3136
3137 if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
3138 {
3139 /* Update state, clear previous result related to AWD2 */
3140 CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD2);
3141
3142 /* Clear flag ADC analog watchdog */
3143 /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */
3144 /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */
3145 /* (in case left enabled by previous ADC operations). */
3146 LL_ADC_ClearFlag_AWD2(hadc->Instance);
3147
3148 /* Configure ADC analog watchdog interrupt */
3149 if (AnalogWDGConfig->ITMode == ENABLE)
3150 {
3151 LL_ADC_EnableIT_AWD2(hadc->Instance);
3152 }
3153 else
3154 {
3155 LL_ADC_DisableIT_AWD2(hadc->Instance);
3156 }
3157 }
3158 /* (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_3) */
3159 else
3160 {
3161 /* Update state, clear previous result related to AWD3 */
3162 CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD3);
3163
3164 /* Clear flag ADC analog watchdog */
3165 /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */
3166 /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */
3167 /* (in case left enabled by previous ADC operations). */
3168 LL_ADC_ClearFlag_AWD3(hadc->Instance);
3169
3170 /* Configure ADC analog watchdog interrupt */
3171 if (AnalogWDGConfig->ITMode == ENABLE)
3172 {
3173 LL_ADC_EnableIT_AWD3(hadc->Instance);
3174 }
3175 else
3176 {
3177 LL_ADC_DisableIT_AWD3(hadc->Instance);
3178 }
3179 }
3180 }
3181
3182 }
3183
3184 /* Analog watchdog thresholds configuration */
3185 if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1)
3186 {
3187 /* Shift the offset with respect to the selected ADC resolution: */
3188 /* Thresholds have to be left-aligned on bit 11, the LSB (right bits) */
3189 /* are set to 0. */
3190 tmpAWDHighThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold);
3191 tmpAWDLowThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold);
3192 }
3193 /* Case of ADC_ANALOGWATCHDOG_2 and ADC_ANALOGWATCHDOG_3 */
3194 else
3195 {
3196 /* Shift the offset with respect to the selected ADC resolution: */
3197 /* Thresholds have to be left-aligned on bit 7, the LSB (right bits) */
3198 /* are set to 0. */
3199 tmpAWDHighThresholdShifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold);
3200 tmpAWDLowThresholdShifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold);
3201 }
3202
3203 /* Set ADC analog watchdog thresholds value of both thresholds high and low */
3204 LL_ADC_ConfigAnalogWDThresholds(hadc->Instance, AnalogWDGConfig->WatchdogNumber, tmpAWDHighThresholdShifted,
3205 tmpAWDLowThresholdShifted);
3206
3207 /* Process unlocked */
3208 __HAL_UNLOCK(hadc);
3209
3210 /* Return function status */
3211 return tmp_hal_status;
3212 }
3213
3214
3215 /**
3216 * @}
3217 */
3218
3219 /** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions
3220 * @brief ADC Peripheral State functions
3221 *
3222 @verbatim
3223 ===============================================================================
3224 ##### Peripheral state and errors functions #####
3225 ===============================================================================
3226 [..]
3227 This subsection provides functions to get in run-time the status of the
3228 peripheral.
3229 (+) Check the ADC state
3230 (+) Check the ADC error code
3231
3232 @endverbatim
3233 * @{
3234 */
3235
3236 /**
3237 * @brief Return the ADC handle state.
3238 * @note ADC state machine is managed by bitfields, ADC status must be
3239 * compared with states bits.
3240 * For example:
3241 * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) "
3242 * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) "
3243 * @param hadc ADC handle
3244 * @retval ADC handle state (bitfield on 32 bits)
3245 */
HAL_ADC_GetState(ADC_HandleTypeDef * hadc)3246 uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc)
3247 {
3248 /* Check the parameters */
3249 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
3250
3251 /* Return ADC handle state */
3252 return hadc->State;
3253 }
3254
3255 /**
3256 * @brief Return the ADC error code.
3257 * @param hadc ADC handle
3258 * @retval ADC error code (bitfield on 32 bits)
3259 */
HAL_ADC_GetError(ADC_HandleTypeDef * hadc)3260 uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
3261 {
3262 /* Check the parameters */
3263 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
3264
3265 return hadc->ErrorCode;
3266 }
3267
3268 /**
3269 * @}
3270 */
3271
3272 /**
3273 * @}
3274 */
3275
3276 /** @defgroup ADC_Private_Functions ADC Private Functions
3277 * @{
3278 */
3279
3280 /**
3281 * @brief Stop ADC conversion.
3282 * @param hadc ADC handle
3283 * @param ConversionGroup ADC group regular and/or injected.
3284 * This parameter can be one of the following values:
3285 * @arg @ref ADC_REGULAR_GROUP ADC regular conversion type.
3286 * @arg @ref ADC_INJECTED_GROUP ADC injected conversion type.
3287 * @arg @ref ADC_REGULAR_INJECTED_GROUP ADC regular and injected conversion type.
3288 * @retval HAL status.
3289 */
ADC_ConversionStop(ADC_HandleTypeDef * hadc,uint32_t ConversionGroup)3290 HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t ConversionGroup)
3291 {
3292 uint32_t tickstart;
3293 uint32_t Conversion_Timeout_CPU_cycles = 0UL;
3294 uint32_t conversion_group_reassigned = ConversionGroup;
3295 uint32_t tmp_ADC_CR_ADSTART_JADSTART;
3296 uint32_t tmp_adc_is_conversion_on_going_regular;
3297 uint32_t tmp_adc_is_conversion_on_going_injected;
3298
3299 /* Check the parameters */
3300 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
3301 assert_param(IS_ADC_CONVERSION_GROUP(ConversionGroup));
3302
3303 /* Verification if ADC is not already stopped (on regular and injected */
3304 /* groups) to bypass this function if not needed. */
3305 tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
3306 tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
3307 if ((tmp_adc_is_conversion_on_going_regular != 0UL)
3308 || (tmp_adc_is_conversion_on_going_injected != 0UL)
3309 )
3310 {
3311 /* Particular case of continuous auto-injection mode combined with */
3312 /* auto-delay mode. */
3313 /* In auto-injection mode, regular group stop ADC_CR_ADSTP is used (not */
3314 /* injected group stop ADC_CR_JADSTP). */
3315 /* Procedure to be followed: Wait until JEOS=1, clear JEOS, set ADSTP=1 */
3316 /* (see reference manual). */
3317 if (((hadc->Instance->CFGR & ADC_CFGR_JAUTO) != 0UL)
3318 && (hadc->Init.ContinuousConvMode == ENABLE)
3319 && (hadc->Init.LowPowerAutoWait == ENABLE)
3320 )
3321 {
3322 /* Use stop of regular group */
3323 conversion_group_reassigned = ADC_REGULAR_GROUP;
3324
3325 /* Wait until JEOS=1 (maximum Timeout: 4 injected conversions) */
3326 while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS) == 0UL)
3327 {
3328 if (Conversion_Timeout_CPU_cycles >= (ADC_CONVERSION_TIME_MAX_CPU_CYCLES * 4UL))
3329 {
3330 /* Update ADC state machine to error */
3331 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
3332
3333 /* Set ADC error code to ADC peripheral internal error */
3334 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
3335
3336 return HAL_ERROR;
3337 }
3338 Conversion_Timeout_CPU_cycles ++;
3339 }
3340
3341 /* Clear JEOS */
3342 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOS);
3343 }
3344
3345 /* Stop potential conversion on going on ADC group regular */
3346 if (conversion_group_reassigned != ADC_INJECTED_GROUP)
3347 {
3348 /* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 */
3349 if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL)
3350 {
3351 if (LL_ADC_IsDisableOngoing(hadc->Instance) == 0UL)
3352 {
3353 /* Stop ADC group regular conversion */
3354 LL_ADC_REG_StopConversion(hadc->Instance);
3355 }
3356 }
3357 }
3358
3359 /* Stop potential conversion on going on ADC group injected */
3360 if (conversion_group_reassigned != ADC_REGULAR_GROUP)
3361 {
3362 /* Software is allowed to set JADSTP only when JADSTART=1 and ADDIS=0 */
3363 if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) != 0UL)
3364 {
3365 if (LL_ADC_IsDisableOngoing(hadc->Instance) == 0UL)
3366 {
3367 /* Stop ADC group injected conversion */
3368 LL_ADC_INJ_StopConversion(hadc->Instance);
3369 }
3370 }
3371 }
3372
3373 /* Selection of start and stop bits with respect to the regular or injected group */
3374 switch (conversion_group_reassigned)
3375 {
3376 case ADC_REGULAR_INJECTED_GROUP:
3377 tmp_ADC_CR_ADSTART_JADSTART = (ADC_CR_ADSTART | ADC_CR_JADSTART);
3378 break;
3379 case ADC_INJECTED_GROUP:
3380 tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_JADSTART;
3381 break;
3382 /* Case ADC_REGULAR_GROUP only*/
3383 default:
3384 tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_ADSTART;
3385 break;
3386 }
3387
3388 /* Wait for conversion effectively stopped */
3389 tickstart = HAL_GetTick();
3390
3391 while ((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != 0UL)
3392 {
3393 if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
3394 {
3395 /* New check to avoid false timeout detection in case of preemption */
3396 if ((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != 0UL)
3397 {
3398 /* Update ADC state machine to error */
3399 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
3400
3401 /* Set ADC error code to ADC peripheral internal error */
3402 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
3403
3404 return HAL_ERROR;
3405 }
3406 }
3407 }
3408
3409 }
3410
3411 /* Return HAL status */
3412 return HAL_OK;
3413 }
3414
3415 /**
3416 * @brief Enable the selected ADC.
3417 * @note Prerequisite condition to use this function: ADC must be disabled
3418 * and voltage regulator must be enabled (done into HAL_ADC_Init()).
3419 * @param hadc ADC handle
3420 * @retval HAL status.
3421 */
ADC_Enable(ADC_HandleTypeDef * hadc)3422 HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc)
3423 {
3424 uint32_t tickstart;
3425
3426 /* ADC enable and wait for ADC ready (in case of ADC is disabled or */
3427 /* enabling phase not yet completed: flag ADC ready not yet set). */
3428 /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */
3429 /* causes: ADC clock not running, ...). */
3430 if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
3431 {
3432 /* Check if conditions to enable the ADC are fulfilled */
3433 if ((hadc->Instance->CR & (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART
3434 | ADC_CR_ADDIS | ADC_CR_ADEN)) != 0UL)
3435 {
3436 /* Update ADC state machine to error */
3437 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
3438
3439 /* Set ADC error code to ADC peripheral internal error */
3440 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
3441
3442 return HAL_ERROR;
3443 }
3444
3445 /* Enable the ADC peripheral */
3446 LL_ADC_Enable(hadc->Instance);
3447
3448 /* Wait for ADC effectively enabled */
3449 tickstart = HAL_GetTick();
3450
3451 while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL)
3452 {
3453 /* If ADEN bit is set less than 4 ADC clock cycles after the ADCAL bit
3454 has been cleared (after a calibration), ADEN bit is reset by the
3455 calibration logic.
3456 The workaround is to continue setting ADEN until ADRDY is becomes 1.
3457 Additionally, ADC_ENABLE_TIMEOUT is defined to encompass this
3458 4 ADC clock cycle duration */
3459 /* Note: Test of ADC enabled required due to hardware constraint to */
3460 /* not enable ADC if already enabled. */
3461 if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
3462 {
3463 LL_ADC_Enable(hadc->Instance);
3464 }
3465
3466 if ((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
3467 {
3468 /* New check to avoid false timeout detection in case of preemption */
3469 if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL)
3470 {
3471 /* Update ADC state machine to error */
3472 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
3473
3474 /* Set ADC error code to ADC peripheral internal error */
3475 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
3476
3477 return HAL_ERROR;
3478 }
3479 }
3480 }
3481 }
3482
3483 /* Return HAL status */
3484 return HAL_OK;
3485 }
3486
3487 /**
3488 * @brief Disable the selected ADC.
3489 * @note Prerequisite condition to use this function: ADC conversions must be
3490 * stopped.
3491 * @param hadc ADC handle
3492 * @retval HAL status.
3493 */
ADC_Disable(ADC_HandleTypeDef * hadc)3494 HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc)
3495 {
3496 uint32_t tickstart;
3497 const uint32_t tmp_adc_is_disable_on_going = LL_ADC_IsDisableOngoing(hadc->Instance);
3498
3499 /* Verification if ADC is not already disabled: */
3500 /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */
3501 /* disabled. */
3502 if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL)
3503 && (tmp_adc_is_disable_on_going == 0UL)
3504 )
3505 {
3506 /* Check if conditions to disable the ADC are fulfilled */
3507 if ((hadc->Instance->CR & (ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN)
3508 {
3509 /* Disable the ADC peripheral */
3510 LL_ADC_Disable(hadc->Instance);
3511 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOSMP | ADC_FLAG_RDY));
3512 }
3513 else
3514 {
3515 /* Update ADC state machine to error */
3516 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
3517
3518 /* Set ADC error code to ADC peripheral internal error */
3519 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
3520
3521 return HAL_ERROR;
3522 }
3523
3524 /* Wait for ADC effectively disabled */
3525 /* Get tick count */
3526 tickstart = HAL_GetTick();
3527
3528 while ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL)
3529 {
3530 if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
3531 {
3532 /* New check to avoid false timeout detection in case of preemption */
3533 if ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL)
3534 {
3535 /* Update ADC state machine to error */
3536 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
3537
3538 /* Set ADC error code to ADC peripheral internal error */
3539 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
3540
3541 return HAL_ERROR;
3542 }
3543 }
3544 }
3545 }
3546
3547 /* Return HAL status */
3548 return HAL_OK;
3549 }
3550
3551 /**
3552 * @brief DMA transfer complete callback.
3553 * @param hdma pointer to DMA handle.
3554 * @retval None
3555 */
ADC_DMAConvCplt(DMA_HandleTypeDef * hdma)3556 void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
3557 {
3558 /* Retrieve ADC handle corresponding to current DMA handle */
3559 ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3560
3561 /* Update state machine on conversion status if not in error state */
3562 if ((hadc->State & (HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) == 0UL)
3563 {
3564 /* Set ADC state */
3565 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
3566
3567 /* Determine whether any further conversion upcoming on group regular */
3568 /* by external trigger, continuous mode or scan sequence on going */
3569 /* to disable interruption. */
3570 /* Is it the end of the regular sequence ? */
3571 if ((hadc->Instance->ISR & ADC_FLAG_EOS) != 0UL)
3572 {
3573 /* Are conversions software-triggered ? */
3574 if (LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL)
3575 {
3576 /* Is CONT bit set ? */
3577 if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_CONT) == 0UL)
3578 {
3579 /* CONT bit is not set, no more conversions expected */
3580 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
3581 if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL)
3582 {
3583 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
3584 }
3585 }
3586 }
3587 }
3588 else
3589 {
3590 /* DMA End of Transfer interrupt was triggered but conversions sequence
3591 is not over. If DMACFG is set to 0, conversions are stopped. */
3592 if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMACFG) == 0UL)
3593 {
3594 /* DMACFG bit is not set, conversions are stopped. */
3595 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
3596 if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL)
3597 {
3598 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
3599 }
3600 }
3601 }
3602
3603 /* Conversion complete callback */
3604 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
3605 hadc->ConvCpltCallback(hadc);
3606 #else
3607 HAL_ADC_ConvCpltCallback(hadc);
3608 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
3609 }
3610 else /* DMA and-or internal error occurred */
3611 {
3612 if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) != 0UL)
3613 {
3614 /* Call HAL ADC Error Callback function */
3615 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
3616 hadc->ErrorCallback(hadc);
3617 #else
3618 HAL_ADC_ErrorCallback(hadc);
3619 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
3620 }
3621 else
3622 {
3623 /* Call ADC DMA error callback */
3624 hadc->DMA_Handle->XferErrorCallback(hdma);
3625 }
3626 }
3627 }
3628
3629 /**
3630 * @brief DMA half transfer complete callback.
3631 * @param hdma pointer to DMA handle.
3632 * @retval None
3633 */
ADC_DMAHalfConvCplt(DMA_HandleTypeDef * hdma)3634 void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
3635 {
3636 /* Retrieve ADC handle corresponding to current DMA handle */
3637 ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3638
3639 /* Half conversion callback */
3640 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
3641 hadc->ConvHalfCpltCallback(hadc);
3642 #else
3643 HAL_ADC_ConvHalfCpltCallback(hadc);
3644 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
3645 }
3646
3647 /**
3648 * @brief DMA error callback.
3649 * @param hdma pointer to DMA handle.
3650 * @retval None
3651 */
ADC_DMAError(DMA_HandleTypeDef * hdma)3652 void ADC_DMAError(DMA_HandleTypeDef *hdma)
3653 {
3654 /* Retrieve ADC handle corresponding to current DMA handle */
3655 ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3656
3657 /* Set ADC state */
3658 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
3659
3660 /* Set ADC error code to DMA error */
3661 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA);
3662
3663 /* Error callback */
3664 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
3665 hadc->ErrorCallback(hadc);
3666 #else
3667 HAL_ADC_ErrorCallback(hadc);
3668 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
3669 }
3670
3671 /**
3672 * @}
3673 */
3674
3675 #endif /* HAL_ADC_MODULE_ENABLED */
3676 /**
3677 * @}
3678 */
3679
3680 /**
3681 * @}
3682 */
3683
