1 /**
2 ******************************************************************************
3 * @file stm32mp1xx_hal_adc.c
4 * @author MCD Application Team
5 * @brief This file provides firmware functions to manage the following
6 * functionalities of the Analog to Digital Converter (ADC)
7 * peripheral:
8 * + Initialization and de-initialization functions
9 * + Peripheral Control functions
10 * + Peripheral State functions
11 * Other functions (extended functions) are available in file
12 * "stm32mp1xx_hal_adc_ex.c".
13 *
14 ******************************************************************************
15 * @attention
16 *
17 * Copyright (c) 2019 STMicroelectronics.
18 * All rights reserved.
19 *
20 * This software is licensed under terms that can be found in the LICENSE file
21 * in the root directory of this software component.
22 * If no LICENSE file comes with this software, it is provided AS-IS.
23 *
24 ******************************************************************************
25 @verbatim
26 ==============================================================================
27 ##### ADC peripheral features #####
28 ==============================================================================
29 [..]
30 (+) 16-bit, 14-bit, 12-bit, 10-bit or 8-bit configurable resolution.
31
32 (+) Interrupt generation at the end of regular conversion and in case of
33 analog watchdog or overrun events.
34
35 (+) Single and continuous conversion modes.
36
37 (+) Scan mode for conversion of several channels sequentially.
38
39 (+) Data alignment with in-built data coherency.
40
41 (+) Programmable sampling time (channel wise)
42
43 (+) External trigger (timer or EXTI) with configurable polarity
44
45 (+) DMA request generation for transfer of conversions data of regular group.
46
47 (+) Configurable delay between conversions in Dual interleaved mode.
48
49 (+) ADC channels selectable single/differential input.
50
51 (+) ADC offset shared on 4 offset instances.
52 (+) ADC calibration
53
54 (+) ADC conversion of regular group.
55
56 (+) ADC supply requirements: 1.62 V to 3.6 V.
57
58 (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to
59 Vdda or to an external voltage reference).
60
61
62 ##### How to use this driver #####
63 ==============================================================================
64 [..]
65
66 *** Configuration of top level parameters related to ADC ***
67 ============================================================
68 [..]
69
70 (#) Enable the ADC interface
71 (++) As prerequisite, ADC clock must be configured at RCC top level.
72
73 (++) Two clock settings are mandatory:
74 (+++) ADC clock (core clock, also possibly conversion clock).
75
76 (+++) ADC clock (conversions clock).
77 Two possible clock sources: synchronous clock derived from AHB clock
78 or asynchronous clock derived from system clock, the PLL4 or the PLL3.
79
80 (+++) Example:
81 Into HAL_ADC_MspInit() (recommended code location) or with
82 other device clock parameters configuration:
83 (+++) __HAL_RCC_ADC_CLK_ENABLE(); (mandatory)
84
85 RCC_ADCCLKSOURCE_PLL enable: (optional: if asynchronous clock selected)
86 (+++) RCC_PeriphClkInitTypeDef RCC_PeriphClkInit;
87 (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC;
88 (+++) PeriphClkInit.AdcClockSelection = RCC_ADCCLKSOURCE_PLL;
89 (+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit);
90
91 (++) ADC clock source and clock prescaler are configured at ADC level with
92 parameter "ClockPrescaler" using function HAL_ADC_Init().
93
94 (#) ADC pins configuration
95 (++) Enable the clock for the ADC GPIOs
96 using macro __HAL_RCC_GPIOx_CLK_ENABLE()
97 (++) Configure these ADC pins in analog mode
98 using function HAL_GPIO_Init()
99
100 (#) Optionally, in case of usage of ADC with interruptions:
101 (++) Configure the NVIC for ADC
102 using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
103 (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
104 into the function of corresponding ADC interruption vector
105 ADCx_IRQHandler().
106
107 (#) Optionally, in case of usage of DMA:
108 (++) Configure the DMA (DMA channel, mode normal or circular, ...)
109 using function HAL_DMA_Init().
110 (++) Configure the NVIC for DMA
111 using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
112 (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler()
113 into the function of corresponding DMA interruption vector
114 DMAx_Channelx_IRQHandler().
115
116 *** Configuration of ADC, group regular, channels parameters ***
117 ================================================================
118 [..]
119
120 (#) Configure the ADC parameters (resolution, data alignment, ...)
121 and regular group parameters (conversion trigger, sequencer, ...)
122 using function HAL_ADC_Init().
123
124 (#) Configure the channels for regular group parameters (channel number,
125 channel rank into sequencer, ..., into regular group)
126 using function HAL_ADC_ConfigChannel().
127
128 (#) Optionally, configure the analog watchdog parameters (channels
129 monitored, thresholds, ...)
130 using function HAL_ADC_AnalogWDGConfig().
131
132 *** Execution of ADC conversions ***
133 ====================================
134 [..]
135
136 (#) Optionally, perform an automatic ADC calibration to improve the
137 conversion accuracy
138 using function HAL_ADCEx_Calibration_Start().
139
140 (#) ADC driver can be used among three modes: polling, interruption,
141 transfer by DMA.
142
143 (++) ADC conversion by polling:
144 (+++) Activate the ADC peripheral and start conversions
145 using function HAL_ADC_Start()
146 (+++) Wait for ADC conversion completion
147 using function HAL_ADC_PollForConversion()
148 (+++) Retrieve conversion results
149 using function HAL_ADC_GetValue()
150 (+++) Stop conversion and disable the ADC peripheral
151 using function HAL_ADC_Stop()
152
153 (++) ADC conversion by interruption:
154 (+++) Activate the ADC peripheral and start conversions
155 using function HAL_ADC_Start_IT()
156 (+++) Wait for ADC conversion completion by call of function
157 HAL_ADC_ConvCpltCallback()
158 (this function must be implemented in user program)
159 (+++) Retrieve conversion results
160 using function HAL_ADC_GetValue()
161 (+++) Stop conversion and disable the ADC peripheral
162 using function HAL_ADC_Stop_IT()
163
164 (++) ADC conversion with transfer by DMA:
165 (+++) Activate the ADC peripheral and start conversions
166 using function HAL_ADC_Start_DMA()
167 (+++) Wait for ADC conversion completion by call of function
168 HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback()
169 (these functions must be implemented in user program)
170 (+++) Conversion results are automatically transferred by DMA into
171 destination variable address.
172 (+++) Stop conversion and disable the ADC peripheral
173 using function HAL_ADC_Stop_DMA()
174
175 [..]
176
177 (@) Callback functions must be implemented in user program:
178 (+@) HAL_ADC_ErrorCallback()
179 (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog)
180 (+@) HAL_ADC_ConvCpltCallback()
181 (+@) HAL_ADC_ConvHalfCpltCallback
182
183 *** Deinitialization of ADC ***
184 ============================================================
185 [..]
186
187 (#) Disable the ADC interface
188 (++) ADC clock can be hard reset and disabled at RCC top level.
189 (++) Hard reset of ADC peripherals
190 using macro __ADCx_FORCE_RESET(), __ADCx_RELEASE_RESET().
191 (++) ADC clock disable
192 using the equivalent macro/functions as configuration step.
193 (+++) Example:
194 Into HAL_ADC_MspDeInit() (recommended code location) or with
195 other device clock parameters configuration:
196 (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI14;
197 (+++) RCC_OscInitStructure.HSI14State = RCC_HSI14_OFF; (if not used for system clock)
198 (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure);
199
200 (#) ADC pins configuration
201 (++) Disable the clock for the ADC GPIOs
202 using macro __HAL_RCC_GPIOx_CLK_DISABLE()
203
204 (#) Optionally, in case of usage of ADC with interruptions:
205 (++) Disable the NVIC for ADC
206 using function HAL_NVIC_EnableIRQ(ADCx_IRQn)
207
208 (#) Optionally, in case of usage of DMA:
209 (++) Deinitialize the DMA
210 using function HAL_DMA_Init().
211 (++) Disable the NVIC for DMA
212 using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn)
213
214 [..]
215
216 *** Callback registration ***
217 =============================================
218 [..]
219
220 The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1,
221 allows the user to configure dynamically the driver callbacks.
222 Use Functions @ref HAL_ADC_RegisterCallback()
223 to register an interrupt callback.
224 [..]
225
226 Function @ref HAL_ADC_RegisterCallback() allows to register following callbacks:
227 (+) ConvCpltCallback : ADC conversion complete callback
228 (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback
229 (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback
230 (+) ErrorCallback : ADC error callback
231 (+) InjectedConvCpltCallback : ADC group injected conversion complete callback
232 (+) InjectedQueueOverflowCallback : ADC group injected context queue overflow callback
233 (+) LevelOutOfWindow2Callback : ADC analog watchdog 2 callback
234 (+) LevelOutOfWindow3Callback : ADC analog watchdog 3 callback
235 (+) EndOfSamplingCallback : ADC end of sampling callback
236 (+) MspInitCallback : ADC Msp Init callback
237 (+) MspDeInitCallback : ADC Msp DeInit callback
238 This function takes as parameters the HAL peripheral handle, the Callback ID
239 and a pointer to the user callback function.
240 [..]
241
242 Use function @ref HAL_ADC_UnRegisterCallback to reset a callback to the default
243 weak function.
244 [..]
245
246 @ref HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle,
247 and the Callback ID.
248 This function allows to reset following callbacks:
249 (+) ConvCpltCallback : ADC conversion complete callback
250 (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback
251 (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback
252 (+) ErrorCallback : ADC error callback
253 (+) InjectedConvCpltCallback : ADC group injected conversion complete callback
254 (+) InjectedQueueOverflowCallback : ADC group injected context queue overflow callback
255 (+) LevelOutOfWindow2Callback : ADC analog watchdog 2 callback
256 (+) LevelOutOfWindow3Callback : ADC analog watchdog 3 callback
257 (+) EndOfSamplingCallback : ADC end of sampling callback
258 (+) MspInitCallback : ADC Msp Init callback
259 (+) MspDeInitCallback : ADC Msp DeInit callback
260 [..]
261
262 By default, after the @ref HAL_ADC_Init() and when the state is @ref HAL_ADC_STATE_RESET
263 all callbacks are set to the corresponding weak functions:
264 examples @ref HAL_ADC_ConvCpltCallback(), @ref HAL_ADC_ErrorCallback().
265 Exception done for MspInit and MspDeInit functions that are
266 reset to the legacy weak functions in the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit() only when
267 these callbacks are null (not registered beforehand).
268 [..]
269
270 If MspInit or MspDeInit are not null, the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit()
271 keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state.
272 [..]
273
274 Callbacks can be registered/unregistered in @ref HAL_ADC_STATE_READY state only.
275 Exception done MspInit/MspDeInit functions that can be registered/unregistered
276 in @ref HAL_ADC_STATE_READY or @ref HAL_ADC_STATE_RESET state,
277 thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
278 [..]
279
280 Then, the user first registers the MspInit/MspDeInit user callbacks
281 using @ref HAL_ADC_RegisterCallback() before calling @ref HAL_ADC_DeInit()
282 or @ref HAL_ADC_Init() function.
283 [..]
284
285 When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or
286 not defined, the callback registration feature is not available and all callbacks
287 are set to the corresponding weak functions.
288
289 @endverbatim
290 ******************************************************************************
291 */
292
293 /* Includes ------------------------------------------------------------------*/
294 #include "stm32mp1xx_hal.h"
295
296 /** @addtogroup STM32MP1xx_HAL_Driver
297 * @{
298 */
299
300 /** @defgroup ADC ADC
301 * @brief ADC HAL module driver
302 * @{
303 */
304
305 #ifdef HAL_ADC_MODULE_ENABLED
306
307 /* Private typedef -----------------------------------------------------------*/
308 /* Private define ------------------------------------------------------------*/
309
310 /** @defgroup ADC_Private_Constants ADC Private Constants
311 * @{
312 */
313 #define ADC_CFGR_FIELDS_1 ((uint32_t)(ADC_CFGR_RES |\
314 ADC_CFGR_CONT | ADC_CFGR_OVRMOD |\
315 ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM |\
316 ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL)) /*!< ADC_CFGR fields of parameters that can be updated when no regular conversion is on-going */
317
318 #define ADC_CFGR2_FIELDS ((uint32_t)(ADC_CFGR2_ROVSE | ADC_CFGR2_OSR |\
319 ADC_CFGR2_OVSS | ADC_CFGR2_TROVS |\
320 ADC_CFGR2_ROVSM)) /*!< ADC_CFGR2 fields of parameters that can be updated when no conversion (neither regular nor injected) is on-going */
321
322 /* Timeout values for ADC operations (enable settling time, */
323 /* disable settling time, ...). */
324 /* Values defined to be higher than worst cases: low clock frequency, */
325 /* maximum prescalers. */
326 #define ADC_ENABLE_TIMEOUT (2UL) /*!< ADC enable time-out value */
327 #define ADC_DISABLE_TIMEOUT (2UL) /*!< ADC disable time-out value */
328
329 /* Timeout to wait for current conversion on going to be completed. */
330 /* Timeout fixed to worst case, for 1 channel. */
331 /* - maximum sampling time (830.5 adc_clk) */
332 /* - ADC resolution (Tsar 16 bits= 16.5 adc_clk) */
333 /* - ADC clock with prescaler 256 */
334 /* 823 * 256 = 210688 clock cycles max */
335 /* Unit: cycles of CPU clock. */
336 #define ADC_CONVERSION_TIME_MAX_CPU_CYCLES ((uint32_t) 210688) /*!< ADC conversion completion time-out value */
337
338 /**
339 * @}
340 */
341
342 /* Private macro -------------------------------------------------------------*/
343 /* Private variables ---------------------------------------------------------*/
344 /* Private function prototypes -----------------------------------------------*/
345 /* Exported functions --------------------------------------------------------*/
346
347 /** @defgroup ADC_Exported_Functions ADC Exported Functions
348 * @{
349 */
350
351 /** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions
352 * @brief ADC Initialization and Configuration functions
353 *
354 @verbatim
355 ===============================================================================
356 ##### Initialization and de-initialization functions #####
357 ===============================================================================
358 [..] This section provides functions allowing to:
359 (+) Initialize and configure the ADC.
360 (+) De-initialize the ADC.
361 @endverbatim
362 * @{
363 */
364
365 /**
366 * @brief Initialize the ADC peripheral and regular group according to
367 * parameters specified in structure "ADC_InitTypeDef".
368 * @note As prerequisite, ADC clock must be configured at RCC top level
369 * (refer to description of RCC configuration for ADC
370 * in header of this file).
371 * @note Possibility to update parameters on the fly:
372 * This function initializes the ADC MSP (HAL_ADC_MspInit()) only when
373 * coming from ADC state reset. Following calls to this function can
374 * be used to reconfigure some parameters of ADC_InitTypeDef
375 * structure on the fly, without modifying MSP configuration. If ADC
376 * MSP has to be modified again, HAL_ADC_DeInit() must be called
377 * before HAL_ADC_Init().
378 * The setting of these parameters is conditioned to ADC state.
379 * For parameters constraints, see comments of structure
380 * "ADC_InitTypeDef".
381 * @note This function configures the ADC within 2 scopes: scope of entire
382 * ADC and scope of regular group. For parameters details, see comments
383 * of structure "ADC_InitTypeDef".
384 * @note Parameters related to common ADC registers (ADC clock mode) are set
385 * only if all ADCs are disabled.
386 * If this is not the case, these common parameters setting are
387 * bypassed without error reporting: it can be the intended behaviour in
388 * case of update of a parameter of ADC_InitTypeDef on the fly,
389 * without disabling the other ADCs.
390 * @param hadc ADC handle
391 * @retval HAL status
392 */
HAL_ADC_Init(ADC_HandleTypeDef * hadc)393 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc)
394 {
395 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
396 uint32_t tmpCFGR;
397 uint32_t tmp_adc_reg_is_conversion_on_going;
398 __IO uint32_t wait_loop_index = 0UL;
399 uint32_t tmp_adc_is_conversion_on_going_regular;
400 uint32_t tmp_adc_is_conversion_on_going_injected;
401
402 /* Check ADC handle */
403 if (hadc == NULL)
404 {
405 return HAL_ERROR;
406 }
407
408 /* Check the parameters */
409 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
410 assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler));
411 assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution));
412 assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
413 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
414 assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
415 assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv));
416 assert_param(IS_ADC_CONVERSIONDATAMGT(hadc->Init.ConversionDataManagement));
417 assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
418 assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun));
419 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait));
420 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OversamplingMode));
421
422 if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
423 {
424 assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
425 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
426
427 if (hadc->Init.DiscontinuousConvMode == ENABLE)
428 {
429 assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion));
430 }
431 }
432
433 /* DISCEN and CONT bits cannot be set at the same time */
434 assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (hadc->Init.ContinuousConvMode == ENABLE)));
435
436 /* Actions performed only if ADC is coming from state reset: */
437 /* - Initialization of ADC MSP */
438 if (hadc->State == HAL_ADC_STATE_RESET)
439 {
440 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
441 /* Init the ADC Callback settings */
442 hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback; /* Legacy weak callback */
443 hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback; /* Legacy weak callback */
444 hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback; /* Legacy weak callback */
445 hadc->ErrorCallback = HAL_ADC_ErrorCallback; /* Legacy weak callback */
446 hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback; /* Legacy weak callback */
447 hadc->InjectedQueueOverflowCallback = HAL_ADCEx_InjectedQueueOverflowCallback; /* Legacy weak callback */
448 hadc->LevelOutOfWindow2Callback = HAL_ADCEx_LevelOutOfWindow2Callback; /* Legacy weak callback */
449 hadc->LevelOutOfWindow3Callback = HAL_ADCEx_LevelOutOfWindow3Callback; /* Legacy weak callback */
450 hadc->EndOfSamplingCallback = HAL_ADCEx_EndOfSamplingCallback; /* Legacy weak callback */
451
452 if (hadc->MspInitCallback == NULL)
453 {
454 hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */
455 }
456
457 /* Init the low level hardware */
458 hadc->MspInitCallback(hadc);
459 #else
460 /* Init the low level hardware */
461 HAL_ADC_MspInit(hadc);
462 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
463
464 /* Set ADC error code to none */
465 ADC_CLEAR_ERRORCODE(hadc);
466
467 /* Initialize Lock */
468 hadc->Lock = HAL_UNLOCKED;
469 }
470
471 /* - Exit from deep-power-down mode and ADC voltage regulator enable */
472 if (LL_ADC_IsDeepPowerDownEnabled(hadc->Instance) != 0UL)
473 {
474 /* Disable ADC deep power down mode */
475 LL_ADC_DisableDeepPowerDown(hadc->Instance);
476
477 /* System was in deep power down mode, calibration must
478 be relaunched or a previously saved calibration factor
479 re-applied once the ADC voltage regulator is enabled */
480 }
481
482 if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL)
483 {
484 /* Enable ADC internal voltage regulator */
485 LL_ADC_EnableInternalRegulator(hadc->Instance);
486
487 /* Note: Variable divided by 2 to compensate partially */
488 /* CPU processing cycles, scaling in us split to not */
489 /* exceed 32 bits register capacity and handle low frequency. */
490 wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
491 while (wait_loop_index != 0UL)
492 {
493 wait_loop_index--;
494 }
495 }
496
497 /* Verification that ADC voltage regulator is correctly enabled, whether */
498 /* or not ADC is coming from state reset (if any potential problem of */
499 /* clocking, voltage regulator would not be enabled). */
500 if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL)
501 {
502 /* Update ADC state machine to error */
503 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
504
505 /* Set ADC error code to ADC peripheral internal error */
506 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
507
508 tmp_hal_status = HAL_ERROR;
509 }
510
511 /* Configuration of ADC parameters if previous preliminary actions are */
512 /* correctly completed and if there is no conversion on going on regular */
513 /* group (ADC may already be enabled at this point if HAL_ADC_Init() is */
514 /* called to update a parameter on the fly). */
515 tmp_adc_reg_is_conversion_on_going = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
516
517 if (((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
518 && (tmp_adc_reg_is_conversion_on_going == 0UL)
519 )
520 {
521 /* Set ADC state */
522 ADC_STATE_CLR_SET(hadc->State,
523 HAL_ADC_STATE_REG_BUSY,
524 HAL_ADC_STATE_BUSY_INTERNAL);
525
526 /* Configuration of common ADC parameters */
527
528 /* Parameters update conditioned to ADC state: */
529 /* Parameters that can be updated only when ADC is disabled: */
530 /* - clock configuration */
531 if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
532 {
533 if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
534 {
535 /* Reset configuration of ADC common register CCR: */
536 /* */
537 /* - ADC clock mode and ACC prescaler (CKMODE and PRESC bits)are set */
538 /* according to adc->Init.ClockPrescaler. It selects the clock */
539 /* source and sets the clock division factor. */
540 /* */
541 /* Some parameters of this register are not reset, since they are set */
542 /* by other functions and must be kept in case of usage of this */
543 /* function on the fly (update of a parameter of ADC_InitTypeDef */
544 /* without needing to reconfigure all other ADC groups/channels */
545 /* parameters): */
546 /* - when multimode feature is available, multimode-related */
547 /* parameters: MDMA, DMACFG, DELAY, DUAL (set by API */
548 /* HAL_ADCEx_MultiModeConfigChannel() ) */
549 /* - internal measurement paths: Vbat, temperature sensor, Vref */
550 /* (set into HAL_ADC_ConfigChannel() or */
551 /* HAL_ADCEx_InjectedConfigChannel() ) */
552 LL_ADC_SetCommonClock(__LL_ADC_COMMON_INSTANCE(hadc->Instance), hadc->Init.ClockPrescaler);
553 }
554 }
555
556 /* Configuration of ADC: */
557 /* - resolution Init.Resolution */
558 /* - external trigger to start conversion Init.ExternalTrigConv */
559 /* - external trigger polarity Init.ExternalTrigConvEdge */
560 /* - continuous conversion mode Init.ContinuousConvMode */
561 /* - overrun Init.Overrun */
562 /* - discontinuous mode Init.DiscontinuousConvMode */
563 /* - discontinuous mode channel count Init.NbrOfDiscConversion */
564 tmpCFGR = (ADC_CFGR_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) |
565 hadc->Init.Overrun |
566 hadc->Init.Resolution |
567 ADC_CFGR_REG_DISCONTINUOUS((uint32_t)hadc->Init.DiscontinuousConvMode));
568
569 if (hadc->Init.DiscontinuousConvMode == ENABLE)
570 {
571 tmpCFGR |= ADC_CFGR_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion);
572 }
573
574 /* Enable external trigger if trigger selection is different of software */
575 /* start. */
576 /* Note: This configuration keeps the hardware feature of parameter */
577 /* ExternalTrigConvEdge "trigger edge none" equivalent to */
578 /* software start. */
579 if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
580 {
581 tmpCFGR |= ((hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL)
582 | hadc->Init.ExternalTrigConvEdge
583 );
584 }
585
586 /* Update Configuration Register CFGR */
587 MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmpCFGR);
588
589 /* Parameters update conditioned to ADC state: */
590 /* Parameters that can be updated when ADC is disabled or enabled without */
591 /* conversion on going on regular and injected groups: */
592 /* - Conversion data management Init.ConversionDataManagement */
593 /* - LowPowerAutoWait feature Init.LowPowerAutoWait */
594 /* - Oversampling parameters Init.Oversampling */
595 tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
596 tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
597 if ((tmp_adc_is_conversion_on_going_regular == 0UL)
598 && (tmp_adc_is_conversion_on_going_injected == 0UL)
599 )
600 {
601 tmpCFGR = (
602 ADC_CFGR_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) |
603 ADC_CFGR_DMACONTREQ((uint32_t)hadc->Init.ConversionDataManagement));
604
605 MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmpCFGR);
606
607 if (hadc->Init.OversamplingMode == ENABLE)
608 {
609 assert_param(IS_ADC_OVERSAMPLING_RATIO(hadc->Init.Oversampling.Ratio));
610 assert_param(IS_ADC_RIGHT_BIT_SHIFT(hadc->Init.Oversampling.RightBitShift));
611 assert_param(IS_ADC_TRIGGERED_OVERSAMPLING_MODE(hadc->Init.Oversampling.TriggeredMode));
612 assert_param(IS_ADC_REGOVERSAMPLING_MODE(hadc->Init.Oversampling.OversamplingStopReset));
613
614 if ((hadc->Init.ExternalTrigConv == ADC_SOFTWARE_START)
615 || (hadc->Init.ExternalTrigConvEdge == ADC_EXTERNALTRIGCONVEDGE_NONE))
616 {
617 /* Multi trigger is not applicable to software-triggered conversions */
618 assert_param((hadc->Init.Oversampling.TriggeredMode == ADC_TRIGGEREDMODE_SINGLE_TRIGGER));
619 }
620
621 /* Configuration of Oversampler: */
622 /* - Oversampling Ratio */
623 /* - Right bit shift */
624 /* - Left bit shift */
625 /* - Triggered mode */
626 /* - Oversampling mode (continued/resumed) */
627 MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_FIELDS,
628 ADC_CFGR2_ROVSE |
629 ((hadc->Init.Oversampling.Ratio - 1UL) << ADC_CFGR2_OSR_Pos) |
630 hadc->Init.Oversampling.RightBitShift |
631 hadc->Init.Oversampling.TriggeredMode |
632 hadc->Init.Oversampling.OversamplingStopReset);
633
634 }
635 else
636 {
637 /* Disable ADC oversampling scope on ADC group regular */
638 CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE);
639 }
640
641 /* Set the LeftShift parameter: it is applied to the final result with or without oversampling */
642 MODIFY_REG(hadc->Instance->CFGR2, ADC_CFGR2_LSHIFT, hadc->Init.LeftBitShift);
643
644 /* Configure the BOOST Mode */
645 ADC_ConfigureBoostMode(hadc);
646 }
647
648 /* Configuration of regular group sequencer: */
649 /* - if scan mode is disabled, regular channels sequence length is set to */
650 /* 0x00: 1 channel converted (channel on regular rank 1) */
651 /* Parameter "NbrOfConversion" is discarded. */
652 /* Note: Scan mode is not present by hardware on this device, but */
653 /* emulated by software for alignment over all STM32 devices. */
654 /* - if scan mode is enabled, regular channels sequence length is set to */
655 /* parameter "NbrOfConversion". */
656
657 if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE)
658 {
659 /* Set number of ranks in regular group sequencer */
660 MODIFY_REG(hadc->Instance->SQR1, ADC_SQR1_L, (hadc->Init.NbrOfConversion - (uint8_t)1));
661 }
662 else
663 {
664 CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L);
665 }
666
667 /* Initialize the ADC state */
668 /* Clear HAL_ADC_STATE_BUSY_INTERNAL bit, set HAL_ADC_STATE_READY bit */
669 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY);
670 }
671 else
672 {
673 /* Update ADC state machine to error */
674 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
675
676 tmp_hal_status = HAL_ERROR;
677 }
678
679 return tmp_hal_status;
680 }
681
682 /**
683 * @brief Deinitialize the ADC peripheral registers to their default reset
684 * values, with deinitialization of the ADC MSP.
685 * @note For devices with several ADCs: reset of ADC common registers is done
686 * only if all ADCs sharing the same common group are disabled.
687 * (function "HAL_ADC_MspDeInit()" is also called under the same conditions:
688 * all ADC instances use the same core clock at RCC level, disabling
689 * the core clock reset all ADC instances).
690 * If this is not the case, reset of these common parameters reset is
691 * bypassed without error reporting: it can be the intended behavior in
692 * case of reset of a single ADC while the other ADCs sharing the same
693 * common group is still running.
694 * @note By default, HAL_ADC_DeInit() set ADC in mode deep power-down:
695 * this saves more power by reducing leakage currents
696 * and is particularly interesting before entering MCU low-power modes.
697 * @param hadc ADC handle
698 * @retval HAL status
699 */
HAL_ADC_DeInit(ADC_HandleTypeDef * hadc)700 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc)
701 {
702 HAL_StatusTypeDef tmp_hal_status;
703
704 /* Check ADC handle */
705 if (hadc == NULL)
706 {
707 return HAL_ERROR;
708 }
709
710 /* Check the parameters */
711 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
712
713 /* Set ADC state */
714 SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL);
715
716 /* Stop potential conversion on going */
717 tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
718
719 /* Disable ADC peripheral if conversions are effectively stopped */
720 /* Flush register JSQR: reset the queue sequencer when injected */
721 /* queue sequencer is enabled and ADC disabled. */
722 /* The software and hardware triggers of the injected sequence are both */
723 /* internally disabled just after the completion of the last valid */
724 /* injected sequence. */
725 SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQM);
726
727 /* Disable ADC peripheral if conversions are effectively stopped */
728 if (tmp_hal_status == HAL_OK)
729 {
730 /* Disable the ADC peripheral */
731 tmp_hal_status = ADC_Disable(hadc);
732
733 /* Check if ADC is effectively disabled */
734 if (tmp_hal_status == HAL_OK)
735 {
736 /* Change ADC state */
737 hadc->State = HAL_ADC_STATE_READY;
738 }
739 }
740
741 /* Note: HAL ADC deInit is done independently of ADC conversion stop */
742 /* and disable return status. In case of status fail, attempt to */
743 /* perform deinitialization anyway and it is up user code in */
744 /* in HAL_ADC_MspDeInit() to reset the ADC peripheral using */
745 /* system RCC hard reset. */
746
747 /* ========== Reset ADC registers ========== */
748 /* Reset register IER */
749 __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_AWD3 | ADC_IT_AWD2 | ADC_IT_AWD1 |
750 ADC_IT_JQOVF | ADC_IT_OVR |
751 ADC_IT_JEOS | ADC_IT_JEOC |
752 ADC_IT_EOS | ADC_IT_EOC |
753 ADC_IT_EOSMP | ADC_IT_RDY));
754
755 /* Reset register ISR */
756 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD3 | ADC_FLAG_AWD2 | ADC_FLAG_AWD1 |
757 ADC_FLAG_JQOVF | ADC_FLAG_OVR |
758 ADC_FLAG_JEOS | ADC_FLAG_JEOC |
759 ADC_FLAG_EOS | ADC_FLAG_EOC |
760 ADC_FLAG_EOSMP | ADC_FLAG_RDY));
761
762 /* Reset register CR */
763 /* Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART,
764 ADC_CR_ADCAL, ADC_CR_ADDIS and ADC_CR_ADEN are in access mode "read-set":
765 no direct reset applicable.
766 Update CR register to reset value where doable by software */
767 CLEAR_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN | ADC_CR_ADCALDIF);
768 SET_BIT(hadc->Instance->CR, ADC_CR_DEEPPWD);
769
770 /* Reset register CFGR */
771 CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN |
772 ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM |
773 ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN |
774 ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD |
775 ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL |
776 ADC_CFGR_RES | ADC_CFGR_DMNGT);
777 SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS);
778
779 /* Reset register CFGR2 */
780 CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSM | ADC_CFGR2_TROVS | ADC_CFGR2_OVSS |
781 ADC_CFGR2_OVSR | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE);
782
783 /* Reset register SMPR1 */
784 CLEAR_BIT(hadc->Instance->SMPR1, ADC_SMPR1_FIELDS);
785
786 /* Reset register SMPR2 */
787 CLEAR_BIT(hadc->Instance->SMPR2, ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | ADC_SMPR2_SMP16 |
788 ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | ADC_SMPR2_SMP13 |
789 ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | ADC_SMPR2_SMP10);
790
791 /* Reset register LTR1 and HTR1 */
792 CLEAR_BIT(hadc->Instance->LTR1, ADC_LTR1_LT1);
793 CLEAR_BIT(hadc->Instance->HTR1, ADC_HTR1_HT1);
794
795 /* Reset register LTR2 and HTR2*/
796 CLEAR_BIT(hadc->Instance->LTR2, ADC_LTR2_LT2);
797 CLEAR_BIT(hadc->Instance->HTR2, ADC_HTR2_HT2);
798
799 /* Reset register LTR3 and HTR3 */
800 CLEAR_BIT(hadc->Instance->LTR3, ADC_LTR2_LT2);
801 CLEAR_BIT(hadc->Instance->HTR3, ADC_HTR2_HT2);
802
803 /* Reset register SQR1 */
804 CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2 |
805 ADC_SQR1_SQ1 | ADC_SQR1_L);
806
807 /* Reset register SQR2 */
808 CLEAR_BIT(hadc->Instance->SQR2, ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7 |
809 ADC_SQR2_SQ6 | ADC_SQR2_SQ5);
810
811 /* Reset register SQR3 */
812 CLEAR_BIT(hadc->Instance->SQR3, ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12 |
813 ADC_SQR3_SQ11 | ADC_SQR3_SQ10);
814
815 /* Reset register SQR4 */
816 CLEAR_BIT(hadc->Instance->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15);
817
818 /* Register JSQR was reset when the ADC was disabled */
819
820 /* Reset register DR */
821 /* bits in access mode read only, no direct reset applicable*/
822
823 /* Reset register OFR1 */
824 CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_SSATE | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1);
825 /* Reset register OFR2 */
826 CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_SSATE | ADC_OFR2_OFFSET2_CH | ADC_OFR2_OFFSET2);
827 /* Reset register OFR3 */
828 CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_SSATE | ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3);
829 /* Reset register OFR4 */
830 CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_SSATE | ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4);
831
832 /* Reset registers JDR1, JDR2, JDR3, JDR4 */
833 /* bits in access mode read only, no direct reset applicable*/
834
835 /* Reset register AWD2CR */
836 CLEAR_BIT(hadc->Instance->AWD2CR, ADC_AWD2CR_AWD2CH);
837
838 /* Reset register AWD3CR */
839 CLEAR_BIT(hadc->Instance->AWD3CR, ADC_AWD3CR_AWD3CH);
840
841 /* Reset register DIFSEL */
842 CLEAR_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_DIFSEL);
843
844 /* Reset register CALFACT */
845 CLEAR_BIT(hadc->Instance->CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S);
846
847
848 /* ========== Reset common ADC registers ========== */
849
850 /* Software is allowed to change common parameters only when all the other
851 ADCs are disabled. */
852 if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
853 {
854 /* Reset configuration of ADC common register CCR:
855 - clock mode: CKMODE, PRESCEN
856 - multimode related parameters(when this feature is available): DELAY, DUAL
857 (set into HAL_ADCEx_MultiModeConfigChannel() API)
858 - internal measurement paths: Vbat, temperature sensor, Vref (set into
859 HAL_ADC_ConfigChannel() or HAL_ADCEx_InjectedConfigChannel() )
860 */
861 ADC_CLEAR_COMMON_CONTROL_REGISTER(hadc);
862
863 /* ========== Hard reset ADC peripheral ========== */
864 /* Performs a global reset of the entire ADC peripherals instances */
865 /* sharing the same common ADC instance: ADC state is forced to */
866 /* a similar state as after device power-on. */
867 /* Note: A possible implementation is to add RCC bus reset of ADC */
868 /* (for example, using macro */
869 /* __HAL_RCC_ADC..._FORCE_RESET()/..._RELEASE_RESET()/..._CLK_DISABLE()) */
870 /* in function "void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc)": */
871 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
872 if (hadc->MspDeInitCallback == NULL)
873 {
874 hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */
875 }
876
877 /* DeInit the low level hardware */
878 hadc->MspDeInitCallback(hadc);
879 #else
880 /* DeInit the low level hardware */
881 HAL_ADC_MspDeInit(hadc);
882 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
883 }
884
885 /* Set ADC error code to none */
886 ADC_CLEAR_ERRORCODE(hadc);
887
888 /* Reset injected channel configuration parameters */
889 hadc->InjectionConfig.ContextQueue = 0;
890 hadc->InjectionConfig.ChannelCount = 0;
891
892 /* Set ADC state */
893 hadc->State = HAL_ADC_STATE_RESET;
894
895 __HAL_UNLOCK(hadc);
896
897 return tmp_hal_status;
898 }
899
900 /**
901 * @brief Initialize the ADC MSP.
902 * @param hadc ADC handle
903 * @retval None
904 */
HAL_ADC_MspInit(ADC_HandleTypeDef * hadc)905 __weak void HAL_ADC_MspInit(ADC_HandleTypeDef *hadc)
906 {
907 /* Prevent unused argument(s) compilation warning */
908 UNUSED(hadc);
909
910 /* NOTE : This function should not be modified. When the callback is needed,
911 function HAL_ADC_MspInit must be implemented in the user file.
912 */
913 }
914
915 /**
916 * @brief DeInitialize the ADC MSP.
917 * @param hadc ADC handle
918 * @note All ADC instances use the same core clock at RCC level, disabling
919 * the core clock reset all ADC instances).
920 * @retval None
921 */
HAL_ADC_MspDeInit(ADC_HandleTypeDef * hadc)922 __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef *hadc)
923 {
924 /* Prevent unused argument(s) compilation warning */
925 UNUSED(hadc);
926
927 /* NOTE : This function should not be modified. When the callback is needed,
928 function HAL_ADC_MspDeInit must be implemented in the user file.
929 */
930 }
931
932 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
933 /**
934 * @brief Register a User ADC Callback
935 * To be used instead of the weak predefined callback
936 * @param hadc Pointer to a ADC_HandleTypeDef structure that contains
937 * the configuration information for the specified ADC.
938 * @param CallbackID ID of the callback to be registered
939 * This parameter can be one of the following values:
940 * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID
941 * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion DMA half-transfer callback ID
942 * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID
943 * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID
944 * @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID
945 * @arg @ref HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID ADC group injected context queue overflow callback ID
946 * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID ADC analog watchdog 2 callback ID
947 * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID ADC analog watchdog 3 callback ID
948 * @arg @ref HAL_ADC_END_OF_SAMPLING_CB_ID ADC end of sampling callback ID
949 * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID
950 * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID
951 * @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID
952 * @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID
953 * @param pCallback pointer to the Callback function
954 * @retval HAL status
955 */
HAL_ADC_RegisterCallback(ADC_HandleTypeDef * hadc,HAL_ADC_CallbackIDTypeDef CallbackID,pADC_CallbackTypeDef pCallback)956 HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID,
957 pADC_CallbackTypeDef pCallback)
958 {
959 HAL_StatusTypeDef status = HAL_OK;
960
961 if (pCallback == NULL)
962 {
963 /* Update the error code */
964 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
965
966 return HAL_ERROR;
967 }
968
969 if ((hadc->State & HAL_ADC_STATE_READY) != 0UL)
970 {
971 switch (CallbackID)
972 {
973 case HAL_ADC_CONVERSION_COMPLETE_CB_ID :
974 hadc->ConvCpltCallback = pCallback;
975 break;
976
977 case HAL_ADC_CONVERSION_HALF_CB_ID :
978 hadc->ConvHalfCpltCallback = pCallback;
979 break;
980
981 case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID :
982 hadc->LevelOutOfWindowCallback = pCallback;
983 break;
984
985 case HAL_ADC_ERROR_CB_ID :
986 hadc->ErrorCallback = pCallback;
987 break;
988
989 case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID :
990 hadc->InjectedConvCpltCallback = pCallback;
991 break;
992
993 case HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID :
994 hadc->InjectedQueueOverflowCallback = pCallback;
995 break;
996
997 case HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID :
998 hadc->LevelOutOfWindow2Callback = pCallback;
999 break;
1000
1001 case HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID :
1002 hadc->LevelOutOfWindow3Callback = pCallback;
1003 break;
1004
1005 case HAL_ADC_END_OF_SAMPLING_CB_ID :
1006 hadc->EndOfSamplingCallback = pCallback;
1007 break;
1008
1009 case HAL_ADC_MSPINIT_CB_ID :
1010 hadc->MspInitCallback = pCallback;
1011 break;
1012
1013 case HAL_ADC_MSPDEINIT_CB_ID :
1014 hadc->MspDeInitCallback = pCallback;
1015 break;
1016
1017 default :
1018 /* Update the error code */
1019 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
1020
1021 /* Return error status */
1022 status = HAL_ERROR;
1023 break;
1024 }
1025 }
1026 else if (HAL_ADC_STATE_RESET == hadc->State)
1027 {
1028 switch (CallbackID)
1029 {
1030 case HAL_ADC_MSPINIT_CB_ID :
1031 hadc->MspInitCallback = pCallback;
1032 break;
1033
1034 case HAL_ADC_MSPDEINIT_CB_ID :
1035 hadc->MspDeInitCallback = pCallback;
1036 break;
1037
1038 default :
1039 /* Update the error code */
1040 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
1041
1042 /* Return error status */
1043 status = HAL_ERROR;
1044 break;
1045 }
1046 }
1047 else
1048 {
1049 /* Update the error code */
1050 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
1051
1052 /* Return error status */
1053 status = HAL_ERROR;
1054 }
1055
1056 return status;
1057 }
1058
1059 /**
1060 * @brief Unregister a ADC Callback
1061 * ADC callback is redirected to the weak predefined callback
1062 * @param hadc Pointer to a ADC_HandleTypeDef structure that contains
1063 * the configuration information for the specified ADC.
1064 * @param CallbackID ID of the callback to be unregistered
1065 * This parameter can be one of the following values:
1066 * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID
1067 * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion DMA half-transfer callback ID
1068 * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID
1069 * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID
1070 * @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID
1071 * @arg @ref HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID ADC group injected context queue overflow callback ID
1072 * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID ADC analog watchdog 2 callback ID
1073 * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID ADC analog watchdog 3 callback ID
1074 * @arg @ref HAL_ADC_END_OF_SAMPLING_CB_ID ADC end of sampling callback ID
1075 * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID
1076 * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID
1077 * @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID
1078 * @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID
1079 * @retval HAL status
1080 */
HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef * hadc,HAL_ADC_CallbackIDTypeDef CallbackID)1081 HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID)
1082 {
1083 HAL_StatusTypeDef status = HAL_OK;
1084
1085 if ((hadc->State & HAL_ADC_STATE_READY) != 0UL)
1086 {
1087 switch (CallbackID)
1088 {
1089 case HAL_ADC_CONVERSION_COMPLETE_CB_ID :
1090 hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback;
1091 break;
1092
1093 case HAL_ADC_CONVERSION_HALF_CB_ID :
1094 hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback;
1095 break;
1096
1097 case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID :
1098 hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback;
1099 break;
1100
1101 case HAL_ADC_ERROR_CB_ID :
1102 hadc->ErrorCallback = HAL_ADC_ErrorCallback;
1103 break;
1104
1105 case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID :
1106 hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback;
1107 break;
1108
1109 case HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID :
1110 hadc->InjectedQueueOverflowCallback = HAL_ADCEx_InjectedQueueOverflowCallback;
1111 break;
1112
1113 case HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID :
1114 hadc->LevelOutOfWindow2Callback = HAL_ADCEx_LevelOutOfWindow2Callback;
1115 break;
1116
1117 case HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID :
1118 hadc->LevelOutOfWindow3Callback = HAL_ADCEx_LevelOutOfWindow3Callback;
1119 break;
1120
1121 case HAL_ADC_END_OF_SAMPLING_CB_ID :
1122 hadc->EndOfSamplingCallback = HAL_ADCEx_EndOfSamplingCallback;
1123 break;
1124
1125 case HAL_ADC_MSPINIT_CB_ID :
1126 hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */
1127 break;
1128
1129 case HAL_ADC_MSPDEINIT_CB_ID :
1130 hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */
1131 break;
1132
1133 default :
1134 /* Update the error code */
1135 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
1136
1137 /* Return error status */
1138 status = HAL_ERROR;
1139 break;
1140 }
1141 }
1142 else if (HAL_ADC_STATE_RESET == hadc->State)
1143 {
1144 switch (CallbackID)
1145 {
1146 case HAL_ADC_MSPINIT_CB_ID :
1147 hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */
1148 break;
1149
1150 case HAL_ADC_MSPDEINIT_CB_ID :
1151 hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */
1152 break;
1153
1154 default :
1155 /* Update the error code */
1156 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
1157
1158 /* Return error status */
1159 status = HAL_ERROR;
1160 break;
1161 }
1162 }
1163 else
1164 {
1165 /* Update the error code */
1166 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK;
1167
1168 /* Return error status */
1169 status = HAL_ERROR;
1170 }
1171
1172 return status;
1173 }
1174
1175 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
1176
1177 /**
1178 * @}
1179 */
1180
1181 /** @defgroup ADC_Exported_Functions_Group2 ADC Input and Output operation functions
1182 * @brief ADC IO operation functions
1183 *
1184 @verbatim
1185 ===============================================================================
1186 ##### IO operation functions #####
1187 ===============================================================================
1188 [..] This section provides functions allowing to:
1189 (+) Start conversion of regular group.
1190 (+) Stop conversion of regular group.
1191 (+) Poll for conversion complete on regular group.
1192 (+) Poll for conversion event.
1193 (+) Get result of regular channel conversion.
1194 (+) Start conversion of regular group and enable interruptions.
1195 (+) Stop conversion of regular group and disable interruptions.
1196 (+) Handle ADC interrupt request
1197 (+) Start conversion of regular group and enable DMA transfer.
1198 (+) Stop conversion of regular group and disable ADC DMA transfer.
1199 @endverbatim
1200 * @{
1201 */
1202
1203 /**
1204 * @brief Enable ADC, start conversion of regular group.
1205 * @note Interruptions enabled in this function: None.
1206 * @note Case of multimode enabled (when multimode feature is available):
1207 * if ADC is Slave, ADC is enabled but conversion is not started,
1208 * if ADC is master, ADC is enabled and multimode conversion is started.
1209 * @param hadc ADC handle
1210 * @retval HAL status
1211 */
HAL_ADC_Start(ADC_HandleTypeDef * hadc)1212 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef *hadc)
1213 {
1214 HAL_StatusTypeDef tmp_hal_status;
1215 #if defined(ADC_MULTIMODE_SUPPORT)
1216 const ADC_TypeDef *tmpADC_Master;
1217 uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
1218 #endif
1219
1220 /* Check the parameters */
1221 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1222
1223 /* Perform ADC enable and conversion start if no conversion is on going */
1224 if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
1225 {
1226 /* Process locked */
1227 __HAL_LOCK(hadc);
1228
1229 /* Enable the ADC peripheral */
1230 tmp_hal_status = ADC_Enable(hadc);
1231
1232 /* Start conversion if ADC is effectively enabled */
1233 if (tmp_hal_status == HAL_OK)
1234 {
1235 /* Set ADC state */
1236 /* - Clear state bitfield related to regular group conversion results */
1237 /* - Set state bitfield related to regular operation */
1238 ADC_STATE_CLR_SET(hadc->State,
1239 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
1240 HAL_ADC_STATE_REG_BUSY);
1241
1242 #if defined(ADC_MULTIMODE_SUPPORT)
1243 /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
1244 - if ADC instance is master or if multimode feature is not available
1245 - if multimode setting is disabled (ADC instance slave in independent mode) */
1246 if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
1247 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
1248 )
1249 {
1250 CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
1251 }
1252 #endif
1253
1254 /* Set ADC error code */
1255 /* Check if a conversion is on going on ADC group injected */
1256 if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY))
1257 {
1258 /* Reset ADC error code fields related to regular conversions only */
1259 CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
1260 }
1261 else
1262 {
1263 /* Reset all ADC error code fields */
1264 ADC_CLEAR_ERRORCODE(hadc);
1265 }
1266
1267 /* Clear ADC group regular conversion flag and overrun flag */
1268 /* (To ensure of no unknown state from potential previous ADC operations) */
1269 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
1270
1271 /* Unlock before starting ADC conversions: in case of potential */
1272 /* interruption, to let the process to ADC IRQ Handler. */
1273 __HAL_UNLOCK(hadc);
1274
1275 /* Enable conversion of regular group. */
1276 /* If software start has been selected, conversion starts immediately. */
1277 /* If external trigger has been selected, conversion will start at next */
1278 /* trigger event. */
1279 /* Case of multimode enabled (when multimode feature is available): */
1280 /* - if ADC is slave and dual regular conversions are enabled, ADC is */
1281 /* enabled only (conversion is not started), */
1282 /* - if ADC is master, ADC is enabled and conversion is started. */
1283 #if defined(ADC_MULTIMODE_SUPPORT)
1284 if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
1285 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
1286 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
1287 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
1288 )
1289 {
1290 /* ADC instance is not a multimode slave instance with multimode regular conversions enabled */
1291 if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != 0UL)
1292 {
1293 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
1294 }
1295
1296 /* Start ADC group regular conversion */
1297 LL_ADC_REG_StartConversion(hadc->Instance);
1298 }
1299 else
1300 {
1301 /* ADC instance is a multimode slave instance with multimode regular conversions enabled */
1302 SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
1303 /* if Master ADC JAUTO bit is set, update Slave State in setting
1304 HAL_ADC_STATE_INJ_BUSY bit and in resetting HAL_ADC_STATE_INJ_EOC bit */
1305 tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
1306 if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != 0UL)
1307 {
1308 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
1309 }
1310
1311 }
1312 #else
1313 if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != 0UL)
1314 {
1315 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
1316 }
1317
1318 /* Start ADC group regular conversion */
1319 LL_ADC_REG_StartConversion(hadc->Instance);
1320 #endif
1321 }
1322 else
1323 {
1324 __HAL_UNLOCK(hadc);
1325 }
1326 }
1327 else
1328 {
1329 tmp_hal_status = HAL_BUSY;
1330 }
1331
1332 return tmp_hal_status;
1333 }
1334
1335 /**
1336 * @brief Stop ADC conversion of regular group (and injected channels in
1337 * case of auto_injection mode), disable ADC peripheral.
1338 * @note: ADC peripheral disable is forcing stop of potential
1339 * conversion on injected group. If injected group is under use, it
1340 * should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
1341 * @param hadc ADC handle
1342 * @retval HAL status.
1343 */
HAL_ADC_Stop(ADC_HandleTypeDef * hadc)1344 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef *hadc)
1345 {
1346 HAL_StatusTypeDef tmp_hal_status;
1347
1348 /* Check the parameters */
1349 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1350
1351 /* Process locked */
1352 __HAL_LOCK(hadc);
1353
1354 /* 1. Stop potential conversion on going, on ADC groups regular and injected */
1355 tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
1356
1357 /* Disable ADC peripheral if conversions are effectively stopped */
1358 if (tmp_hal_status == HAL_OK)
1359 {
1360 /* 2. Disable the ADC peripheral */
1361 tmp_hal_status = ADC_Disable(hadc);
1362
1363 /* Check if ADC is effectively disabled */
1364 if (tmp_hal_status == HAL_OK)
1365 {
1366 /* Set ADC state */
1367 ADC_STATE_CLR_SET(hadc->State,
1368 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
1369 HAL_ADC_STATE_READY);
1370 }
1371 }
1372
1373 __HAL_UNLOCK(hadc);
1374
1375 return tmp_hal_status;
1376 }
1377
1378 /**
1379 * @brief Wait for regular group conversion to be completed.
1380 * @note ADC conversion flags EOS (end of sequence) and EOC (end of
1381 * conversion) are cleared by this function, with an exception:
1382 * if low power feature "LowPowerAutoWait" is enabled, flags are
1383 * not cleared to not interfere with this feature until data register
1384 * is read using function HAL_ADC_GetValue().
1385 * @note This function cannot be used in a particular setup: ADC configured
1386 * in DMA mode and polling for end of each conversion (ADC init
1387 * parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV).
1388 * In this case, DMA resets the flag EOC and polling cannot be
1389 * performed on each conversion. Nevertheless, polling can still
1390 * be performed on the complete sequence (ADC init
1391 * parameter "EOCSelection" set to ADC_EOC_SEQ_CONV).
1392 * @param hadc ADC handle
1393 * @param Timeout Timeout value in millisecond.
1394 * @retval HAL status
1395 */
HAL_ADC_PollForConversion(ADC_HandleTypeDef * hadc,uint32_t Timeout)1396 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef *hadc, uint32_t Timeout)
1397 {
1398 uint32_t tickstart;
1399 uint32_t tmp_Flag_End;
1400 uint32_t tmp_cfgr;
1401 #if defined(ADC_MULTIMODE_SUPPORT)
1402 const ADC_TypeDef *tmpADC_Master;
1403 uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
1404 #endif
1405
1406 /* Check the parameters */
1407 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1408
1409 /* If end of conversion selected to end of sequence conversions */
1410 if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV)
1411 {
1412 tmp_Flag_End = ADC_FLAG_EOS;
1413 }
1414 /* If end of conversion selected to end of unitary conversion */
1415 else /* ADC_EOC_SINGLE_CONV */
1416 {
1417 /* Verification that ADC configuration is compliant with polling for */
1418 /* each conversion: */
1419 /* Particular case is ADC configured in DMA mode and ADC sequencer with */
1420 /* several ranks and polling for end of each conversion. */
1421 /* For code simplicity sake, this particular case is generalized to */
1422 /* ADC configured in DMA mode and and polling for end of each conversion. */
1423 #if defined(ADC_MULTIMODE_SUPPORT)
1424 if ((tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
1425 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
1426 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
1427 )
1428 {
1429 /* Check DMNGT bit in handle ADC CFGR register */
1430 if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMNGT_0) != 0UL)
1431 {
1432 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
1433 return HAL_ERROR;
1434 }
1435 else
1436 {
1437 tmp_Flag_End = (ADC_FLAG_EOC);
1438 }
1439 }
1440 else
1441 {
1442 /* Check ADC DMA mode in multimode on ADC group regular */
1443 if (LL_ADC_GetMultiDMATransfer(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) != LL_ADC_MULTI_REG_DMA_EACH_ADC)
1444 {
1445 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
1446 return HAL_ERROR;
1447 }
1448 else
1449 {
1450 tmp_Flag_End = (ADC_FLAG_EOC);
1451 }
1452 }
1453 #else
1454 /* Check ADC DMA mode */
1455 if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMNGT_0) != 0UL)
1456 {
1457 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
1458 return HAL_ERROR;
1459 }
1460 else
1461 {
1462 tmp_Flag_End = (ADC_FLAG_EOC);
1463 }
1464 #endif
1465 }
1466
1467 /* Get tick count */
1468 tickstart = HAL_GetTick();
1469
1470 /* Wait until End of unitary conversion or sequence conversions flag is raised */
1471 while ((hadc->Instance->ISR & tmp_Flag_End) == 0UL)
1472 {
1473 /* Check if timeout is disabled (set to infinite wait) */
1474 if (Timeout != HAL_MAX_DELAY)
1475 {
1476 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
1477 {
1478 /* New check to avoid false timeout detection in case of preemption */
1479 if ((hadc->Instance->ISR & tmp_Flag_End) == 0UL)
1480 {
1481 /* Update ADC state machine to timeout */
1482 SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
1483
1484 __HAL_UNLOCK(hadc);
1485
1486 return HAL_TIMEOUT;
1487 }
1488 }
1489 }
1490 }
1491
1492 /* Update ADC state machine */
1493 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
1494
1495 /* Determine whether any further conversion upcoming on group regular */
1496 /* by external trigger, continuous mode or scan sequence on going. */
1497 if ((LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL)
1498 && (hadc->Init.ContinuousConvMode == DISABLE)
1499 )
1500 {
1501 /* Check whether end of sequence is reached */
1502 if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS))
1503 {
1504 /* Set ADC state */
1505 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
1506
1507 if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL)
1508 {
1509 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
1510 }
1511 }
1512 }
1513
1514 /* Get relevant register CFGR in ADC instance of ADC master or slave */
1515 /* in function of multimode state (for devices with multimode */
1516 /* available). */
1517 #if defined(ADC_MULTIMODE_SUPPORT)
1518 if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
1519 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
1520 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
1521 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
1522 )
1523 {
1524 /* Retrieve handle ADC CFGR register */
1525 tmp_cfgr = READ_REG(hadc->Instance->CFGR);
1526 }
1527 else
1528 {
1529 /* Retrieve Master ADC CFGR register */
1530 tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
1531 tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
1532 }
1533 #else
1534 /* Retrieve handle ADC CFGR register */
1535 tmp_cfgr = READ_REG(hadc->Instance->CFGR);
1536 #endif
1537
1538 /* Clear polled flag */
1539 if (tmp_Flag_End == ADC_FLAG_EOS)
1540 {
1541 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOS);
1542 }
1543 else
1544 {
1545 /* Clear end of conversion EOC flag of regular group if low power feature */
1546 /* "LowPowerAutoWait " is disabled, to not interfere with this feature */
1547 /* until data register is read using function HAL_ADC_GetValue(). */
1548 if (READ_BIT(tmp_cfgr, ADC_CFGR_AUTDLY) == 0UL)
1549 {
1550 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS));
1551 }
1552 }
1553
1554 return HAL_OK;
1555 }
1556
1557 /**
1558 * @brief Poll for ADC event.
1559 * @param hadc ADC handle
1560 * @param EventType the ADC event type.
1561 * This parameter can be one of the following values:
1562 * @arg @ref ADC_EOSMP_EVENT ADC End of Sampling event
1563 * @arg @ref ADC_AWD1_EVENT ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 devices)
1564 * @arg @ref ADC_AWD2_EVENT ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 families)
1565 * @arg @ref ADC_AWD3_EVENT ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 families)
1566 * @arg @ref ADC_OVR_EVENT ADC Overrun event
1567 * @arg @ref ADC_JQOVF_EVENT ADC Injected context queue overflow event
1568 * @param Timeout Timeout value in millisecond.
1569 * @note The relevant flag is cleared if found to be set, except for ADC_FLAG_OVR.
1570 * Indeed, the latter is reset only if hadc->Init.Overrun field is set
1571 * to ADC_OVR_DATA_OVERWRITTEN. Otherwise, data register may be potentially overwritten
1572 * by a new converted data as soon as OVR is cleared.
1573 * To reset OVR flag once the preserved data is retrieved, the user can resort
1574 * to macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
1575 * @retval HAL status
1576 */
HAL_ADC_PollForEvent(ADC_HandleTypeDef * hadc,uint32_t EventType,uint32_t Timeout)1577 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef *hadc, uint32_t EventType, uint32_t Timeout)
1578 {
1579 uint32_t tickstart;
1580
1581 /* Check the parameters */
1582 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1583 assert_param(IS_ADC_EVENT_TYPE(EventType));
1584
1585 /* Get tick count */
1586 tickstart = HAL_GetTick();
1587
1588 /* Check selected event flag */
1589 while (__HAL_ADC_GET_FLAG(hadc, EventType) == 0UL)
1590 {
1591 /* Check if timeout is disabled (set to infinite wait) */
1592 if (Timeout != HAL_MAX_DELAY)
1593 {
1594 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0UL))
1595 {
1596 /* New check to avoid false timeout detection in case of preemption */
1597 if (__HAL_ADC_GET_FLAG(hadc, EventType) == 0UL)
1598 {
1599 /* Update ADC state machine to timeout */
1600 SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT);
1601
1602 __HAL_UNLOCK(hadc);
1603
1604 return HAL_TIMEOUT;
1605 }
1606 }
1607 }
1608 }
1609
1610 switch (EventType)
1611 {
1612 /* End Of Sampling event */
1613 case ADC_EOSMP_EVENT:
1614 /* Set ADC state */
1615 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP);
1616
1617 /* Clear the End Of Sampling flag */
1618 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP);
1619
1620 break;
1621
1622 /* Analog watchdog (level out of window) event */
1623 /* Note: In case of several analog watchdog enabled, if needed to know */
1624 /* which one triggered and on which ADCx, test ADC state of analog watchdog */
1625 /* flags HAL_ADC_STATE_AWD1/2/3 using function "HAL_ADC_GetState()". */
1626 /* For example: */
1627 /* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) " */
1628 /* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD2) != 0UL) " */
1629 /* " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD3) != 0UL) " */
1630
1631 /* Check analog watchdog 1 flag */
1632 case ADC_AWD_EVENT:
1633 /* Set ADC state */
1634 SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
1635
1636 /* Clear ADC analog watchdog flag */
1637 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
1638
1639 break;
1640
1641 /* Check analog watchdog 2 flag */
1642 case ADC_AWD2_EVENT:
1643 /* Set ADC state */
1644 SET_BIT(hadc->State, HAL_ADC_STATE_AWD2);
1645
1646 /* Clear ADC analog watchdog flag */
1647 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
1648
1649 break;
1650
1651 /* Check analog watchdog 3 flag */
1652 case ADC_AWD3_EVENT:
1653 /* Set ADC state */
1654 SET_BIT(hadc->State, HAL_ADC_STATE_AWD3);
1655
1656 /* Clear ADC analog watchdog flag */
1657 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
1658
1659 break;
1660
1661 /* Injected context queue overflow event */
1662 case ADC_JQOVF_EVENT:
1663 /* Set ADC state */
1664 SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
1665
1666 /* Set ADC error code to Injected context queue overflow */
1667 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
1668
1669 /* Clear ADC Injected context queue overflow flag */
1670 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF);
1671
1672 break;
1673
1674 /* Overrun event */
1675 default: /* Case ADC_OVR_EVENT */
1676 /* If overrun is set to overwrite previous data, overrun event is not */
1677 /* considered as an error. */
1678 /* (cf ref manual "Managing conversions without using the DMA and without */
1679 /* overrun ") */
1680 if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
1681 {
1682 /* Set ADC state */
1683 SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
1684
1685 /* Set ADC error code to overrun */
1686 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
1687 }
1688 else
1689 {
1690 /* Clear ADC Overrun flag only if Overrun is set to ADC_OVR_DATA_OVERWRITTEN
1691 otherwise, data register is potentially overwritten by new converted data as soon
1692 as OVR is cleared. */
1693 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
1694 }
1695 break;
1696 }
1697
1698 return HAL_OK;
1699 }
1700
1701 /**
1702 * @brief Enable ADC, start conversion of regular group with interruption.
1703 * @note Interruptions enabled in this function according to initialization
1704 * setting : EOC (end of conversion), EOS (end of sequence),
1705 * OVR overrun.
1706 * Each of these interruptions has its dedicated callback function.
1707 * @note Case of multimode enabled (when multimode feature is available):
1708 * HAL_ADC_Start_IT() must be called for ADC Slave first, then for
1709 * ADC Master.
1710 * For ADC Slave, ADC is enabled only (conversion is not started).
1711 * For ADC Master, ADC is enabled and multimode conversion is started.
1712 * @note To guarantee a proper reset of all interruptions once all the needed
1713 * conversions are obtained, HAL_ADC_Stop_IT() must be called to ensure
1714 * a correct stop of the IT-based conversions.
1715 * @note By default, HAL_ADC_Start_IT() does not enable the End Of Sampling
1716 * interruption. If required (e.g. in case of oversampling with trigger
1717 * mode), the user must:
1718 * 1. first clear the EOSMP flag if set with macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP)
1719 * 2. then enable the EOSMP interrupt with macro __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOSMP)
1720 * before calling HAL_ADC_Start_IT().
1721 * @param hadc ADC handle
1722 * @retval HAL status
1723 */
HAL_ADC_Start_IT(ADC_HandleTypeDef * hadc)1724 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef *hadc)
1725 {
1726 HAL_StatusTypeDef tmp_hal_status;
1727 #if defined(ADC_MULTIMODE_SUPPORT)
1728 const ADC_TypeDef *tmpADC_Master;
1729 uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
1730 #endif
1731
1732 /* Check the parameters */
1733 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1734
1735 /* Perform ADC enable and conversion start if no conversion is on going */
1736 if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
1737 {
1738 /* Process locked */
1739 __HAL_LOCK(hadc);
1740
1741 /* Enable the ADC peripheral */
1742 tmp_hal_status = ADC_Enable(hadc);
1743
1744 /* Start conversion if ADC is effectively enabled */
1745 if (tmp_hal_status == HAL_OK)
1746 {
1747 /* Set ADC state */
1748 /* - Clear state bitfield related to regular group conversion results */
1749 /* - Set state bitfield related to regular operation */
1750 ADC_STATE_CLR_SET(hadc->State,
1751 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
1752 HAL_ADC_STATE_REG_BUSY);
1753
1754 #if defined(ADC_MULTIMODE_SUPPORT)
1755 /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
1756 - if ADC instance is master or if multimode feature is not available
1757 - if multimode setting is disabled (ADC instance slave in independent mode) */
1758 if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
1759 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
1760 )
1761 {
1762 CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
1763 }
1764 #endif
1765
1766 /* Set ADC error code */
1767 /* Check if a conversion is on going on ADC group injected */
1768 if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) != 0UL)
1769 {
1770 /* Reset ADC error code fields related to regular conversions only */
1771 CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
1772 }
1773 else
1774 {
1775 /* Reset all ADC error code fields */
1776 ADC_CLEAR_ERRORCODE(hadc);
1777 }
1778
1779 /* Clear ADC group regular conversion flag and overrun flag */
1780 /* (To ensure of no unknown state from potential previous ADC operations) */
1781 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
1782
1783 /* Unlock before starting ADC conversions: in case of potential */
1784 /* interruption, to let the process to ADC IRQ Handler. */
1785 __HAL_UNLOCK(hadc);
1786
1787 /* Disable all interruptions before enabling the desired ones */
1788 __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
1789
1790 /* Enable ADC end of conversion interrupt */
1791 switch (hadc->Init.EOCSelection)
1792 {
1793 case ADC_EOC_SEQ_CONV:
1794 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOS);
1795 break;
1796 /* case ADC_EOC_SINGLE_CONV */
1797 default:
1798 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC);
1799 break;
1800 }
1801
1802 /* Enable ADC overrun interrupt */
1803 /* If hadc->Init.Overrun is set to ADC_OVR_DATA_PRESERVED, only then is
1804 ADC_IT_OVR enabled; otherwise data overwrite is considered as normal
1805 behavior and no CPU time is lost for a non-processed interruption */
1806 if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
1807 {
1808 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
1809 }
1810
1811 /* Enable conversion of regular group. */
1812 /* If software start has been selected, conversion starts immediately. */
1813 /* If external trigger has been selected, conversion will start at next */
1814 /* trigger event. */
1815 /* Case of multimode enabled (when multimode feature is available): */
1816 /* - if ADC is slave and dual regular conversions are enabled, ADC is */
1817 /* enabled only (conversion is not started), */
1818 /* - if ADC is master, ADC is enabled and conversion is started. */
1819 #if defined(ADC_MULTIMODE_SUPPORT)
1820 if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
1821 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
1822 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
1823 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
1824 )
1825 {
1826 /* ADC instance is not a multimode slave instance with multimode regular conversions enabled */
1827 if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != 0UL)
1828 {
1829 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
1830
1831 /* Enable as well injected interruptions in case
1832 HAL_ADCEx_InjectedStart_IT() has not been called beforehand. This
1833 allows to start regular and injected conversions when JAUTO is
1834 set with a single call to HAL_ADC_Start_IT() */
1835 switch (hadc->Init.EOCSelection)
1836 {
1837 case ADC_EOC_SEQ_CONV:
1838 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
1839 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
1840 break;
1841 /* case ADC_EOC_SINGLE_CONV */
1842 default:
1843 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
1844 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
1845 break;
1846 }
1847 }
1848
1849 /* Start ADC group regular conversion */
1850 LL_ADC_REG_StartConversion(hadc->Instance);
1851 }
1852 else
1853 {
1854 /* ADC instance is a multimode slave instance with multimode regular conversions enabled */
1855 SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
1856 /* if Master ADC JAUTO bit is set, Slave injected interruptions
1857 are enabled nevertheless (for same reason as above) */
1858 tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
1859 if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != 0UL)
1860 {
1861 /* First, update Slave State in setting HAL_ADC_STATE_INJ_BUSY bit
1862 and in resetting HAL_ADC_STATE_INJ_EOC bit */
1863 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
1864 /* Next, set Slave injected interruptions */
1865 switch (hadc->Init.EOCSelection)
1866 {
1867 case ADC_EOC_SEQ_CONV:
1868 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
1869 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
1870 break;
1871 /* case ADC_EOC_SINGLE_CONV */
1872 default:
1873 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
1874 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
1875 break;
1876 }
1877 }
1878 }
1879 #else
1880 /* ADC instance is not a multimode slave instance with multimode regular conversions enabled */
1881 if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != 0UL)
1882 {
1883 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY);
1884
1885 /* Enable as well injected interruptions in case
1886 HAL_ADCEx_InjectedStart_IT() has not been called beforehand. This
1887 allows to start regular and injected conversions when JAUTO is
1888 set with a single call to HAL_ADC_Start_IT() */
1889 switch (hadc->Init.EOCSelection)
1890 {
1891 case ADC_EOC_SEQ_CONV:
1892 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
1893 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS);
1894 break;
1895 /* case ADC_EOC_SINGLE_CONV */
1896 default:
1897 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS);
1898 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
1899 break;
1900 }
1901 }
1902
1903 /* Start ADC group regular conversion */
1904 LL_ADC_REG_StartConversion(hadc->Instance);
1905 #endif
1906 }
1907 else
1908 {
1909 __HAL_UNLOCK(hadc);
1910 }
1911
1912 }
1913 else
1914 {
1915 tmp_hal_status = HAL_BUSY;
1916 }
1917
1918 return tmp_hal_status;
1919 }
1920
1921 /**
1922 * @brief Stop ADC conversion of regular group (and injected group in
1923 * case of auto_injection mode), disable interrution of
1924 * end-of-conversion, disable ADC peripheral.
1925 * @param hadc ADC handle
1926 * @retval HAL status.
1927 */
HAL_ADC_Stop_IT(ADC_HandleTypeDef * hadc)1928 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef *hadc)
1929 {
1930 HAL_StatusTypeDef tmp_hal_status;
1931
1932 /* Check the parameters */
1933 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1934
1935 /* Process locked */
1936 __HAL_LOCK(hadc);
1937
1938 /* 1. Stop potential conversion on going, on ADC groups regular and injected */
1939 tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
1940
1941 /* Disable ADC peripheral if conversions are effectively stopped */
1942 if (tmp_hal_status == HAL_OK)
1943 {
1944 /* Disable ADC end of conversion interrupt for regular group */
1945 /* Disable ADC overrun interrupt */
1946 __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR));
1947
1948 /* 2. Disable the ADC peripheral */
1949 tmp_hal_status = ADC_Disable(hadc);
1950
1951 /* Check if ADC is effectively disabled */
1952 if (tmp_hal_status == HAL_OK)
1953 {
1954 /* Set ADC state */
1955 ADC_STATE_CLR_SET(hadc->State,
1956 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
1957 HAL_ADC_STATE_READY);
1958 }
1959 }
1960
1961 __HAL_UNLOCK(hadc);
1962
1963 return tmp_hal_status;
1964 }
1965
1966 /**
1967 * @brief Enable ADC, start conversion of regular group and transfer result through DMA.
1968 * @note Interruptions enabled in this function:
1969 * overrun (if applicable), DMA half transfer, DMA transfer complete.
1970 * Each of these interruptions has its dedicated callback function.
1971 * @note Case of multimode enabled (when multimode feature is available): HAL_ADC_Start_DMA()
1972 * is designed for single-ADC mode only. For multimode, the dedicated
1973 * HAL_ADCEx_MultiModeStart_DMA() function must be used.
1974 * @param hadc ADC handle
1975 * @param pData Destination Buffer address.
1976 * @param Length Number of data to be transferred from ADC peripheral to memory
1977 * @retval HAL status.
1978 */
HAL_ADC_Start_DMA(ADC_HandleTypeDef * hadc,uint32_t * pData,uint32_t Length)1979 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length)
1980 {
1981 HAL_StatusTypeDef tmp_hal_status;
1982 #if defined(ADC_MULTIMODE_SUPPORT)
1983 uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
1984 #endif
1985
1986 /* Check the parameters */
1987 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
1988
1989 /* Perform ADC enable and conversion start if no conversion is on going */
1990 if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
1991 {
1992 /* Process locked */
1993 __HAL_LOCK(hadc);
1994
1995 #if defined(ADC_MULTIMODE_SUPPORT)
1996 /* Ensure that multimode regular conversions are not enabled. */
1997 /* Otherwise, dedicated API HAL_ADCEx_MultiModeStart_DMA() must be used. */
1998 if ((tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
1999 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
2000 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
2001 )
2002 #endif
2003 {
2004 /* Enable the ADC peripheral */
2005 tmp_hal_status = ADC_Enable(hadc);
2006
2007 /* Start conversion if ADC is effectively enabled */
2008 if (tmp_hal_status == HAL_OK)
2009 {
2010 /* Set ADC state */
2011 /* - Clear state bitfield related to regular group conversion results */
2012 /* - Set state bitfield related to regular operation */
2013 ADC_STATE_CLR_SET(hadc->State,
2014 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP,
2015 HAL_ADC_STATE_REG_BUSY);
2016
2017 #if defined(ADC_MULTIMODE_SUPPORT)
2018 /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit
2019 - if ADC instance is master or if multimode feature is not available
2020 - if multimode setting is disabled (ADC instance slave in independent mode) */
2021 if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
2022 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
2023 )
2024 {
2025 CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE);
2026 }
2027 #endif
2028
2029 /* Check if a conversion is on going on ADC group injected */
2030 if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) != 0UL)
2031 {
2032 /* Reset ADC error code fields related to regular conversions only */
2033 CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA));
2034 }
2035 else
2036 {
2037 /* Reset all ADC error code fields */
2038 ADC_CLEAR_ERRORCODE(hadc);
2039 }
2040
2041 /* Set the DMA transfer complete callback */
2042 hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
2043
2044 /* Set the DMA half transfer complete callback */
2045 hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
2046
2047 /* Set the DMA error callback */
2048 hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
2049
2050
2051 /* Manage ADC and DMA start: ADC overrun interruption, DMA start, */
2052 /* ADC start (in case of SW start): */
2053
2054 /* Clear regular group conversion flag and overrun flag */
2055 /* (To ensure of no unknown state from potential previous ADC */
2056 /* operations) */
2057 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR));
2058
2059 /* Unlock before starting ADC conversions: in case of potential */
2060 /* interruption, to let the process to ADC IRQ Handler. */
2061 __HAL_UNLOCK(hadc);
2062
2063 /* With DMA, overrun event is always considered as an error even if
2064 hadc->Init.Overrun is set to ADC_OVR_DATA_OVERWRITTEN. Therefore,
2065 ADC_IT_OVR is enabled. */
2066 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
2067
2068 /* Enable ADC DMA mode*/
2069 LL_ADC_REG_SetDataTransferMode(hadc->Instance, (uint32_t)hadc->Init.ConversionDataManagement);
2070
2071 /* Start the DMA channel */
2072 tmp_hal_status = HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
2073
2074 /* Enable conversion of regular group. */
2075 /* If software start has been selected, conversion starts immediately. */
2076 /* If external trigger has been selected, conversion will start at next */
2077 /* trigger event. */
2078 /* Start ADC group regular conversion */
2079 LL_ADC_REG_StartConversion(hadc->Instance);
2080 }
2081 else
2082 {
2083 __HAL_UNLOCK(hadc);
2084 }
2085
2086 }
2087 #if defined(ADC_MULTIMODE_SUPPORT)
2088 else
2089 {
2090 tmp_hal_status = HAL_ERROR;
2091 __HAL_UNLOCK(hadc);
2092 }
2093 #endif
2094 }
2095 else
2096 {
2097 tmp_hal_status = HAL_BUSY;
2098 }
2099
2100 return tmp_hal_status;
2101 }
2102
2103 /**
2104 * @brief Stop ADC conversion of regular group (and injected group in
2105 * case of auto_injection mode), disable ADC DMA transfer, disable
2106 * ADC peripheral.
2107 * @note: ADC peripheral disable is forcing stop of potential
2108 * conversion on ADC group injected. If ADC group injected is under use, it
2109 * should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
2110 * @note Case of multimode enabled (when multimode feature is available):
2111 * HAL_ADC_Stop_DMA() function is dedicated to single-ADC mode only.
2112 * For multimode, the dedicated HAL_ADCEx_MultiModeStop_DMA() API must be used.
2113 * @param hadc ADC handle
2114 * @retval HAL status.
2115 */
HAL_ADC_Stop_DMA(ADC_HandleTypeDef * hadc)2116 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc)
2117 {
2118 HAL_StatusTypeDef tmp_hal_status;
2119
2120 /* Check the parameters */
2121 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
2122
2123 /* Process locked */
2124 __HAL_LOCK(hadc);
2125
2126 /* 1. Stop potential ADC group regular conversion on going */
2127 tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP);
2128
2129 /* Disable ADC peripheral if conversions are effectively stopped */
2130 if (tmp_hal_status == HAL_OK)
2131 {
2132 /* Disable ADC DMA (ADC DMA configuration of continuous requests is kept) */
2133 MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_DMNGT_0 |ADC_CFGR_DMNGT_1, 0UL);
2134
2135 /* Disable the DMA channel (in case of DMA in circular mode or stop */
2136 /* while DMA transfer is on going) */
2137 if (hadc->DMA_Handle->State == HAL_DMA_STATE_BUSY)
2138 {
2139 tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle);
2140
2141 /* Check if DMA channel effectively disabled */
2142 if (tmp_hal_status != HAL_OK)
2143 {
2144 /* Update ADC state machine to error */
2145 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
2146 }
2147 }
2148
2149 /* Disable ADC overrun interrupt */
2150 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR);
2151
2152 /* 2. Disable the ADC peripheral */
2153 /* Update "tmp_hal_status" only if DMA channel disabling passed, */
2154 /* to keep in memory a potential failing status. */
2155 if (tmp_hal_status == HAL_OK)
2156 {
2157 tmp_hal_status = ADC_Disable(hadc);
2158 }
2159 else
2160 {
2161 (void)ADC_Disable(hadc);
2162 }
2163
2164 /* Check if ADC is effectively disabled */
2165 if (tmp_hal_status == HAL_OK)
2166 {
2167 /* Set ADC state */
2168 ADC_STATE_CLR_SET(hadc->State,
2169 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY,
2170 HAL_ADC_STATE_READY);
2171 }
2172
2173 }
2174
2175 __HAL_UNLOCK(hadc);
2176
2177 return tmp_hal_status;
2178 }
2179
2180 /**
2181 * @brief Get ADC regular group conversion result.
2182 * @note Reading register DR automatically clears ADC flag EOC
2183 * (ADC group regular end of unitary conversion).
2184 * @note This function does not clear ADC flag EOS
2185 * (ADC group regular end of sequence conversion).
2186 * Occurrence of flag EOS rising:
2187 * - If sequencer is composed of 1 rank, flag EOS is equivalent
2188 * to flag EOC.
2189 * - If sequencer is composed of several ranks, during the scan
2190 * sequence flag EOC only is raised, at the end of the scan sequence
2191 * both flags EOC and EOS are raised.
2192 * To clear this flag, either use function:
2193 * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
2194 * model polling: @ref HAL_ADC_PollForConversion()
2195 * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS).
2196 * @param hadc ADC handle
2197 * @retval ADC group regular conversion data
2198 */
HAL_ADC_GetValue(ADC_HandleTypeDef * hadc)2199 uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc)
2200 {
2201 /* Check the parameters */
2202 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
2203
2204 /* Note: EOC flag is not cleared here by software because automatically */
2205 /* cleared by hardware when reading register DR. */
2206
2207 /* Return ADC converted value */
2208 return hadc->Instance->DR;
2209 }
2210
2211 /**
2212 * @brief Handle ADC interrupt request.
2213 * @param hadc ADC handle
2214 * @retval None
2215 */
HAL_ADC_IRQHandler(ADC_HandleTypeDef * hadc)2216 void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc)
2217 {
2218 uint32_t overrun_error = 0UL; /* flag set if overrun occurrence has to be considered as an error */
2219 uint32_t tmp_isr = hadc->Instance->ISR;
2220 uint32_t tmp_ier = hadc->Instance->IER;
2221 uint32_t tmp_adc_inj_is_trigger_source_sw_start;
2222 uint32_t tmp_adc_reg_is_trigger_source_sw_start;
2223 uint32_t tmp_cfgr;
2224 #if defined(ADC_MULTIMODE_SUPPORT)
2225 const ADC_TypeDef *tmpADC_Master;
2226 uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
2227 #endif
2228
2229 /* Check the parameters */
2230 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
2231 assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
2232
2233 /* ========== Check End of Sampling flag for ADC group regular ========== */
2234 if (((tmp_isr & ADC_FLAG_EOSMP) == ADC_FLAG_EOSMP) && ((tmp_ier & ADC_IT_EOSMP) == ADC_IT_EOSMP))
2235 {
2236 /* Update state machine on end of sampling status if not in error state */
2237 if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
2238 {
2239 /* Set ADC state */
2240 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP);
2241 }
2242
2243 /* End Of Sampling callback */
2244 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
2245 hadc->EndOfSamplingCallback(hadc);
2246 #else
2247 HAL_ADCEx_EndOfSamplingCallback(hadc);
2248 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
2249
2250 /* Clear regular group conversion flag */
2251 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP);
2252 }
2253
2254 /* ====== Check ADC group regular end of unitary conversion sequence conversions ===== */
2255 if ((((tmp_isr & ADC_FLAG_EOC) == ADC_FLAG_EOC) && ((tmp_ier & ADC_IT_EOC) == ADC_IT_EOC)) ||
2256 (((tmp_isr & ADC_FLAG_EOS) == ADC_FLAG_EOS) && ((tmp_ier & ADC_IT_EOS) == ADC_IT_EOS)))
2257 {
2258 /* Update state machine on conversion status if not in error state */
2259 if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
2260 {
2261 /* Set ADC state */
2262 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
2263 }
2264
2265 /* Determine whether any further conversion upcoming on group regular */
2266 /* by external trigger, continuous mode or scan sequence on going */
2267 /* to disable interruption. */
2268 if (LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL)
2269 {
2270 /* Get relevant register CFGR in ADC instance of ADC master or slave */
2271 /* in function of multimode state (for devices with multimode */
2272 /* available). */
2273 #if defined(ADC_MULTIMODE_SUPPORT)
2274 if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
2275 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
2276 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_SIMULT)
2277 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_INJ_ALTERN)
2278 )
2279 {
2280 /* check CONT bit directly in handle ADC CFGR register */
2281 tmp_cfgr = READ_REG(hadc->Instance->CFGR);
2282 }
2283 else
2284 {
2285 /* else need to check Master ADC CONT bit */
2286 tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
2287 tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
2288 }
2289 #else
2290 tmp_cfgr = READ_REG(hadc->Instance->CFGR);
2291 #endif
2292
2293 /* Carry on if continuous mode is disabled */
2294 if (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) != ADC_CFGR_CONT)
2295 {
2296 /* If End of Sequence is reached, disable interrupts */
2297 if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS))
2298 {
2299 /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */
2300 /* ADSTART==0 (no conversion on going) */
2301 if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
2302 {
2303 /* Disable ADC end of sequence conversion interrupt */
2304 /* Note: Overrun interrupt was enabled with EOC interrupt in */
2305 /* HAL_Start_IT(), but is not disabled here because can be used */
2306 /* by overrun IRQ process below. */
2307 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS);
2308
2309 /* Set ADC state */
2310 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
2311
2312 if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL)
2313 {
2314 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
2315 }
2316 }
2317 else
2318 {
2319 /* Change ADC state to error state */
2320 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
2321
2322 /* Set ADC error code to ADC peripheral internal error */
2323 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
2324 }
2325 }
2326 }
2327 }
2328
2329 /* Conversion complete callback */
2330 /* Note: Into callback function "HAL_ADC_ConvCpltCallback()", */
2331 /* to determine if conversion has been triggered from EOC or EOS, */
2332 /* possibility to use: */
2333 /* " if ( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) " */
2334 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
2335 hadc->ConvCpltCallback(hadc);
2336 #else
2337 HAL_ADC_ConvCpltCallback(hadc);
2338 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
2339
2340 /* Clear regular group conversion flag */
2341 /* Note: in case of overrun set to ADC_OVR_DATA_PRESERVED, end of */
2342 /* conversion flags clear induces the release of the preserved data.*/
2343 /* Therefore, if the preserved data value is needed, it must be */
2344 /* read preliminarily into HAL_ADC_ConvCpltCallback(). */
2345 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS));
2346 }
2347
2348 /* ====== Check ADC group injected end of unitary conversion sequence conversions ===== */
2349 if ((((tmp_isr & ADC_FLAG_JEOC) == ADC_FLAG_JEOC) && ((tmp_ier & ADC_IT_JEOC) == ADC_IT_JEOC)) ||
2350 (((tmp_isr & ADC_FLAG_JEOS) == ADC_FLAG_JEOS) && ((tmp_ier & ADC_IT_JEOS) == ADC_IT_JEOS)))
2351 {
2352 /* Update state machine on conversion status if not in error state */
2353 if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL)
2354 {
2355 /* Set ADC state */
2356 SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC);
2357 }
2358
2359 /* Retrieve ADC configuration */
2360 tmp_adc_inj_is_trigger_source_sw_start = LL_ADC_INJ_IsTriggerSourceSWStart(hadc->Instance);
2361 tmp_adc_reg_is_trigger_source_sw_start = LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance);
2362 /* Get relevant register CFGR in ADC instance of ADC master or slave */
2363 /* in function of multimode state (for devices with multimode */
2364 /* available). */
2365 #if defined(ADC_MULTIMODE_SUPPORT)
2366 if ((__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
2367 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
2368 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_SIMULT)
2369 || (tmp_multimode_config == LL_ADC_MULTI_DUAL_REG_INTERL)
2370 )
2371 {
2372 tmp_cfgr = READ_REG(hadc->Instance->CFGR);
2373 }
2374 else
2375 {
2376 tmpADC_Master = __LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance);
2377 tmp_cfgr = READ_REG(tmpADC_Master->CFGR);
2378 }
2379 #else
2380 tmp_cfgr = READ_REG(hadc->Instance->CFGR);
2381 #endif
2382
2383 /* Disable interruption if no further conversion upcoming by injected */
2384 /* external trigger or by automatic injected conversion with regular */
2385 /* group having no further conversion upcoming (same conditions as */
2386 /* regular group interruption disabling above), */
2387 /* and if injected scan sequence is completed. */
2388 if (tmp_adc_inj_is_trigger_source_sw_start != 0UL)
2389 {
2390 if ((READ_BIT(tmp_cfgr, ADC_CFGR_JAUTO) == 0UL) ||
2391 ((tmp_adc_reg_is_trigger_source_sw_start != 0UL) &&
2392 (READ_BIT(tmp_cfgr, ADC_CFGR_CONT) == 0UL)))
2393 {
2394 /* If End of Sequence is reached, disable interrupts */
2395 if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS))
2396 {
2397 /* Particular case if injected contexts queue is enabled: */
2398 /* when the last context has been fully processed, JSQR is reset */
2399 /* by the hardware. Even if no injected conversion is planned to come */
2400 /* (queue empty, triggers are ignored), it can start again */
2401 /* immediately after setting a new context (JADSTART is still set). */
2402 /* Therefore, state of HAL ADC injected group is kept to busy. */
2403 if (READ_BIT(tmp_cfgr, ADC_CFGR_JQM) == 0UL)
2404 {
2405 /* Allowed to modify bits ADC_IT_JEOC/ADC_IT_JEOS only if bit */
2406 /* JADSTART==0 (no conversion on going) */
2407 if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) == 0UL)
2408 {
2409 /* Disable ADC end of sequence conversion interrupt */
2410 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS);
2411
2412 /* Set ADC state */
2413 CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY);
2414
2415 if ((hadc->State & HAL_ADC_STATE_REG_BUSY) == 0UL)
2416 {
2417 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
2418 }
2419 }
2420 else
2421 {
2422 /* Update ADC state machine to error */
2423 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
2424
2425 /* Set ADC error code to ADC peripheral internal error */
2426 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
2427 }
2428 }
2429 }
2430 }
2431 }
2432
2433 /* Injected Conversion complete callback */
2434 /* Note: HAL_ADCEx_InjectedConvCpltCallback can resort to
2435 if (__HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOS)) or
2436 if (__HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOC)) to determine whether
2437 interruption has been triggered by end of conversion or end of
2438 sequence. */
2439 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
2440 hadc->InjectedConvCpltCallback(hadc);
2441 #else
2442 HAL_ADCEx_InjectedConvCpltCallback(hadc);
2443 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
2444
2445 /* Clear injected group conversion flag */
2446 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC | ADC_FLAG_JEOS);
2447 }
2448
2449 /* ========== Check Analog watchdog 1 flag ========== */
2450 if (((tmp_isr & ADC_FLAG_AWD1) == ADC_FLAG_AWD1) && ((tmp_ier & ADC_IT_AWD1) == ADC_IT_AWD1))
2451 {
2452 /* Set ADC state */
2453 SET_BIT(hadc->State, HAL_ADC_STATE_AWD1);
2454
2455 /* Level out of window 1 callback */
2456 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
2457 hadc->LevelOutOfWindowCallback(hadc);
2458 #else
2459 HAL_ADC_LevelOutOfWindowCallback(hadc);
2460 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
2461
2462 /* Clear ADC analog watchdog flag */
2463 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1);
2464 }
2465
2466 /* ========== Check analog watchdog 2 flag ========== */
2467 if (((tmp_isr & ADC_FLAG_AWD2) == ADC_FLAG_AWD2) && ((tmp_ier & ADC_IT_AWD2) == ADC_IT_AWD2))
2468 {
2469 /* Set ADC state */
2470 SET_BIT(hadc->State, HAL_ADC_STATE_AWD2);
2471
2472 /* Level out of window 2 callback */
2473 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
2474 hadc->LevelOutOfWindow2Callback(hadc);
2475 #else
2476 HAL_ADCEx_LevelOutOfWindow2Callback(hadc);
2477 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
2478
2479 /* Clear ADC analog watchdog flag */
2480 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2);
2481 }
2482
2483 /* ========== Check analog watchdog 3 flag ========== */
2484 if (((tmp_isr & ADC_FLAG_AWD3) == ADC_FLAG_AWD3) && ((tmp_ier & ADC_IT_AWD3) == ADC_IT_AWD3))
2485 {
2486 /* Set ADC state */
2487 SET_BIT(hadc->State, HAL_ADC_STATE_AWD3);
2488
2489 /* Level out of window 3 callback */
2490 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
2491 hadc->LevelOutOfWindow3Callback(hadc);
2492 #else
2493 HAL_ADCEx_LevelOutOfWindow3Callback(hadc);
2494 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
2495
2496 /* Clear ADC analog watchdog flag */
2497 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3);
2498 }
2499
2500 /* ========== Check Overrun flag ========== */
2501 if (((tmp_isr & ADC_FLAG_OVR) == ADC_FLAG_OVR) && ((tmp_ier & ADC_IT_OVR) == ADC_IT_OVR))
2502 {
2503 /* If overrun is set to overwrite previous data (default setting), */
2504 /* overrun event is not considered as an error. */
2505 /* (cf ref manual "Managing conversions without using the DMA and without */
2506 /* overrun ") */
2507 /* Exception for usage with DMA overrun event always considered as an */
2508 /* error. */
2509 if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED)
2510 {
2511 overrun_error = 1UL;
2512 }
2513 else
2514 {
2515 /* Check DMA configuration */
2516 #if defined(ADC_MULTIMODE_SUPPORT)
2517 if (tmp_multimode_config != LL_ADC_MULTI_INDEPENDENT)
2518 {
2519 /* Multimode (when feature is available) is enabled,
2520 Common Control Register MDMA bits must be checked. */
2521 if (LL_ADC_GetMultiDMATransfer(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) != LL_ADC_MULTI_REG_DMA_EACH_ADC)
2522 {
2523 overrun_error = 1UL;
2524 }
2525 }
2526 else
2527 #endif
2528 {
2529 /* Multimode not set or feature not available or ADC independent */
2530 if ((hadc->Instance->CFGR & ADC_CFGR_DMNGT) != 0UL)
2531 {
2532 overrun_error = 1UL;
2533 }
2534 }
2535 }
2536
2537 if (overrun_error == 1UL)
2538 {
2539 /* Change ADC state to error state */
2540 SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR);
2541
2542 /* Set ADC error code to overrun */
2543 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR);
2544
2545 /* Error callback */
2546 /* Note: In case of overrun, ADC conversion data is preserved until */
2547 /* flag OVR is reset. */
2548 /* Therefore, old ADC conversion data can be retrieved in */
2549 /* function "HAL_ADC_ErrorCallback()". */
2550 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
2551 hadc->ErrorCallback(hadc);
2552 #else
2553 HAL_ADC_ErrorCallback(hadc);
2554 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
2555 }
2556
2557 /* Clear ADC overrun flag */
2558 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
2559 }
2560
2561 /* ========== Check Injected context queue overflow flag ========== */
2562 if (((tmp_isr & ADC_FLAG_JQOVF) == ADC_FLAG_JQOVF) && ((tmp_ier & ADC_IT_JQOVF) == ADC_IT_JQOVF))
2563 {
2564 /* Change ADC state to overrun state */
2565 SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF);
2566
2567 /* Set ADC error code to Injected context queue overflow */
2568 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF);
2569
2570 /* Clear the Injected context queue overflow flag */
2571 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF);
2572
2573 /* Injected context queue overflow callback */
2574 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
2575 hadc->InjectedQueueOverflowCallback(hadc);
2576 #else
2577 HAL_ADCEx_InjectedQueueOverflowCallback(hadc);
2578 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
2579 }
2580
2581 }
2582
2583 /**
2584 * @brief Conversion complete callback in non-blocking mode.
2585 * @param hadc ADC handle
2586 * @retval None
2587 */
HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef * hadc)2588 __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef *hadc)
2589 {
2590 /* Prevent unused argument(s) compilation warning */
2591 UNUSED(hadc);
2592
2593 /* NOTE : This function should not be modified. When the callback is needed,
2594 function HAL_ADC_ConvCpltCallback must be implemented in the user file.
2595 */
2596 }
2597
2598 /**
2599 * @brief Conversion DMA half-transfer callback in non-blocking mode.
2600 * @param hadc ADC handle
2601 * @retval None
2602 */
HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef * hadc)2603 __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef *hadc)
2604 {
2605 /* Prevent unused argument(s) compilation warning */
2606 UNUSED(hadc);
2607
2608 /* NOTE : This function should not be modified. When the callback is needed,
2609 function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file.
2610 */
2611 }
2612
2613 /**
2614 * @brief Analog watchdog 1 callback in non-blocking mode.
2615 * @param hadc ADC handle
2616 * @retval None
2617 */
HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef * hadc)2618 __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef *hadc)
2619 {
2620 /* Prevent unused argument(s) compilation warning */
2621 UNUSED(hadc);
2622
2623 /* NOTE : This function should not be modified. When the callback is needed,
2624 function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file.
2625 */
2626 }
2627
2628 /**
2629 * @brief ADC error callback in non-blocking mode
2630 * (ADC conversion with interruption or transfer by DMA).
2631 * @note In case of error due to overrun when using ADC with DMA transfer
2632 * (HAL ADC handle parameter "ErrorCode" to state "HAL_ADC_ERROR_OVR"):
2633 * - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()".
2634 * - If needed, restart a new ADC conversion using function
2635 * "HAL_ADC_Start_DMA()"
2636 * (this function is also clearing overrun flag)
2637 * @param hadc ADC handle
2638 * @retval None
2639 */
HAL_ADC_ErrorCallback(ADC_HandleTypeDef * hadc)2640 __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
2641 {
2642 /* Prevent unused argument(s) compilation warning */
2643 UNUSED(hadc);
2644
2645 /* NOTE : This function should not be modified. When the callback is needed,
2646 function HAL_ADC_ErrorCallback must be implemented in the user file.
2647 */
2648 }
2649
2650 /**
2651 * @}
2652 */
2653
2654 /** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
2655 * @brief Peripheral Control functions
2656 *
2657 @verbatim
2658 ===============================================================================
2659 ##### Peripheral Control functions #####
2660 ===============================================================================
2661 [..] This section provides functions allowing to:
2662 (+) Configure channels on regular group
2663 (+) Configure the analog watchdog
2664
2665 @endverbatim
2666 * @{
2667 */
2668
2669 /**
2670 * @brief Configure a channel to be assigned to ADC group regular.
2671 * @note In case of usage of internal measurement channels:
2672 * Vbat/VrefInt/TempSensor/VddCore.
2673 * These internal paths can be disabled using function
2674 * HAL_ADC_DeInit().
2675 * @note Possibility to update parameters on the fly:
2676 * This function initializes channel into ADC group regular,
2677 * following calls to this function can be used to reconfigure
2678 * some parameters of structure "ADC_ChannelConfTypeDef" on the fly,
2679 * without resetting the ADC.
2680 * The setting of these parameters is conditioned to ADC state:
2681 * Refer to comments of structure "ADC_ChannelConfTypeDef".
2682 * @param hadc ADC handle
2683 * @param pConfig Structure of ADC channel assigned to ADC group regular.
2684 * @retval HAL status
2685 */
HAL_ADC_ConfigChannel(ADC_HandleTypeDef * hadc,ADC_ChannelConfTypeDef * pConfig)2686 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *pConfig)
2687 {
2688 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
2689 uint32_t tmpOffsetShifted;
2690 uint32_t tmp_config_internal_channel;
2691 __IO uint32_t wait_loop_index = 0UL;
2692 uint32_t tmp_adc_is_conversion_on_going_regular;
2693 uint32_t tmp_adc_is_conversion_on_going_injected;
2694
2695 /* Check the parameters */
2696 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
2697 assert_param(IS_ADC_REGULAR_RANK(pConfig->Rank));
2698 assert_param(IS_ADC_SAMPLE_TIME(pConfig->SamplingTime));
2699 assert_param(IS_ADC_SINGLE_DIFFERENTIAL(pConfig->SingleDiff));
2700 assert_param(IS_ADC_OFFSET_NUMBER(pConfig->OffsetNumber));
2701 /* Check offset range according to oversampling setting */
2702 if (hadc->Init.OversamplingMode == ENABLE)
2703 {
2704 assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), pConfig->Offset/(hadc->Init.Oversampling.Ratio+1U)));
2705 }
2706 else
2707 {
2708 assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), pConfig->Offset));
2709 }
2710
2711 /* if ROVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is
2712 ignored (considered as reset) */
2713 assert_param(!((pConfig->OffsetNumber != ADC_OFFSET_NONE) && (hadc->Init.OversamplingMode == ENABLE)));
2714
2715 /* Verification of channel number */
2716 if (pConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED)
2717 {
2718 assert_param(IS_ADC_CHANNEL(pConfig->Channel));
2719 }
2720 else
2721 {
2722 if (hadc->Instance == ADC1)
2723 {
2724 assert_param(IS_ADC1_DIFF_CHANNEL(pConfig->Channel));
2725 }
2726 if (hadc->Instance == ADC2)
2727 {
2728 assert_param(IS_ADC2_DIFF_CHANNEL(pConfig->Channel));
2729 }
2730 }
2731
2732 /* Process locked */
2733 __HAL_LOCK(hadc);
2734
2735 /* Parameters update conditioned to ADC state: */
2736 /* Parameters that can be updated when ADC is disabled or enabled without */
2737 /* conversion on going on regular group: */
2738 /* - Channel number */
2739 /* - Channel rank */
2740 if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) == 0UL)
2741 {
2742 /* ADC channels preselection */
2743 hadc->Instance->PCSEL |= (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)pConfig->Channel) & 0x1FUL));
2744
2745 /* Set ADC group regular sequence: channel on the selected scan sequence rank */
2746 LL_ADC_REG_SetSequencerRanks(hadc->Instance, pConfig->Rank, pConfig->Channel);
2747
2748 /* Parameters update conditioned to ADC state: */
2749 /* Parameters that can be updated when ADC is disabled or enabled without */
2750 /* conversion on going on regular group: */
2751 /* - Channel sampling time */
2752 /* - Channel offset */
2753 tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
2754 tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
2755 if ((tmp_adc_is_conversion_on_going_regular == 0UL)
2756 && (tmp_adc_is_conversion_on_going_injected == 0UL)
2757 )
2758 {
2759 /* Set sampling time of the selected ADC channel */
2760 LL_ADC_SetChannelSamplingTime(hadc->Instance, pConfig->Channel, pConfig->SamplingTime);
2761
2762 /* Configure the offset: offset enable/disable, channel, offset value */
2763
2764 /* Shift the offset with respect to the selected ADC resolution. */
2765 /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */
2766 tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, (uint32_t)pConfig->Offset);
2767
2768 if (pConfig->OffsetNumber != ADC_OFFSET_NONE)
2769 {
2770 /* Set ADC selected offset number */
2771 LL_ADC_SetOffset(hadc->Instance, pConfig->OffsetNumber, pConfig->Channel, tmpOffsetShifted);
2772
2773 assert_param(IS_FUNCTIONAL_STATE(pConfig->OffsetSignedSaturation));
2774 /* Set ADC selected offset signed saturation */
2775 LL_ADC_SetOffsetSignedSaturation(hadc->Instance, pConfig->OffsetNumber, (pConfig->OffsetSignedSaturation == ENABLE) ? LL_ADC_OFFSET_SIGNED_SATURATION_ENABLE : LL_ADC_OFFSET_SIGNED_SATURATION_DISABLE);
2776
2777 assert_param(IS_FUNCTIONAL_STATE(pConfig->OffsetRightShift));
2778 /* Set ADC selected offset right shift */
2779 LL_ADC_SetDataRightShift(hadc->Instance, pConfig->OffsetNumber, (pConfig->OffsetRightShift == ENABLE) ? LL_ADC_OFFSET_RSHIFT_ENABLE : LL_ADC_OFFSET_RSHIFT_DISABLE);
2780
2781 }
2782 else
2783 {
2784 /* Scan OFR1, OFR2, OFR3, OFR4 to check if the selected channel is enabled.
2785 If this is the case, offset OFRx is disabled since
2786 pConfig->OffsetNumber = ADC_OFFSET_NONE. */
2787 if (((hadc->Instance->OFR1) & ADC_OFR1_OFFSET1_CH) == ADC_OFR_CHANNEL(pConfig->Channel))
2788 {
2789 CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_SSATE);
2790 }
2791 if (((hadc->Instance->OFR2) & ADC_OFR2_OFFSET2_CH) == ADC_OFR_CHANNEL(pConfig->Channel))
2792 {
2793 CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_SSATE);
2794 }
2795 if (((hadc->Instance->OFR3) & ADC_OFR3_OFFSET3_CH) == ADC_OFR_CHANNEL(pConfig->Channel))
2796 {
2797 CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_SSATE);
2798 }
2799 if (((hadc->Instance->OFR4) & ADC_OFR4_OFFSET4_CH) == ADC_OFR_CHANNEL(pConfig->Channel))
2800 {
2801 CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_SSATE);
2802 }
2803 }
2804 }
2805
2806 /* Parameters update conditioned to ADC state: */
2807 /* Parameters that can be updated only when ADC is disabled: */
2808 /* - Single or differential mode */
2809 /* - Internal measurement channels: Vbat/VrefInt/TempSensor/VddCore */
2810 if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
2811 {
2812 /* Set mode single-ended or differential input of the selected ADC channel */
2813 LL_ADC_SetChannelSingleDiff(hadc->Instance, pConfig->Channel, pConfig->SingleDiff);
2814
2815 /* Configuration of differential mode */
2816 if (pConfig->SingleDiff == ADC_DIFFERENTIAL_ENDED)
2817 {
2818 /* Set sampling time of the selected ADC channel */
2819 /* Note: ADC channel number masked with value "0x1F" to ensure shift value within 32 bits range */
2820 LL_ADC_SetChannelSamplingTime(hadc->Instance,
2821 (uint32_t)(__LL_ADC_DECIMAL_NB_TO_CHANNEL((__LL_ADC_CHANNEL_TO_DECIMAL_NB((uint32_t)pConfig->Channel) + 1UL) & 0x1FUL)),
2822 pConfig->SamplingTime);
2823 }
2824
2825 /* Management of internal measurement channels: Vbat/VrefInt/TempSensor/VddCore. */
2826 /* If internal channel selected, enable dedicated internal buffers and */
2827 /* paths. */
2828 /* Note: these internal measurement paths can be disabled using */
2829 /* HAL_ADC_DeInit(). */
2830
2831 if (__LL_ADC_IS_CHANNEL_INTERNAL(pConfig->Channel))
2832 {
2833 /* Configuration of common ADC parameters */
2834
2835 tmp_config_internal_channel = LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
2836
2837 /* Software is allowed to change common parameters only when all ADCs */
2838 /* of the common group are disabled. */
2839 if (__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) == 0UL)
2840 {
2841 /* If the requested internal measurement path has already been enabled, */
2842 /* bypass the configuration processing. */
2843 if ((pConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
2844 && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0UL))
2845 {
2846 if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc))
2847 {
2848 LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_TEMPSENSOR | tmp_config_internal_channel);
2849
2850 /* Delay for temperature sensor stabilization time */
2851 /* Wait loop initialization and execution */
2852 /* Note: Variable divided by 2 to compensate partially */
2853 /* CPU processing cycles, scaling in us split to not */
2854 /* exceed 32 bits register capacity and handle low frequency. */
2855 wait_loop_index = ((LL_ADC_DELAY_TEMPSENSOR_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL));
2856 while(wait_loop_index != 0UL)
2857 {
2858 wait_loop_index--;
2859 }
2860 }
2861 }
2862 else if ((pConfig->Channel == ADC_CHANNEL_VBAT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VBAT) == 0UL))
2863 {
2864 if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc))
2865 {
2866 LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VBAT | tmp_config_internal_channel);
2867 }
2868 }
2869 else if ((pConfig->Channel == ADC_CHANNEL_VREFINT) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VREFINT) == 0UL))
2870 {
2871 if (ADC_VREFINT_INSTANCE(hadc))
2872 {
2873 LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VREFINT | tmp_config_internal_channel);
2874 }
2875 }
2876 else if ((pConfig->Channel == ADC_CHANNEL_VCORE) && ((tmp_config_internal_channel & LL_ADC_PATH_INTERNAL_VDDCORE) == 0UL))
2877 {
2878 if (ADC_VDDCORE_INSTANCE(hadc))
2879 {
2880 LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VDDCORE | tmp_config_internal_channel);
2881 }
2882 }
2883 else
2884 {
2885 /* nothing to do */
2886 }
2887 }
2888 /* If the requested internal measurement path has already been */
2889 /* enabled and other ADC of the common group are enabled, internal */
2890 /* measurement paths cannot be enabled. */
2891 else
2892 {
2893 /* Update ADC state machine to error */
2894 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
2895
2896 tmp_hal_status = HAL_ERROR;
2897 }
2898 }
2899 }
2900 }
2901
2902 /* If a conversion is on going on regular group, no update on regular */
2903 /* channel could be done on neither of the channel configuration structure */
2904 /* parameters. */
2905 else
2906 {
2907 /* Update ADC state machine to error */
2908 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
2909
2910 tmp_hal_status = HAL_ERROR;
2911 }
2912
2913 __HAL_UNLOCK(hadc);
2914
2915 return tmp_hal_status;
2916 }
2917
2918 /**
2919 * @brief Configure the analog watchdog.
2920 * @note Possibility to update parameters on the fly:
2921 * This function initializes the selected analog watchdog, successive
2922 * calls to this function can be used to reconfigure some parameters
2923 * of structure "ADC_AnalogWDGConfTypeDef" on the fly, without resetting
2924 * the ADC.
2925 * The setting of these parameters is conditioned to ADC state.
2926 * For parameters constraints, see comments of structure
2927 * "ADC_AnalogWDGConfTypeDef".
2928 * @note On this STM32 series, analog watchdog thresholds cannot be modified
2929 * while ADC conversion is on going.
2930 * @param hadc ADC handle
2931 * @param pAnalogWDGConfig Structure of ADC analog watchdog configuration
2932 * @retval HAL status
2933 */
HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef * hadc,ADC_AnalogWDGConfTypeDef * pAnalogWDGConfig)2934 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *pAnalogWDGConfig)
2935 {
2936 HAL_StatusTypeDef tmp_hal_status = HAL_OK;
2937 uint32_t tmp_awd_high_threshold_shifted;
2938 uint32_t tmp_awd_low_threshold_shifted;
2939 uint32_t tmp_adc_is_conversion_on_going_regular;
2940 uint32_t tmp_adc_is_conversion_on_going_injected;
2941
2942 /* Check the parameters */
2943 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
2944 assert_param(IS_ADC_ANALOG_WATCHDOG_NUMBER(pAnalogWDGConfig->WatchdogNumber));
2945 assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(pAnalogWDGConfig->WatchdogMode));
2946 assert_param(IS_FUNCTIONAL_STATE(pAnalogWDGConfig->ITMode));
2947
2948 if ((pAnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) ||
2949 (pAnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC) ||
2950 (pAnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC))
2951 {
2952 assert_param(IS_ADC_CHANNEL(pAnalogWDGConfig->Channel));
2953 }
2954
2955 /* Verify thresholds range */
2956 if (hadc->Init.OversamplingMode == ENABLE)
2957 {
2958 /* Case of oversampling enabled: thresholds are compared to oversampling
2959 intermediate computation (after ratio, before shift application) */
2960 assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), pAnalogWDGConfig->HighThreshold / (hadc->Init.Oversampling.Ratio + 1UL)));
2961 assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), pAnalogWDGConfig->LowThreshold / (hadc->Init.Oversampling.Ratio + 1UL)));
2962 }
2963 else
2964 {
2965 /* Verify if thresholds are within the selected ADC resolution */
2966 assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), pAnalogWDGConfig->HighThreshold));
2967 assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), pAnalogWDGConfig->LowThreshold));
2968 }
2969
2970 /* Process locked */
2971 __HAL_LOCK(hadc);
2972
2973 /* Parameters update conditioned to ADC state: */
2974 /* Parameters that can be updated when ADC is disabled or enabled without */
2975 /* conversion on going on ADC groups regular and injected: */
2976 /* - Analog watchdog channels */
2977 /* - Analog watchdog thresholds */
2978 tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
2979 tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
2980 if ((tmp_adc_is_conversion_on_going_regular == 0UL)
2981 && (tmp_adc_is_conversion_on_going_injected == 0UL)
2982 )
2983 {
2984 /* Analog watchdog configuration */
2985 if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1)
2986 {
2987 /* Configuration of analog watchdog: */
2988 /* - Set the analog watchdog enable mode: one or overall group of */
2989 /* channels, on groups regular and-or injected. */
2990 switch (pAnalogWDGConfig->WatchdogMode)
2991 {
2992 case ADC_ANALOGWATCHDOG_SINGLE_REG:
2993 LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(pAnalogWDGConfig->Channel,
2994 LL_ADC_GROUP_REGULAR));
2995 break;
2996
2997 case ADC_ANALOGWATCHDOG_SINGLE_INJEC:
2998 LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(pAnalogWDGConfig->Channel,
2999 LL_ADC_GROUP_INJECTED));
3000 break;
3001
3002 case ADC_ANALOGWATCHDOG_SINGLE_REGINJEC:
3003 LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(pAnalogWDGConfig->Channel,
3004 LL_ADC_GROUP_REGULAR_INJECTED));
3005 break;
3006
3007 case ADC_ANALOGWATCHDOG_ALL_REG:
3008 LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_REG);
3009 break;
3010
3011 case ADC_ANALOGWATCHDOG_ALL_INJEC:
3012 LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_INJ);
3013 break;
3014
3015 case ADC_ANALOGWATCHDOG_ALL_REGINJEC:
3016 LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_REG_INJ);
3017 break;
3018
3019 default: /* ADC_ANALOGWATCHDOG_NONE */
3020 LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_DISABLE);
3021 break;
3022 }
3023
3024 /* Shift the offset in function of the selected ADC resolution: */
3025 /* Thresholds have to be left-aligned on bit 11, the LSB (right bits) */
3026 /* are set to 0 */
3027 tmp_awd_high_threshold_shifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, pAnalogWDGConfig->HighThreshold);
3028 tmp_awd_low_threshold_shifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, pAnalogWDGConfig->LowThreshold);
3029
3030 /* Set the high and low thresholds */
3031 MODIFY_REG(hadc->Instance->LTR1, ADC_LTR1_LT1 , tmp_awd_low_threshold_shifted);
3032 MODIFY_REG(hadc->Instance->HTR1, ADC_HTR1_HT1 , tmp_awd_high_threshold_shifted);
3033
3034 /* Update state, clear previous result related to AWD1 */
3035 CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD1);
3036
3037 /* Clear flag ADC analog watchdog */
3038 /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */
3039 /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */
3040 /* (in case left enabled by previous ADC operations). */
3041 LL_ADC_ClearFlag_AWD1(hadc->Instance);
3042
3043 /* Configure ADC analog watchdog interrupt */
3044 if (pAnalogWDGConfig->ITMode == ENABLE)
3045 {
3046 LL_ADC_EnableIT_AWD1(hadc->Instance);
3047 }
3048 else
3049 {
3050 LL_ADC_DisableIT_AWD1(hadc->Instance);
3051 }
3052 }
3053 /* Case of ADC_ANALOGWATCHDOG_2 or ADC_ANALOGWATCHDOG_3 */
3054 else
3055 {
3056 switch (pAnalogWDGConfig->WatchdogMode)
3057 {
3058 case ADC_ANALOGWATCHDOG_SINGLE_REG:
3059 case ADC_ANALOGWATCHDOG_SINGLE_INJEC:
3060 case ADC_ANALOGWATCHDOG_SINGLE_REGINJEC:
3061 /* Update AWD by bitfield to keep the possibility to monitor */
3062 /* several channels by successive calls of this function. */
3063 if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
3064 {
3065 SET_BIT(hadc->Instance->AWD2CR, (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(pAnalogWDGConfig->Channel) & 0x1FUL)));
3066 }
3067 else
3068 {
3069 SET_BIT(hadc->Instance->AWD3CR, (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(pAnalogWDGConfig->Channel) & 0x1FUL)));
3070 }
3071 break;
3072
3073 case ADC_ANALOGWATCHDOG_ALL_REG:
3074 case ADC_ANALOGWATCHDOG_ALL_INJEC:
3075 case ADC_ANALOGWATCHDOG_ALL_REGINJEC:
3076 /* Update AWD by bitfield to keep the possibility to monitor */
3077 /* several channels by successive calls of this function. */
3078 if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
3079 {
3080 SET_BIT(hadc->Instance->AWD2CR, (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(pAnalogWDGConfig->Channel) & 0x1FUL)));
3081 }
3082 else
3083 {
3084 SET_BIT(hadc->Instance->AWD3CR, (1UL << (__LL_ADC_CHANNEL_TO_DECIMAL_NB(pAnalogWDGConfig->Channel) & 0x1FUL)));
3085 }
3086 break;
3087
3088 default: /* ADC_ANALOGWATCHDOG_NONE */
3089 LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, pAnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_DISABLE);
3090 break;
3091 }
3092
3093 /* Shift the thresholds in function of the selected ADC resolution */
3094 /* have to be left-aligned on bit 15, the LSB (right bits) are set to 0 */
3095 tmp_awd_high_threshold_shifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, pAnalogWDGConfig->HighThreshold);
3096 tmp_awd_low_threshold_shifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, pAnalogWDGConfig->LowThreshold);
3097
3098 if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
3099 {
3100 /* Set ADC analog watchdog thresholds value of both thresholds high and low */
3101 MODIFY_REG(hadc->Instance->LTR2, ADC_LTR2_LT2 , tmp_awd_low_threshold_shifted);
3102 MODIFY_REG(hadc->Instance->HTR2, ADC_HTR2_HT2 , tmp_awd_high_threshold_shifted);
3103 }
3104 else
3105 {
3106 /* Set ADC analog watchdog thresholds value of both thresholds high and low */
3107 MODIFY_REG(hadc->Instance->LTR3, ADC_LTR3_LT3 , tmp_awd_low_threshold_shifted);
3108 MODIFY_REG(hadc->Instance->HTR3, ADC_HTR3_HT3 , tmp_awd_high_threshold_shifted);
3109 }
3110
3111 if (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2)
3112 {
3113 /* Update state, clear previous result related to AWD2 */
3114 CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD2);
3115
3116 /* Clear flag ADC analog watchdog */
3117 /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */
3118 /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */
3119 /* (in case left enabled by previous ADC operations). */
3120 LL_ADC_ClearFlag_AWD2(hadc->Instance);
3121
3122 /* Configure ADC analog watchdog interrupt */
3123 if (pAnalogWDGConfig->ITMode == ENABLE)
3124 {
3125 LL_ADC_EnableIT_AWD2(hadc->Instance);
3126 }
3127 else
3128 {
3129 LL_ADC_DisableIT_AWD2(hadc->Instance);
3130 }
3131 }
3132 /* (pAnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_3) */
3133 else
3134 {
3135 /* Update state, clear previous result related to AWD3 */
3136 CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD3);
3137
3138 /* Clear flag ADC analog watchdog */
3139 /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */
3140 /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */
3141 /* (in case left enabled by previous ADC operations). */
3142 LL_ADC_ClearFlag_AWD3(hadc->Instance);
3143
3144 /* Configure ADC analog watchdog interrupt */
3145 if (pAnalogWDGConfig->ITMode == ENABLE)
3146 {
3147 LL_ADC_EnableIT_AWD3(hadc->Instance);
3148 }
3149 else
3150 {
3151 LL_ADC_DisableIT_AWD3(hadc->Instance);
3152 }
3153 }
3154 }
3155
3156 }
3157 /* If a conversion is on going on ADC group regular or injected, no update */
3158 /* could be done on neither of the AWD configuration structure parameters. */
3159 else
3160 {
3161 /* Update ADC state machine to error */
3162 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG);
3163
3164 tmp_hal_status = HAL_ERROR;
3165 }
3166 __HAL_UNLOCK(hadc);
3167
3168 return tmp_hal_status;
3169 }
3170
3171
3172 /**
3173 * @}
3174 */
3175
3176 /** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions
3177 * @brief ADC Peripheral State functions
3178 *
3179 @verbatim
3180 ===============================================================================
3181 ##### Peripheral state and errors functions #####
3182 ===============================================================================
3183 [..]
3184 This subsection provides functions to get in run-time the status of the
3185 peripheral.
3186 (+) Check the ADC state
3187 (+) Check the ADC error code
3188
3189 @endverbatim
3190 * @{
3191 */
3192
3193 /**
3194 * @brief Return the ADC handle state.
3195 * @note ADC state machine is managed by bitfields, ADC status must be
3196 * compared with states bits.
3197 * For example:
3198 * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_REG_BUSY) != 0UL) "
3199 * " if ((HAL_ADC_GetState(hadc1) & HAL_ADC_STATE_AWD1) != 0UL) "
3200 * @param hadc ADC handle
3201 * @retval ADC handle state (bitfield on 32 bits)
3202 */
HAL_ADC_GetState(ADC_HandleTypeDef * hadc)3203 uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc)
3204 {
3205 /* Check the parameters */
3206 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
3207
3208 /* Return ADC handle state */
3209 return hadc->State;
3210 }
3211
3212 /**
3213 * @brief Return the ADC error code.
3214 * @param hadc ADC handle
3215 * @retval ADC error code (bitfield on 32 bits)
3216 */
HAL_ADC_GetError(ADC_HandleTypeDef * hadc)3217 uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
3218 {
3219 /* Check the parameters */
3220 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
3221
3222 return hadc->ErrorCode;
3223 }
3224
3225 /**
3226 * @}
3227 */
3228
3229 /**
3230 * @}
3231 */
3232
3233 /** @defgroup ADC_Private_Functions ADC Private Functions
3234 * @{
3235 */
3236
3237 /**
3238 * @brief Stop ADC conversion.
3239 * @param hadc ADC handle
3240 * @param ConversionGroup ADC group regular and/or injected.
3241 * This parameter can be one of the following values:
3242 * @arg @ref ADC_REGULAR_GROUP ADC regular conversion type.
3243 * @arg @ref ADC_INJECTED_GROUP ADC injected conversion type.
3244 * @arg @ref ADC_REGULAR_INJECTED_GROUP ADC regular and injected conversion type.
3245 * @retval HAL status.
3246 */
ADC_ConversionStop(ADC_HandleTypeDef * hadc,uint32_t ConversionGroup)3247 HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef *hadc, uint32_t ConversionGroup)
3248 {
3249 uint32_t tickstart;
3250 uint32_t Conversion_Timeout_CPU_cycles = 0UL;
3251 uint32_t conversion_group_reassigned = ConversionGroup;
3252 uint32_t tmp_ADC_CR_ADSTART_JADSTART;
3253 uint32_t tmp_adc_is_conversion_on_going_regular;
3254 uint32_t tmp_adc_is_conversion_on_going_injected;
3255
3256 /* Check the parameters */
3257 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
3258 assert_param(IS_ADC_CONVERSION_GROUP(ConversionGroup));
3259
3260 /* Verification if ADC is not already stopped (on regular and injected */
3261 /* groups) to bypass this function if not needed. */
3262 tmp_adc_is_conversion_on_going_regular = LL_ADC_REG_IsConversionOngoing(hadc->Instance);
3263 tmp_adc_is_conversion_on_going_injected = LL_ADC_INJ_IsConversionOngoing(hadc->Instance);
3264 if ((tmp_adc_is_conversion_on_going_regular != 0UL)
3265 || (tmp_adc_is_conversion_on_going_injected != 0UL)
3266 )
3267 {
3268 /* Particular case of continuous auto-injection mode combined with */
3269 /* auto-delay mode. */
3270 /* In auto-injection mode, regular group stop ADC_CR_ADSTP is used (not */
3271 /* injected group stop ADC_CR_JADSTP). */
3272 /* Procedure to be followed: Wait until JEOS=1, clear JEOS, set ADSTP=1 */
3273 /* (see reference manual). */
3274 if (((hadc->Instance->CFGR & ADC_CFGR_JAUTO) != 0UL)
3275 && (hadc->Init.ContinuousConvMode == ENABLE)
3276 && (hadc->Init.LowPowerAutoWait == ENABLE)
3277 )
3278 {
3279 /* Use stop of regular group */
3280 conversion_group_reassigned = ADC_REGULAR_GROUP;
3281
3282 /* Wait until JEOS=1 (maximum Timeout: 4 injected conversions) */
3283 while (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS) == 0UL)
3284 {
3285 if (Conversion_Timeout_CPU_cycles >= (ADC_CONVERSION_TIME_MAX_CPU_CYCLES * 4UL))
3286 {
3287 /* Update ADC state machine to error */
3288 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
3289
3290 /* Set ADC error code to ADC peripheral internal error */
3291 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
3292
3293 return HAL_ERROR;
3294 }
3295 Conversion_Timeout_CPU_cycles ++;
3296 }
3297
3298 /* Clear JEOS */
3299 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOS);
3300 }
3301
3302 /* Stop potential conversion on going on ADC group regular */
3303 if (conversion_group_reassigned != ADC_INJECTED_GROUP)
3304 {
3305 /* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 */
3306 if (LL_ADC_REG_IsConversionOngoing(hadc->Instance) != 0UL)
3307 {
3308 if (LL_ADC_IsDisableOngoing(hadc->Instance) == 0UL)
3309 {
3310 /* Stop ADC group regular conversion */
3311 LL_ADC_REG_StopConversion(hadc->Instance);
3312 }
3313 }
3314 }
3315
3316 /* Stop potential conversion on going on ADC group injected */
3317 if (conversion_group_reassigned != ADC_REGULAR_GROUP)
3318 {
3319 /* Software is allowed to set JADSTP only when JADSTART=1 and ADDIS=0 */
3320 if (LL_ADC_INJ_IsConversionOngoing(hadc->Instance) != 0UL)
3321 {
3322 if (LL_ADC_IsDisableOngoing(hadc->Instance) == 0UL)
3323 {
3324 /* Stop ADC group injected conversion */
3325 LL_ADC_INJ_StopConversion(hadc->Instance);
3326 }
3327 }
3328 }
3329
3330 /* Selection of start and stop bits with respect to the regular or injected group */
3331 switch (conversion_group_reassigned)
3332 {
3333 case ADC_REGULAR_INJECTED_GROUP:
3334 tmp_ADC_CR_ADSTART_JADSTART = (ADC_CR_ADSTART | ADC_CR_JADSTART);
3335 break;
3336 case ADC_INJECTED_GROUP:
3337 tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_JADSTART;
3338 break;
3339 /* Case ADC_REGULAR_GROUP only*/
3340 default:
3341 tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_ADSTART;
3342 break;
3343 }
3344
3345 /* Wait for conversion effectively stopped */
3346 tickstart = HAL_GetTick();
3347
3348 while ((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != 0UL)
3349 {
3350 if ((HAL_GetTick() - tickstart) > ADC_STOP_CONVERSION_TIMEOUT)
3351 {
3352 /* New check to avoid false timeout detection in case of preemption */
3353 if ((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != 0UL)
3354 {
3355 /* Update ADC state machine to error */
3356 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
3357
3358 /* Set ADC error code to ADC peripheral internal error */
3359 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
3360
3361 return HAL_ERROR;
3362 }
3363 }
3364 }
3365 }
3366
3367 /* Return HAL status */
3368 return HAL_OK;
3369 }
3370
3371 /**
3372 * @brief Enable the selected ADC.
3373 * @note Prerequisite condition to use this function: ADC must be disabled
3374 * and voltage regulator must be enabled (done into HAL_ADC_Init()).
3375 * @param hadc ADC handle
3376 * @retval HAL status.
3377 */
ADC_Enable(ADC_HandleTypeDef * hadc)3378 HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef *hadc)
3379 {
3380 uint32_t tickstart;
3381
3382 /* ADC enable and wait for ADC ready (in case of ADC is disabled or */
3383 /* enabling phase not yet completed: flag ADC ready not yet set). */
3384 /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */
3385 /* causes: ADC clock not running, ...). */
3386 if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
3387 {
3388 /* Check if conditions to enable the ADC are fulfilled */
3389 if ((hadc->Instance->CR & (ADC_CR_ADCAL | ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART
3390 | ADC_CR_ADDIS | ADC_CR_ADEN)) != 0UL)
3391 {
3392 /* Update ADC state machine to error */
3393 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
3394
3395 /* Set ADC error code to ADC peripheral internal error */
3396 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
3397
3398 return HAL_ERROR;
3399 }
3400
3401 /* Enable the ADC peripheral */
3402 LL_ADC_Enable(hadc->Instance);
3403
3404 /* Wait for ADC effectively enabled */
3405 tickstart = HAL_GetTick();
3406
3407 #if defined(ADC_MULTIMODE_SUPPORT)
3408 /* Poll for ADC ready flag raised except case of multimode enabled
3409 and ADC slave selected. */
3410 uint32_t tmp_multimode_config = LL_ADC_GetMultimode(__LL_ADC_COMMON_INSTANCE(hadc->Instance));
3411 if ( (__LL_ADC_MULTI_INSTANCE_MASTER(hadc->Instance) == hadc->Instance)
3412 || (tmp_multimode_config == LL_ADC_MULTI_INDEPENDENT)
3413 )
3414 {
3415 while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL)
3416 {
3417 /* If ADEN bit is set less than 4 ADC clock cycles after the ADCAL bit
3418 has been cleared (after a calibration), ADEN bit is reset by the
3419 calibration logic.
3420 The workaround is to continue setting ADEN until ADRDY is becomes 1.
3421 Additionally, ADC_ENABLE_TIMEOUT is defined to encompass this
3422 4 ADC clock cycle duration */
3423 /* Note: Test of ADC enabled required due to hardware constraint to */
3424 /* not enable ADC if already enabled. */
3425 if (LL_ADC_IsEnabled(hadc->Instance) == 0UL)
3426 {
3427 LL_ADC_Enable(hadc->Instance);
3428 }
3429
3430 if ((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT)
3431 {
3432 /* New check to avoid false timeout detection in case of preemption */
3433 if (__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == 0UL)
3434 {
3435 /* Update ADC state machine to error */
3436 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
3437
3438 /* Set ADC error code to ADC peripheral internal error */
3439 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
3440
3441 return HAL_ERROR;
3442 }
3443 }
3444 }
3445 }
3446 #endif
3447 }
3448
3449 /* Return HAL status */
3450 return HAL_OK;
3451 }
3452
3453 /**
3454 * @brief Disable the selected ADC.
3455 * @note Prerequisite condition to use this function: ADC conversions must be
3456 * stopped.
3457 * @param hadc ADC handle
3458 * @retval HAL status.
3459 */
ADC_Disable(ADC_HandleTypeDef * hadc)3460 HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef *hadc)
3461 {
3462 uint32_t tickstart;
3463 const uint32_t tmp_adc_is_disable_on_going = LL_ADC_IsDisableOngoing(hadc->Instance);
3464
3465 /* Verification if ADC is not already disabled: */
3466 /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */
3467 /* disabled. */
3468 if ((LL_ADC_IsEnabled(hadc->Instance) != 0UL)
3469 && (tmp_adc_is_disable_on_going == 0UL)
3470 )
3471 {
3472 /* Check if conditions to disable the ADC are fulfilled */
3473 if ((hadc->Instance->CR & (ADC_CR_JADSTART | ADC_CR_ADSTART | ADC_CR_ADEN)) == ADC_CR_ADEN)
3474 {
3475 /* Disable the ADC peripheral */
3476 LL_ADC_Disable(hadc->Instance);
3477 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOSMP | ADC_FLAG_RDY));
3478 }
3479 else
3480 {
3481 /* Update ADC state machine to error */
3482 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
3483
3484 /* Set ADC error code to ADC peripheral internal error */
3485 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
3486
3487 return HAL_ERROR;
3488 }
3489
3490 /* Wait for ADC effectively disabled */
3491 /* Get tick count */
3492 tickstart = HAL_GetTick();
3493
3494 while ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL)
3495 {
3496 if ((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT)
3497 {
3498 /* New check to avoid false timeout detection in case of preemption */
3499 if ((hadc->Instance->CR & ADC_CR_ADEN) != 0UL)
3500 {
3501 /* Update ADC state machine to error */
3502 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL);
3503
3504 /* Set ADC error code to ADC peripheral internal error */
3505 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL);
3506
3507 return HAL_ERROR;
3508 }
3509 }
3510 }
3511 }
3512
3513 /* Return HAL status */
3514 return HAL_OK;
3515 }
3516
3517 /**
3518 * @brief DMA transfer complete callback.
3519 * @param hdma pointer to DMA handle.
3520 * @retval None
3521 */
ADC_DMAConvCplt(DMA_HandleTypeDef * hdma)3522 void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
3523 {
3524 /* Retrieve ADC handle corresponding to current DMA handle */
3525 ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3526
3527 /* Update state machine on conversion status if not in error state */
3528 if ((hadc->State & (HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) == 0UL)
3529 {
3530 /* Set ADC state */
3531 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC);
3532
3533 /* Determine whether any further conversion upcoming on group regular */
3534 /* by external trigger, continuous mode or scan sequence on going */
3535 /* to disable interruption. */
3536 /* Is it the end of the regular sequence ? */
3537 if ((hadc->Instance->ISR & ADC_FLAG_EOS) != 0UL)
3538 {
3539 /* Are conversions software-triggered ? */
3540 if (LL_ADC_REG_IsTriggerSourceSWStart(hadc->Instance) != 0UL)
3541 {
3542 /* Is CONT bit set ? */
3543 if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_CONT) == 0UL)
3544 {
3545 /* CONT bit is not set, no more conversions expected */
3546 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
3547 if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL)
3548 {
3549 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
3550 }
3551 }
3552 }
3553 }
3554 else
3555 {
3556 /* DMA End of Transfer interrupt was triggered but conversions sequence
3557 is not over. If DMACFG is set to 0, conversions are stopped. */
3558 if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMNGT) == 0UL)
3559 {
3560 /* DMACFG bit is not set, conversions are stopped. */
3561 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY);
3562 if ((hadc->State & HAL_ADC_STATE_INJ_BUSY) == 0UL)
3563 {
3564 SET_BIT(hadc->State, HAL_ADC_STATE_READY);
3565 }
3566 }
3567 }
3568
3569 /* Conversion complete callback */
3570 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
3571 hadc->ConvCpltCallback(hadc);
3572 #else
3573 HAL_ADC_ConvCpltCallback(hadc);
3574 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
3575 }
3576 else /* DMA and-or internal error occurred */
3577 {
3578 if ((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) != 0UL)
3579 {
3580 /* Call HAL ADC Error Callback function */
3581 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
3582 hadc->ErrorCallback(hadc);
3583 #else
3584 HAL_ADC_ErrorCallback(hadc);
3585 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
3586 }
3587 else
3588 {
3589 /* Call ADC DMA error callback */
3590 hadc->DMA_Handle->XferErrorCallback(hdma);
3591 }
3592 }
3593 }
3594
3595 /**
3596 * @brief DMA half transfer complete callback.
3597 * @param hdma pointer to DMA handle.
3598 * @retval None
3599 */
ADC_DMAHalfConvCplt(DMA_HandleTypeDef * hdma)3600 void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
3601 {
3602 /* Retrieve ADC handle corresponding to current DMA handle */
3603 ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3604
3605 /* Half conversion callback */
3606 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
3607 hadc->ConvHalfCpltCallback(hadc);
3608 #else
3609 HAL_ADC_ConvHalfCpltCallback(hadc);
3610 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
3611 }
3612
3613 /**
3614 * @brief DMA error callback.
3615 * @param hdma pointer to DMA handle.
3616 * @retval None
3617 */
ADC_DMAError(DMA_HandleTypeDef * hdma)3618 void ADC_DMAError(DMA_HandleTypeDef *hdma)
3619 {
3620 /* Retrieve ADC handle corresponding to current DMA handle */
3621 ADC_HandleTypeDef *hadc = (ADC_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3622
3623 /* Set ADC state */
3624 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA);
3625
3626 /* Set ADC error code to DMA error */
3627 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA);
3628
3629 /* Error callback */
3630 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1)
3631 hadc->ErrorCallback(hadc);
3632 #else
3633 HAL_ADC_ErrorCallback(hadc);
3634 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */
3635 }
3636
3637 /**
3638 * @brief Configure boost mode of selected ADC.
3639 * @note Prerequisite condition to use this function: ADC conversions must be
3640 * stopped.
3641 * @param hadc ADC handle
3642 * @retval None.
3643 */
ADC_ConfigureBoostMode(ADC_HandleTypeDef * hadc)3644 void ADC_ConfigureBoostMode(ADC_HandleTypeDef* hadc)
3645 {
3646 uint32_t freq;
3647 if (ADC_IS_SYNCHRONOUS_CLOCK_MODE(hadc))
3648 {
3649 freq = HAL_RCC_GetHCLK2Freq();
3650 switch(hadc->Init.ClockPrescaler)
3651 {
3652 case ADC_CLOCK_SYNC_PCLK_DIV1:
3653 case ADC_CLOCK_SYNC_PCLK_DIV2:
3654 freq /= (hadc->Init.ClockPrescaler >> ADC_CCR_CKMODE_Pos);
3655 break;
3656 case ADC_CLOCK_SYNC_PCLK_DIV4:
3657 freq /= 4UL;
3658 break;
3659 default:
3660 break;
3661 }
3662 }
3663 else
3664 {
3665 freq = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_ADC);
3666 switch(hadc->Init.ClockPrescaler)
3667 {
3668 case ADC_CLOCK_ASYNC_DIV2:
3669 case ADC_CLOCK_ASYNC_DIV4:
3670 case ADC_CLOCK_ASYNC_DIV6:
3671 case ADC_CLOCK_ASYNC_DIV8:
3672 case ADC_CLOCK_ASYNC_DIV10:
3673 case ADC_CLOCK_ASYNC_DIV12:
3674 freq /= ((hadc->Init.ClockPrescaler >> ADC_CCR_PRESC_Pos) << 1UL);
3675 break;
3676 case ADC_CLOCK_ASYNC_DIV16:
3677 freq /= 16UL;
3678 break;
3679 case ADC_CLOCK_ASYNC_DIV32:
3680 freq /= 32UL;
3681 break;
3682 case ADC_CLOCK_ASYNC_DIV64:
3683 freq /= 64UL;
3684 break;
3685 case ADC_CLOCK_ASYNC_DIV128:
3686 freq /= 128UL;
3687 break;
3688 case ADC_CLOCK_ASYNC_DIV256:
3689 freq /= 256UL;
3690 break;
3691 default:
3692 break;
3693 }
3694 }
3695
3696 if (freq > 20000000UL)
3697 {
3698 SET_BIT(hadc->Instance->CR, ADC_CR_BOOST);
3699 }
3700 else
3701 {
3702 CLEAR_BIT(hadc->Instance->CR, 0);
3703 }
3704 }
3705
3706 /**
3707 * @}
3708 */
3709
3710 #endif /* HAL_ADC_MODULE_ENABLED */
3711 /**
3712 * @}
3713 */
3714
3715 /**
3716 * @}
3717 */
3718
