1 /**
2 ******************************************************************************
3 * @file stm32f7xx_hal_cryp.c
4 * @author MCD Application Team
5 * @brief CRYP HAL module driver.
6 * This file provides firmware functions to manage the following
7 * functionalities of the Cryptography (CRYP) peripheral:
8 * + Initialization, de-initialization, set config and get config functions
9 * + DES/TDES, AES processing functions
10 * + DMA callback functions
11 * + CRYP IRQ handler management
12 * + Peripheral State functions
13 *
14 ******************************************************************************
15 * @attention
16 *
17 * Copyright (c) 2017 STMicroelectronics.
18 * All rights reserved.
19 *
20 * This software is licensed under terms that can be found in the LICENSE file
21 * in the root directory of this software component.
22 * If no LICENSE file comes with this software, it is provided AS-IS.
23 *
24 ******************************************************************************
25 @verbatim
26 ==============================================================================
27 ##### How to use this driver #####
28 ==============================================================================
29 [..]
30 The CRYP HAL driver can be used in CRYP or TinyAES IP as follows:
31
32 (#)Initialize the CRYP low level resources by implementing the HAL_CRYP_MspInit():
33 (##) Enable the CRYP interface clock using __HAL_RCC_CRYP_CLK_ENABLE()or __HAL_RCC_AES_CLK_ENABLE for TinyAES IP
34 (##) In case of using interrupts (e.g. HAL_CRYP_Encrypt_IT())
35 (+++) Configure the CRYP interrupt priority using HAL_NVIC_SetPriority()
36 (+++) Enable the CRYP IRQ handler using HAL_NVIC_EnableIRQ()
37 (+++) In CRYP IRQ handler, call HAL_CRYP_IRQHandler()
38 (##) In case of using DMA to control data transfer (e.g. HAL_CRYP_Encrypt_DMA())
39 (+++) Enable the DMAx interface clock using __RCC_DMAx_CLK_ENABLE()
40 (+++) Configure and enable two DMA streams one for managing data transfer from
41 memory to peripheral (input stream) and another stream for managing data
42 transfer from peripheral to memory (output stream)
43 (+++) Associate the initialized DMA handle to the CRYP DMA handle
44 using __HAL_LINKDMA()
45 (+++) Configure the priority and enable the NVIC for the transfer complete
46 interrupt on the two DMA Streams. The output stream should have higher
47 priority than the input stream HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ()
48
49 (#)Initialize the CRYP according to the specified parameters :
50 (##) The data type: 1-bit, 8-bit, 16-bit or 32-bit.
51 (##) The key size: 128, 192 or 256.
52 (##) The AlgoMode DES/ TDES Algorithm ECB/CBC or AES Algorithm ECB/CBC/CTR/GCM or CCM.
53 (##) The initialization vector (counter). It is not used in ECB mode.
54 (##) The key buffer used for encryption/decryption.
55 (##) The Header used only in AES GCM and CCM Algorithm for authentication.
56 (##) The HeaderSize The size of header buffer in word.
57 (##) The B0 block is the first authentication block used only in AES CCM mode.
58
59 (#)Three processing (encryption/decryption) functions are available:
60 (##) Polling mode: encryption and decryption APIs are blocking functions
61 i.e. they process the data and wait till the processing is finished,
62 e.g. HAL_CRYP_Encrypt & HAL_CRYP_Decrypt
63 (##) Interrupt mode: encryption and decryption APIs are not blocking functions
64 i.e. they process the data under interrupt,
65 e.g. HAL_CRYP_Encrypt_IT & HAL_CRYP_Decrypt_IT
66 (##) DMA mode: encryption and decryption APIs are not blocking functions
67 i.e. the data transfer is ensured by DMA,
68 e.g. HAL_CRYP_Encrypt_DMA & HAL_CRYP_Decrypt_DMA
69
70 (#)When the processing function is called at first time after HAL_CRYP_Init()
71 the CRYP peripheral is configured and processes the buffer in input.
72 At second call, no need to Initialize the CRYP, user have to get current configuration via
73 HAL_CRYP_GetConfig() API, then only HAL_CRYP_SetConfig() is requested to set
74 new parametres, finally user can start encryption/decryption.
75
76 (#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral.
77
78 (#)To process a single message with consecutive calls to HAL_CRYP_Encrypt() or HAL_CRYP_Decrypt()
79 without having to configure again the Key or the Initialization Vector between each API call,
80 the field KeyIVConfigSkip of the initialization structure must be set to CRYP_KEYIVCONFIG_ONCE.
81 Same is true for consecutive calls of HAL_CRYP_Encrypt_IT(), HAL_CRYP_Decrypt_IT(), HAL_CRYP_Encrypt_DMA()
82 or HAL_CRYP_Decrypt_DMA().
83
84 [..]
85 The cryptographic processor supports following standards:
86 (#) The data encryption standard (DES) and Triple-DES (TDES) supported only by CRYP1 IP:
87 (##)64-bit data block processing
88 (##) chaining modes supported :
89 (+++) Electronic Code Book(ECB)
90 (+++) Cipher Block Chaining (CBC)
91 (##) keys length supported :64-bit, 128-bit and 192-bit.
92 (#) The advanced encryption standard (AES) supported by CRYP1 & TinyAES IP:
93 (##)128-bit data block processing
94 (##) chaining modes supported :
95 (+++) Electronic Code Book(ECB)
96 (+++) Cipher Block Chaining (CBC)
97 (+++) Counter mode (CTR)
98 (+++) Galois/counter mode (GCM/GMAC)
99 (+++) Counter with Cipher Block Chaining-Message(CCM)
100 (##) keys length Supported :
101 (+++) for CRYP1 IP: 128-bit, 192-bit and 256-bit.
102 (+++) for TinyAES IP: 128-bit and 256-bit
103
104 [..] This section describes the AES Galois/counter mode (GCM) supported by both CRYP1 IP:
105 (#) Algorithm supported :
106 (##) Galois/counter mode (GCM)
107 (##) Galois message authentication code (GMAC) :is exactly the same as
108 GCM algorithm composed only by an header.
109 (#) Four phases are performed in GCM :
110 (##) Init phase: IP prepares the GCM hash subkey (H) and do the IV processing
111 (##) Header phase: IP processes the Additional Authenticated Data (AAD), with hash
112 computation only.
113 (##) Payload phase: IP processes the plaintext (P) with hash computation + keystream
114 encryption + data XORing. It works in a similar way for ciphertext (C).
115 (##) Final phase: IP generates the authenticated tag (T) using the last block of data.
116 (#) structure of message construction in GCM is defined as below :
117 (##) 16 bytes Initial Counter Block (ICB)composed of IV and counter
118 (##) The authenticated header A (also knows as Additional Authentication Data AAD)
119 this part of the message is only authenticated, not encrypted.
120 (##) The plaintext message P is both authenticated and encrypted as ciphertext.
121 GCM standard specifies that ciphertext has same bit length as the plaintext.
122 (##) The last block is composed of the length of A (on 64 bits) and the length of ciphertext
123 (on 64 bits)
124
125 [..] This section describe The AES Counter with Cipher Block Chaining-Message
126 Authentication Code (CCM) supported by both CRYP1 IP:
127 (#) Specific parameters for CCM :
128
129 (##) B0 block : According to NIST Special Publication 800-38C,
130 The first block B0 is formatted as follows, where l(m) is encoded in
131 most-significant-byte first order(see below table 3)
132
133 (+++) Q: a bit string representation of the octet length of P (plaintext)
134 (+++) q The octet length of the binary representation of the octet length of the payload
135 (+++) A nonce (N), n The octet length of the where n+q=15.
136 (+++) Flags: most significant octet containing four flags for control information,
137 (+++) t The octet length of the MAC.
138 (##) B1 block (header) : associated data length(a) concatenated with Associated Data (A)
139 the associated data length expressed in bytes (a) defined as below:
140 (+++) If 0 < a < 216-28, then it is encoded as [a]16, i.e. two octets
141 (+++) If 216-28 < a < 232, then it is encoded as 0xff || 0xfe || [a]32, i.e. six octets
142 (+++) If 232 < a < 264, then it is encoded as 0xff || 0xff || [a]64, i.e. ten octets
143 (##) CTRx block : control blocks
144 (+++) Generation of CTR1 from first block B0 information :
145 equal to B0 with first 5 bits zeroed and most significant bits storing octet
146 length of P also zeroed, then incremented by one ( see below Table 4)
147 (+++) Generation of CTR0: same as CTR1 with bit[0] set to zero.
148
149 (#) Four phases are performed in CCM for CRYP1 IP:
150 (##) Init phase: IP prepares the GCM hash subkey (H) and do the IV processing
151 (##) Header phase: IP processes the Additional Authenticated Data (AAD), with hash
152 computation only.
153 (##) Payload phase: IP processes the plaintext (P) with hash computation + keystream
154 encryption + data XORing. It works in a similar way for ciphertext (C).
155 (##) Final phase: IP generates the authenticated tag (T) using the last block of data.
156
157 *** Callback registration ***
158 =============================================
159
160 The compilation define USE_HAL_CRYP_REGISTER_CALLBACKS when set to 1
161 allows the user to configure dynamically the driver callbacks.
162 Use Functions HAL_CRYP_RegisterCallback() or HAL_CRYP_RegisterXXXCallback()
163 to register an interrupt callback.
164
165 Function HAL_CRYP_RegisterCallback() allows to register following callbacks:
166 (+) InCpltCallback : Input FIFO transfer completed callback.
167 (+) OutCpltCallback : Output FIFO transfer completed callback.
168 (+) ErrorCallback : callback for error detection.
169 (+) MspInitCallback : CRYP MspInit.
170 (+) MspDeInitCallback : CRYP MspDeInit.
171 This function takes as parameters the HAL peripheral handle, the Callback ID
172 and a pointer to the user callback function.
173
174 Use function HAL_CRYP_UnRegisterCallback() to reset a callback to the default
175 weak function.
176 HAL_CRYP_UnRegisterCallback() takes as parameters the HAL peripheral handle,
177 and the Callback ID.
178 This function allows to reset following callbacks:
179 (+) InCpltCallback : Input FIFO transfer completed callback.
180 (+) OutCpltCallback : Output FIFO transfer completed callback.
181 (+) ErrorCallback : callback for error detection.
182 (+) MspInitCallback : CRYP MspInit.
183 (+) MspDeInitCallback : CRYP MspDeInit.
184
185 By default, after the HAL_CRYP_Init() and when the state is HAL_CRYP_STATE_RESET
186 all callbacks are set to the corresponding weak functions :
187 examples HAL_CRYP_InCpltCallback() , HAL_CRYP_OutCpltCallback().
188 Exception done for MspInit and MspDeInit functions that are
189 reset to the legacy weak function in the HAL_CRYP_Init()/ HAL_CRYP_DeInit() only when
190 these callbacks are null (not registered beforehand).
191 if not, MspInit or MspDeInit are not null, the HAL_CRYP_Init() / HAL_CRYP_DeInit()
192 keep and use the user MspInit/MspDeInit functions (registered beforehand)
193
194 Callbacks can be registered/unregistered in HAL_CRYP_STATE_READY state only.
195 Exception done MspInit/MspDeInit callbacks that can be registered/unregistered
196 in HAL_CRYP_STATE_READY or HAL_CRYP_STATE_RESET state,
197 thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
198 In that case first register the MspInit/MspDeInit user callbacks
199 using HAL_CRYP_RegisterCallback() before calling HAL_CRYP_DeInit()
200 or HAL_CRYP_Init() function.
201
202 When The compilation define USE_HAL_CRYP_REGISTER_CALLBACKS is set to 0 or
203 not defined, the callback registration feature is not available and all callbacks
204 are set to the corresponding weak functions.
205
206 Table 1. Initial Counter Block (ICB)
207 +-------------------------------------------------------+
208 | Initialization vector (IV) | Counter |
209 |----------------|----------------|-----------|---------|
210 127 95 63 31 0
211
212
213 Bit Number Register Contents
214 ---------- --------------- -----------
215 127 ...96 CRYP_IV1R[31:0] ICB[127:96]
216 95 ...64 CRYP_IV1L[31:0] B0[95:64]
217 63 ... 32 CRYP_IV0R[31:0] ICB[63:32]
218 31 ... 0 CRYP_IV0L[31:0] ICB[31:0], where 32-bit counter= 0x2
219
220 Table 2. GCM last block definition
221
222 +-------------------------------------------------------------------+
223 | Bit[0] | Bit[32] | Bit[64] | Bit[96] |
224 |-----------|--------------------|-----------|----------------------|
225 | 0x0 | Header length[31:0]| 0x0 | Payload length[31:0] |
226 |-----------|--------------------|-----------|----------------------|
227
228 Table 3. B0 block
229 Octet Number Contents
230 ------------ ---------
231 0 Flags
232 1 ... 15-q Nonce N
233 16-q ... 15 Q
234
235 the Flags field is formatted as follows:
236
237 Bit Number Contents
238 ---------- ----------------------
239 7 Reserved (always zero)
240 6 Adata
241 5 ... 3 (t-2)/2
242 2 ... 0 [q-1]3
243
244 Table 4. CTRx block
245 Bit Number Register Contents
246 ---------- --------------- -----------
247 127 ...96 CRYP_IV1R[31:0] B0[127:96], where Q length bits are set to 0, except for
248 bit 0 that is set to 1
249 95 ...64 CRYP_IV1L[31:0] B0[95:64]
250 63 ... 32 CRYP_IV0R[31:0] B0[63:32]
251 31 ... 0 CRYP_IV0L[31:0] B0[31:0], where flag bits set to 0
252
253 @endverbatim
254 ******************************************************************************
255 */
256
257 /* Includes ------------------------------------------------------------------*/
258 #include "stm32f7xx_hal.h"
259
260 /** @addtogroup STM32F7xx_HAL_Driver
261 * @{
262 */
263
264 #if defined (AES) || defined (CRYP)
265
266 /** @defgroup CRYP CRYP
267 * @brief CRYP HAL module driver.
268 * @{
269 */
270
271
272 #ifdef HAL_CRYP_MODULE_ENABLED
273
274 /* Private typedef -----------------------------------------------------------*/
275 /* Private define ------------------------------------------------------------*/
276 /** @addtogroup CRYP_Private_Defines
277 * @{
278 */
279 #define CRYP_TIMEOUT_KEYPREPARATION 82U /*The latency of key preparation operation is 82 clock cycles.*/
280 #define CRYP_TIMEOUT_GCMCCMINITPHASE 299U /* The latency of GCM/CCM init phase to prepare hash subkey is 299 clock cycles.*/
281 #define CRYP_TIMEOUT_GCMCCMHEADERPHASE 290U /* The latency of GCM/CCM header phase is 290 clock cycles.*/
282
283 #define CRYP_PHASE_READY 0x00000001U /*!< CRYP peripheral is ready for initialization. */
284 #define CRYP_PHASE_PROCESS 0x00000002U /*!< CRYP peripheral is in processing phase */
285
286 #if defined(AES)
287 #define CRYP_OPERATINGMODE_ENCRYPT 0x00000000U /*!< Encryption mode(Mode 1) */
288 #define CRYP_OPERATINGMODE_KEYDERIVATION AES_CR_MODE_0 /*!< Key derivation mode only used when performing ECB and CBC decryptions (Mode 2) */
289 #define CRYP_OPERATINGMODE_DECRYPT AES_CR_MODE_1 /*!< Decryption (Mode 3) */
290 #define CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT AES_CR_MODE /*!< Key derivation and decryption only used when performing ECB and CBC decryptions (Mode 4) */
291 #define CRYP_PHASE_INIT 0x00000000U /*!< GCM/GMAC (or CCM) init phase */
292 #define CRYP_PHASE_HEADER AES_CR_GCMPH_0 /*!< GCM/GMAC or CCM header phase */
293 #define CRYP_PHASE_PAYLOAD AES_CR_GCMPH_1 /*!< GCM(/CCM) payload phase */
294 #define CRYP_PHASE_FINAL AES_CR_GCMPH /*!< GCM/GMAC or CCM final phase */
295 #else /* CRYP */
296 #define CRYP_PHASE_INIT 0x00000000U /*!< GCM/GMAC (or CCM) init phase */
297 #define CRYP_PHASE_HEADER CRYP_CR_GCM_CCMPH_0 /*!< GCM/GMAC or CCM header phase */
298 #define CRYP_PHASE_PAYLOAD CRYP_CR_GCM_CCMPH_1 /*!< GCM(/CCM) payload phase */
299 #define CRYP_PHASE_FINAL CRYP_CR_GCM_CCMPH /*!< GCM/GMAC or CCM final phase */
300 #define CRYP_OPERATINGMODE_ENCRYPT 0x00000000U /*!< Encryption mode */
301 #define CRYP_OPERATINGMODE_DECRYPT CRYP_CR_ALGODIR /*!< Decryption */
302 #endif /* End CRYP or AES */
303
304 /* CTR1 information to use in CCM algorithm */
305 #define CRYP_CCM_CTR1_0 0x07FFFFFFU
306 #define CRYP_CCM_CTR1_1 0xFFFFFF00U
307 #define CRYP_CCM_CTR1_2 0x00000001U
308
309
310 /**
311 * @}
312 */
313
314
315 /* Private macro -------------------------------------------------------------*/
316 /** @addtogroup CRYP_Private_Macros
317 * @{
318 */
319
320 #if defined(CRYP)
321
322 #define CRYP_SET_PHASE(__HANDLE__, __PHASE__) do{(__HANDLE__)->Instance->CR &= (uint32_t)(~CRYP_CR_GCM_CCMPH);\
323 (__HANDLE__)->Instance->CR |= (uint32_t)(__PHASE__);\
324 }while(0)
325
326 #define HAL_CRYP_FIFO_FLUSH(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRYP_CR_FFLUSH)
327
328 #else /*AES*/
329 #define CRYP_SET_PHASE(__HANDLE__, __PHASE__) do{(__HANDLE__)->Instance->CR &= (uint32_t)(~AES_CR_GCMPH);\
330 (__HANDLE__)->Instance->CR |= (uint32_t)(__PHASE__);\
331 }while(0)
332 #endif /* End AES or CRYP*/
333
334
335 /**
336 * @}
337 */
338
339 /* Private struct -------------------------------------------------------------*/
340 /* Private variables ---------------------------------------------------------*/
341 /* Private function prototypes -----------------------------------------------*/
342 /** @addtogroup CRYP_Private_Functions_prototypes
343 * @{
344 */
345
346 static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr);
347 static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma);
348 static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma);
349 static void CRYP_DMAError(DMA_HandleTypeDef *hdma);
350 static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint32_t KeySize);
351 static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp);
352
353 static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
354 static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp);
355 static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp);
356 static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcryp);
357 static void CRYP_Workaround(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
358 static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp);
359 static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp);
360 static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
361 static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
362 static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp);
363 static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp);
364
365 static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcrypt, uint32_t Timeout);
366 static HAL_StatusTypeDef CRYP_AES_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
367 static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
368 static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp);
369 static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp);
370 static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp);
371 #if defined (CRYP)
372 static void CRYP_TDES_IT(CRYP_HandleTypeDef *hcryp);
373
374 static HAL_StatusTypeDef CRYP_WaitOnIFEMFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
375
376 static HAL_StatusTypeDef CRYP_WaitOnBUSYFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
377 static HAL_StatusTypeDef CRYP_WaitOnOFNEFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
378 static HAL_StatusTypeDef CRYP_TDES_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
379 #else /*AES*/
380 static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout);
381 #endif /* End CRYP or AES */
382
383 /**
384 * @}
385 */
386
387 /* Exported functions ---------------------------------------------------------*/
388
389 /** @defgroup CRYP_Exported_Functions CRYP Exported Functions
390 * @{
391 */
392
393
394 /** @defgroup CRYP_Exported_Functions_Group1 Initialization and de-initialization functions
395 * @brief Initialization and Configuration functions.
396 *
397 @verbatim
398 ========================================================================================
399 ##### Initialization, de-initialization and Set and Get configuration functions #####
400 ========================================================================================
401 [..] This section provides functions allowing to:
402 (+) Initialize the CRYP
403 (+) DeInitialize the CRYP
404 (+) Initialize the CRYP MSP
405 (+) DeInitialize the CRYP MSP
406 (+) configure CRYP (HAL_CRYP_SetConfig) with the specified parameters in the CRYP_ConfigTypeDef
407 Parameters which are configured in This section are :
408 (+) Key size
409 (+) Data Type : 32,16, 8 or 1bit
410 (+) AlgoMode :
411 - for CRYP1 IP :
412 ECB and CBC in DES/TDES Standard
413 ECB,CBC,CTR,GCM/GMAC and CCM in AES Standard.
414 - for TinyAES2 IP, only ECB,CBC,CTR,GCM/GMAC and CCM in AES Standard are supported.
415 (+) Get CRYP configuration (HAL_CRYP_GetConfig) from the specified parameters in the CRYP_HandleTypeDef
416
417
418 @endverbatim
419 * @{
420 */
421
422
423 /**
424 * @brief Initializes the CRYP according to the specified
425 * parameters in the CRYP_ConfigTypeDef and creates the associated handle.
426 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
427 * the configuration information for CRYP module
428 * @retval HAL status
429 */
HAL_CRYP_Init(CRYP_HandleTypeDef * hcryp)430 HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp)
431 {
432 /* Check the CRYP handle allocation */
433 if (hcryp == NULL)
434 {
435 return HAL_ERROR;
436 }
437
438 /* Check parameters */
439 assert_param(IS_CRYP_KEYSIZE(hcryp->Init.KeySize));
440 assert_param(IS_CRYP_DATATYPE(hcryp->Init.DataType));
441 assert_param(IS_CRYP_ALGORITHM(hcryp->Init.Algorithm));
442 assert_param(IS_CRYP_INIT(hcryp->Init.KeyIVConfigSkip));
443
444 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
445 if (hcryp->State == HAL_CRYP_STATE_RESET)
446 {
447 /* Allocate lock resource and initialize it */
448 hcryp->Lock = HAL_UNLOCKED;
449
450 hcryp->InCpltCallback = HAL_CRYP_InCpltCallback; /* Legacy weak InCpltCallback */
451 hcryp->OutCpltCallback = HAL_CRYP_OutCpltCallback; /* Legacy weak OutCpltCallback */
452 hcryp->ErrorCallback = HAL_CRYP_ErrorCallback; /* Legacy weak ErrorCallback */
453
454 if (hcryp->MspInitCallback == NULL)
455 {
456 hcryp->MspInitCallback = HAL_CRYP_MspInit; /* Legacy weak MspInit */
457 }
458
459 /* Init the low level hardware */
460 hcryp->MspInitCallback(hcryp);
461 }
462 #else
463 if (hcryp->State == HAL_CRYP_STATE_RESET)
464 {
465 /* Allocate lock resource and initialize it */
466 hcryp->Lock = HAL_UNLOCKED;
467
468 /* Init the low level hardware */
469 HAL_CRYP_MspInit(hcryp);
470 }
471 #endif /* (USE_HAL_CRYP_REGISTER_CALLBACKS) */
472
473 /* Set the key size(This bit field is don't care in the DES or TDES modes) data type and Algorithm */
474 #if defined (CRYP)
475
476 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_DATATYPE | CRYP_CR_KEYSIZE | CRYP_CR_ALGOMODE,
477 hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm);
478
479 #else /*AES*/
480
481 MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD,
482 hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm);
483
484 #endif /* End AES or CRYP*/
485
486 /* Reset Error Code field */
487 hcryp->ErrorCode = HAL_CRYP_ERROR_NONE;
488
489 /* Change the CRYP state */
490 hcryp->State = HAL_CRYP_STATE_READY;
491
492 /* Set the default CRYP phase */
493 hcryp->Phase = CRYP_PHASE_READY;
494
495 /* Return function status */
496 return HAL_OK;
497 }
498
499 /**
500 * @brief De-Initializes the CRYP peripheral.
501 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
502 * the configuration information for CRYP module
503 * @retval HAL status
504 */
HAL_CRYP_DeInit(CRYP_HandleTypeDef * hcryp)505 HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp)
506 {
507 /* Check the CRYP handle allocation */
508 if (hcryp == NULL)
509 {
510 return HAL_ERROR;
511 }
512
513 /* Set the default CRYP phase */
514 hcryp->Phase = CRYP_PHASE_READY;
515
516 /* Reset CrypInCount and CrypOutCount */
517 hcryp->CrypInCount = 0;
518 hcryp->CrypOutCount = 0;
519 hcryp->CrypHeaderCount = 0;
520
521 /* Disable the CRYP peripheral clock */
522 __HAL_CRYP_DISABLE(hcryp);
523
524 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
525
526 if (hcryp->MspDeInitCallback == NULL)
527 {
528 hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit; /* Legacy weak MspDeInit */
529 }
530 /* DeInit the low level hardware */
531 hcryp->MspDeInitCallback(hcryp);
532
533 #else
534
535 /* DeInit the low level hardware: CLOCK, NVIC.*/
536 HAL_CRYP_MspDeInit(hcryp);
537
538 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
539
540 /* Change the CRYP state */
541 hcryp->State = HAL_CRYP_STATE_RESET;
542
543 /* Release Lock */
544 __HAL_UNLOCK(hcryp);
545
546 /* Return function status */
547 return HAL_OK;
548 }
549
550 /**
551 * @brief Configure the CRYP according to the specified
552 * parameters in the CRYP_ConfigTypeDef
553 * @param hcryp: pointer to a CRYP_HandleTypeDef structure
554 * @param pConf: pointer to a CRYP_ConfigTypeDef structure that contains
555 * the configuration information for CRYP module
556 * @retval HAL status
557 */
HAL_CRYP_SetConfig(CRYP_HandleTypeDef * hcryp,CRYP_ConfigTypeDef * pConf)558 HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf)
559 {
560 /* Check the CRYP handle allocation */
561 if ((hcryp == NULL) || (pConf == NULL))
562 {
563 return HAL_ERROR;
564 }
565
566 /* Check parameters */
567 assert_param(IS_CRYP_KEYSIZE(pConf->KeySize));
568 assert_param(IS_CRYP_DATATYPE(pConf->DataType));
569 assert_param(IS_CRYP_ALGORITHM(pConf->Algorithm));
570
571 if (hcryp->State == HAL_CRYP_STATE_READY)
572 {
573 /* Change the CRYP state */
574 hcryp->State = HAL_CRYP_STATE_BUSY;
575
576 /* Process locked */
577 __HAL_LOCK(hcryp);
578
579 /* Set CRYP parameters */
580 hcryp->Init.DataType = pConf->DataType;
581 hcryp->Init.pKey = pConf->pKey;
582 hcryp->Init.Algorithm = pConf->Algorithm;
583 hcryp->Init.KeySize = pConf->KeySize;
584 hcryp->Init.pInitVect = pConf->pInitVect;
585 hcryp->Init.Header = pConf->Header;
586 hcryp->Init.HeaderSize = pConf->HeaderSize;
587 hcryp->Init.B0 = pConf->B0;
588 hcryp->Init.DataWidthUnit = pConf->DataWidthUnit;
589 hcryp->Init.KeyIVConfigSkip = pConf->KeyIVConfigSkip;
590 hcryp->Init.HeaderWidthUnit = pConf->HeaderWidthUnit;
591
592 /* Set the key size(This bit field is don't care in the DES or TDES modes) data type, AlgoMode and operating mode*/
593 #if defined (CRYP)
594
595 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_DATATYPE | CRYP_CR_KEYSIZE | CRYP_CR_ALGOMODE,
596 hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm);
597
598 #else /*AES*/
599 MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE | AES_CR_KEYSIZE | AES_CR_CHMOD,
600 hcryp->Init.DataType | hcryp->Init.KeySize | hcryp->Init.Algorithm);
601
602 /*clear error flags*/
603 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_ERR_CLEAR);
604
605 #endif /* End AES or CRYP */
606
607 /* Process Unlocked */
608 __HAL_UNLOCK(hcryp);
609
610 /* Reset Error Code field */
611 hcryp->ErrorCode = HAL_CRYP_ERROR_NONE;
612
613 /* Change the CRYP state */
614 hcryp->State = HAL_CRYP_STATE_READY;
615
616 /* Set the default CRYP phase */
617 hcryp->Phase = CRYP_PHASE_READY;
618
619 /* Return function status */
620 return HAL_OK;
621 }
622 else
623 {
624 /* Process Unlocked */
625 __HAL_UNLOCK(hcryp);
626
627 /* Busy error code field */
628 hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
629 return HAL_ERROR;
630 }
631 }
632
633 /**
634 * @brief Get CRYP Configuration parameters in associated handle.
635 * @param pConf: pointer to a CRYP_ConfigTypeDef structure
636 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
637 * the configuration information for CRYP module
638 * @retval HAL status
639 */
HAL_CRYP_GetConfig(CRYP_HandleTypeDef * hcryp,CRYP_ConfigTypeDef * pConf)640 HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf)
641 {
642 /* Check the CRYP handle allocation */
643 if ((hcryp == NULL) || (pConf == NULL))
644 {
645 return HAL_ERROR;
646 }
647
648 if (hcryp->State == HAL_CRYP_STATE_READY)
649 {
650 /* Change the CRYP state */
651 hcryp->State = HAL_CRYP_STATE_BUSY;
652
653 /* Process locked */
654 __HAL_LOCK(hcryp);
655
656 /* Get CRYP parameters */
657 pConf->DataType = hcryp->Init.DataType;
658 pConf->pKey = hcryp->Init.pKey;
659 pConf->Algorithm = hcryp->Init.Algorithm;
660 pConf->KeySize = hcryp->Init.KeySize ;
661 pConf->pInitVect = hcryp->Init.pInitVect;
662 pConf->Header = hcryp->Init.Header ;
663 pConf->HeaderSize = hcryp->Init.HeaderSize;
664 pConf->B0 = hcryp->Init.B0;
665 pConf->DataWidthUnit = hcryp->Init.DataWidthUnit;
666 pConf->KeyIVConfigSkip = hcryp->Init.KeyIVConfigSkip;
667 pConf->HeaderWidthUnit = hcryp->Init.HeaderWidthUnit;
668
669 /* Process Unlocked */
670 __HAL_UNLOCK(hcryp);
671
672 /* Change the CRYP state */
673 hcryp->State = HAL_CRYP_STATE_READY;
674
675 /* Return function status */
676 return HAL_OK;
677 }
678 else
679 {
680 /* Process Unlocked */
681 __HAL_UNLOCK(hcryp);
682
683 /* Busy error code field */
684 hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
685 return HAL_ERROR;
686 }
687 }
688 /**
689 * @brief Initializes the CRYP MSP.
690 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
691 * the configuration information for CRYP module
692 * @retval None
693 */
HAL_CRYP_MspInit(CRYP_HandleTypeDef * hcryp)694 __weak void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp)
695 {
696 /* Prevent unused argument(s) compilation warning */
697 UNUSED(hcryp);
698
699 /* NOTE : This function should not be modified, when the callback is needed,
700 the HAL_CRYP_MspInit can be implemented in the user file
701 */
702 }
703
704 /**
705 * @brief DeInitializes CRYP MSP.
706 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
707 * the configuration information for CRYP module
708 * @retval None
709 */
HAL_CRYP_MspDeInit(CRYP_HandleTypeDef * hcryp)710 __weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp)
711 {
712 /* Prevent unused argument(s) compilation warning */
713 UNUSED(hcryp);
714
715 /* NOTE : This function should not be modified, when the callback is needed,
716 the HAL_CRYP_MspDeInit can be implemented in the user file
717 */
718 }
719
720 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
721 /**
722 * @brief Register a User CRYP Callback
723 * To be used instead of the weak predefined callback
724 * @param hcryp cryp handle
725 * @param CallbackID ID of the callback to be registered
726 * This parameter can be one of the following values:
727 * @arg @ref HAL_CRYP_INPUT_COMPLETE_CB_ID Input FIFO transfer completed callback ID
728 * @arg @ref HAL_CRYP_OUTPUT_COMPLETE_CB_ID Output FIFO transfer completed callback ID
729 * @arg @ref HAL_CRYP_ERROR_CB_ID Error callback ID
730 * @arg @ref HAL_CRYP_MSPINIT_CB_ID MspInit callback ID
731 * @arg @ref HAL_CRYP_MSPDEINIT_CB_ID MspDeInit callback ID
732 * @param pCallback pointer to the Callback function
733 * @retval status
734 */
HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef * hcryp,HAL_CRYP_CallbackIDTypeDef CallbackID,pCRYP_CallbackTypeDef pCallback)735 HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID,
736 pCRYP_CallbackTypeDef pCallback)
737 {
738 HAL_StatusTypeDef status = HAL_OK;
739
740 if (pCallback == NULL)
741 {
742 /* Update the error code */
743 hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
744
745 return HAL_ERROR;
746 }
747 /* Process locked */
748 __HAL_LOCK(hcryp);
749
750 if (hcryp->State == HAL_CRYP_STATE_READY)
751 {
752 switch (CallbackID)
753 {
754 case HAL_CRYP_INPUT_COMPLETE_CB_ID :
755 hcryp->InCpltCallback = pCallback;
756 break;
757
758 case HAL_CRYP_OUTPUT_COMPLETE_CB_ID :
759 hcryp->OutCpltCallback = pCallback;
760 break;
761
762 case HAL_CRYP_ERROR_CB_ID :
763 hcryp->ErrorCallback = pCallback;
764 break;
765
766 case HAL_CRYP_MSPINIT_CB_ID :
767 hcryp->MspInitCallback = pCallback;
768 break;
769
770 case HAL_CRYP_MSPDEINIT_CB_ID :
771 hcryp->MspDeInitCallback = pCallback;
772 break;
773
774 default :
775 /* Update the error code */
776 hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
777 /* Return error status */
778 status = HAL_ERROR;
779 break;
780 }
781 }
782 else if (hcryp->State == HAL_CRYP_STATE_RESET)
783 {
784 switch (CallbackID)
785 {
786 case HAL_CRYP_MSPINIT_CB_ID :
787 hcryp->MspInitCallback = pCallback;
788 break;
789
790 case HAL_CRYP_MSPDEINIT_CB_ID :
791 hcryp->MspDeInitCallback = pCallback;
792 break;
793
794 default :
795 /* Update the error code */
796 hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
797 /* Return error status */
798 status = HAL_ERROR;
799 break;
800 }
801 }
802 else
803 {
804 /* Update the error code */
805 hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
806 /* Return error status */
807 status = HAL_ERROR;
808 }
809
810 /* Release Lock */
811 __HAL_UNLOCK(hcryp);
812
813 return status;
814 }
815
816 /**
817 * @brief Unregister an CRYP Callback
818 * CRYP callback is redirected to the weak predefined callback
819 * @param hcryp cryp handle
820 * @param CallbackID ID of the callback to be unregistered
821 * This parameter can be one of the following values:
822 * @arg @ref HAL_CRYP_INPUT_COMPLETE_CB_ID Input FIFO transfer completed callback ID
823 * @arg @ref HAL_CRYP_OUTPUT_COMPLETE_CB_ID Output FIFO transfer completed callback ID
824 * @arg @ref HAL_CRYP_ERROR_CB_ID Error callback ID
825 * @arg @ref HAL_CRYP_MSPINIT_CB_ID MspInit callback ID
826 * @arg @ref HAL_CRYP_MSPDEINIT_CB_ID MspDeInit callback ID
827 * @retval status
828 */
HAL_CRYP_UnRegisterCallback(CRYP_HandleTypeDef * hcryp,HAL_CRYP_CallbackIDTypeDef CallbackID)829 HAL_StatusTypeDef HAL_CRYP_UnRegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID)
830 {
831 HAL_StatusTypeDef status = HAL_OK;
832
833 /* Process locked */
834 __HAL_LOCK(hcryp);
835
836 if (hcryp->State == HAL_CRYP_STATE_READY)
837 {
838 switch (CallbackID)
839 {
840 case HAL_CRYP_INPUT_COMPLETE_CB_ID :
841 hcryp->InCpltCallback = HAL_CRYP_InCpltCallback; /* Legacy weak InCpltCallback */
842 break;
843
844 case HAL_CRYP_OUTPUT_COMPLETE_CB_ID :
845 hcryp->OutCpltCallback = HAL_CRYP_OutCpltCallback; /* Legacy weak OutCpltCallback */
846 break;
847
848 case HAL_CRYP_ERROR_CB_ID :
849 hcryp->ErrorCallback = HAL_CRYP_ErrorCallback; /* Legacy weak ErrorCallback */
850 break;
851
852 case HAL_CRYP_MSPINIT_CB_ID :
853 hcryp->MspInitCallback = HAL_CRYP_MspInit;
854 break;
855
856 case HAL_CRYP_MSPDEINIT_CB_ID :
857 hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit;
858 break;
859
860 default :
861 /* Update the error code */
862 hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
863 /* Return error status */
864 status = HAL_ERROR;
865 break;
866 }
867 }
868 else if (hcryp->State == HAL_CRYP_STATE_RESET)
869 {
870 switch (CallbackID)
871 {
872 case HAL_CRYP_MSPINIT_CB_ID :
873 hcryp->MspInitCallback = HAL_CRYP_MspInit;
874 break;
875
876 case HAL_CRYP_MSPDEINIT_CB_ID :
877 hcryp->MspDeInitCallback = HAL_CRYP_MspDeInit;
878 break;
879
880 default :
881 /* Update the error code */
882 hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
883 /* Return error status */
884 status = HAL_ERROR;
885 break;
886 }
887 }
888 else
889 {
890 /* Update the error code */
891 hcryp->ErrorCode |= HAL_CRYP_ERROR_INVALID_CALLBACK;
892 /* Return error status */
893 status = HAL_ERROR;
894 }
895
896 /* Release Lock */
897 __HAL_UNLOCK(hcryp);
898
899 return status;
900 }
901 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */
902 /**
903 * @}
904 */
905
906 /** @defgroup CRYP_Exported_Functions_Group2 Encrypt Decrypt functions
907 * @brief processing functions.
908 *
909 @verbatim
910 ==============================================================================
911 ##### Encrypt Decrypt functions #####
912 ==============================================================================
913 [..] This section provides API allowing to Encrypt/Decrypt Data following
914 Standard DES/TDES or AES, and Algorithm configured by the user:
915 (+) Standard DES/TDES only supported by CRYP1 IP, below list of Algorithm supported :
916 - Electronic Code Book(ECB)
917 - Cipher Block Chaining (CBC)
918 (+) Standard AES supported by CRYP1 IP & TinyAES, list of Algorithm supported:
919 - Electronic Code Book(ECB)
920 - Cipher Block Chaining (CBC)
921 - Counter mode (CTR)
922 - Cipher Block Chaining (CBC)
923 - Counter mode (CTR)
924 - Galois/counter mode (GCM)
925 - Counter with Cipher Block Chaining-Message(CCM)
926 [..] Three processing functions are available:
927 (+) Polling mode : HAL_CRYP_Encrypt & HAL_CRYP_Decrypt
928 (+) Interrupt mode : HAL_CRYP_Encrypt_IT & HAL_CRYP_Decrypt_IT
929 (+) DMA mode : HAL_CRYP_Encrypt_DMA & HAL_CRYP_Decrypt_DMA
930
931 @endverbatim
932 * @{
933 */
934
935
936 /**
937 * @brief Encryption mode.
938 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
939 * the configuration information for CRYP module
940 * @param Input: Pointer to the input buffer (plaintext)
941 * @param Size: Length of the plaintext buffer in word.
942 * @param Output: Pointer to the output buffer(ciphertext)
943 * @param Timeout: Specify Timeout value
944 * @retval HAL status
945 */
HAL_CRYP_Encrypt(CRYP_HandleTypeDef * hcryp,uint32_t * Input,uint16_t Size,uint32_t * Output,uint32_t Timeout)946 HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output,
947 uint32_t Timeout)
948 {
949 uint32_t algo;
950 HAL_StatusTypeDef status;
951
952 if (hcryp->State == HAL_CRYP_STATE_READY)
953 {
954 /* Change state Busy */
955 hcryp->State = HAL_CRYP_STATE_BUSY;
956
957 /* Process locked */
958 __HAL_LOCK(hcryp);
959
960 /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/
961 hcryp->CrypInCount = 0U;
962 hcryp->CrypOutCount = 0U;
963 hcryp->pCrypInBuffPtr = Input;
964 hcryp->pCrypOutBuffPtr = Output;
965
966 /* Calculate Size parameter in Byte*/
967 if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
968 {
969 hcryp->Size = Size * 4U;
970 }
971 else
972 {
973 hcryp->Size = Size;
974 }
975
976 #if defined (CRYP)
977 /* Set Encryption operating mode*/
978 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_ENCRYPT);
979
980 /* algo get algorithm selected */
981 algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE;
982
983 switch (algo)
984 {
985 case CRYP_DES_ECB:
986 case CRYP_DES_CBC:
987 case CRYP_TDES_ECB:
988 case CRYP_TDES_CBC:
989
990 /*Set Key */
991 hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey);
992 hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1);
993 if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
994 {
995 hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2);
996 hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 3);
997 hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 4);
998 hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 5);
999 }
1000
1001 /*Set Initialization Vector (IV)*/
1002 if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
1003 {
1004 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
1005 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
1006 }
1007
1008 /* Flush FIFO */
1009 HAL_CRYP_FIFO_FLUSH(hcryp);
1010
1011 /* Set the phase */
1012 hcryp->Phase = CRYP_PHASE_PROCESS;
1013
1014 /* Statrt DES/TDES encryption process */
1015 status = CRYP_TDES_Process(hcryp, Timeout);
1016 break;
1017
1018 case CRYP_AES_ECB:
1019 case CRYP_AES_CBC:
1020 case CRYP_AES_CTR:
1021
1022 /* AES encryption */
1023 status = CRYP_AES_Encrypt(hcryp, Timeout);
1024 break;
1025
1026 case CRYP_AES_GCM:
1027
1028 /* AES GCM encryption */
1029 status = CRYP_AESGCM_Process(hcryp, Timeout);
1030
1031 break;
1032
1033 case CRYP_AES_CCM:
1034
1035 /* AES CCM encryption */
1036 status = CRYP_AESCCM_Process(hcryp, Timeout);
1037 break;
1038
1039 default:
1040 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
1041 /* Change the CRYP peripheral state */
1042 hcryp->State = HAL_CRYP_STATE_READY;
1043 /* Process unlocked */
1044 __HAL_UNLOCK(hcryp);
1045 return HAL_ERROR;
1046 }
1047
1048 #else /*AES*/
1049
1050 /* Set the operating mode*/
1051 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
1052
1053 /* algo get algorithm selected */
1054 algo = hcryp->Instance->CR & AES_CR_CHMOD;
1055
1056 switch (algo)
1057 {
1058
1059 case CRYP_AES_ECB:
1060 case CRYP_AES_CBC:
1061 case CRYP_AES_CTR:
1062
1063 /* AES encryption */
1064 status = CRYP_AES_Encrypt(hcryp, Timeout);
1065 break;
1066
1067 case CRYP_AES_GCM_GMAC:
1068
1069 /* AES GCM encryption */
1070 status = CRYP_AESGCM_Process(hcryp, Timeout) ;
1071 break;
1072
1073 case CRYP_AES_CCM:
1074
1075 /* AES CCM encryption */
1076 status = CRYP_AESCCM_Process(hcryp, Timeout);
1077 break;
1078
1079 default:
1080 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
1081 /* Change the CRYP peripheral state */
1082 hcryp->State = HAL_CRYP_STATE_READY;
1083 /* Process unlocked */
1084 __HAL_UNLOCK(hcryp);
1085 return HAL_ERROR;
1086 }
1087 #endif /*end AES or CRYP */
1088
1089 if (status == HAL_OK)
1090 {
1091 /* Change the CRYP peripheral state */
1092 hcryp->State = HAL_CRYP_STATE_READY;
1093
1094 /* Process unlocked */
1095 __HAL_UNLOCK(hcryp);
1096 }
1097 }
1098 else
1099 {
1100 /* Busy error code field */
1101 hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
1102 return HAL_ERROR;
1103 }
1104
1105 /* Return function status */
1106 return HAL_OK;
1107 }
1108
1109 /**
1110 * @brief Decryption mode.
1111 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
1112 * the configuration information for CRYP module
1113 * @param Input: Pointer to the input buffer (ciphertext )
1114 * @param Size: Length of the plaintext buffer in word.
1115 * @param Output: Pointer to the output buffer(plaintext)
1116 * @param Timeout: Specify Timeout value
1117 * @retval HAL status
1118 */
HAL_CRYP_Decrypt(CRYP_HandleTypeDef * hcryp,uint32_t * Input,uint16_t Size,uint32_t * Output,uint32_t Timeout)1119 HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output,
1120 uint32_t Timeout)
1121 {
1122 HAL_StatusTypeDef status;
1123 uint32_t algo;
1124
1125 if (hcryp->State == HAL_CRYP_STATE_READY)
1126 {
1127 /* Change state Busy */
1128 hcryp->State = HAL_CRYP_STATE_BUSY;
1129
1130 /* Process locked */
1131 __HAL_LOCK(hcryp);
1132
1133 /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/
1134 hcryp->CrypInCount = 0U;
1135 hcryp->CrypOutCount = 0U;
1136 hcryp->pCrypInBuffPtr = Input;
1137 hcryp->pCrypOutBuffPtr = Output;
1138
1139 /* Calculate Size parameter in Byte*/
1140 if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
1141 {
1142 hcryp->Size = Size * 4U;
1143 }
1144 else
1145 {
1146 hcryp->Size = Size;
1147 }
1148
1149 #if defined (CRYP)
1150
1151 /* Set Decryption operating mode*/
1152 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_DECRYPT);
1153
1154 /* algo get algorithm selected */
1155 algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE;
1156
1157 switch (algo)
1158 {
1159 case CRYP_DES_ECB:
1160 case CRYP_DES_CBC:
1161 case CRYP_TDES_ECB:
1162 case CRYP_TDES_CBC:
1163
1164 /*Set Key */
1165 hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey);
1166 hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1);
1167 if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
1168 {
1169 hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2);
1170 hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 3);
1171 hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 4);
1172 hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 5);
1173 }
1174
1175 /*Set Initialization Vector (IV)*/
1176 if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
1177 {
1178 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
1179 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
1180 }
1181
1182 /* Flush FIFO */
1183 HAL_CRYP_FIFO_FLUSH(hcryp);
1184
1185 /* Set the phase */
1186 hcryp->Phase = CRYP_PHASE_PROCESS;
1187
1188 /* Start DES/TDES decryption process */
1189 status = CRYP_TDES_Process(hcryp, Timeout);
1190
1191 break;
1192
1193 case CRYP_AES_ECB:
1194 case CRYP_AES_CBC:
1195 case CRYP_AES_CTR:
1196
1197 /* AES decryption */
1198 status = CRYP_AES_Decrypt(hcryp, Timeout);
1199 break;
1200
1201 case CRYP_AES_GCM:
1202
1203 /* AES GCM decryption */
1204 status = CRYP_AESGCM_Process(hcryp, Timeout) ;
1205 break;
1206
1207 case CRYP_AES_CCM:
1208
1209 /* AES CCM decryption */
1210 status = CRYP_AESCCM_Process(hcryp, Timeout);
1211 break;
1212
1213 default:
1214 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
1215 /* Change the CRYP peripheral state */
1216 hcryp->State = HAL_CRYP_STATE_READY;
1217 /* Process unlocked */
1218 __HAL_UNLOCK(hcryp);
1219 return HAL_ERROR;
1220 }
1221
1222 #else /*AES*/
1223
1224 /* Set Decryption operating mode*/
1225 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
1226
1227 /* algo get algorithm selected */
1228 algo = hcryp->Instance->CR & AES_CR_CHMOD;
1229
1230 switch (algo)
1231 {
1232
1233 case CRYP_AES_ECB:
1234 case CRYP_AES_CBC:
1235 case CRYP_AES_CTR:
1236
1237 /* AES decryption */
1238 status = CRYP_AES_Decrypt(hcryp, Timeout);
1239 break;
1240
1241 case CRYP_AES_GCM_GMAC:
1242
1243 /* AES GCM decryption */
1244 status = CRYP_AESGCM_Process(hcryp, Timeout) ;
1245 break;
1246
1247 case CRYP_AES_CCM:
1248
1249 /* AES CCM decryption */
1250 status = CRYP_AESCCM_Process(hcryp, Timeout);
1251 break;
1252
1253 default:
1254 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
1255 /* Change the CRYP peripheral state */
1256 hcryp->State = HAL_CRYP_STATE_READY;
1257 /* Process unlocked */
1258 __HAL_UNLOCK(hcryp);
1259 return HAL_ERROR;
1260 }
1261 #endif /* End AES or CRYP */
1262
1263 if (status == HAL_OK)
1264 {
1265 /* Change the CRYP peripheral state */
1266 hcryp->State = HAL_CRYP_STATE_READY;
1267
1268 /* Process unlocked */
1269 __HAL_UNLOCK(hcryp);
1270 }
1271 }
1272 else
1273 {
1274 /* Busy error code field */
1275 hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
1276 return HAL_ERROR;
1277 }
1278
1279 /* Return function status */
1280 return HAL_OK;
1281 }
1282
1283 /**
1284 * @brief Encryption in interrupt mode.
1285 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
1286 * the configuration information for CRYP module
1287 * @param Input: Pointer to the input buffer (plaintext)
1288 * @param Size: Length of the plaintext buffer in word
1289 * @param Output: Pointer to the output buffer(ciphertext)
1290 * @retval HAL status
1291 */
HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef * hcryp,uint32_t * Input,uint16_t Size,uint32_t * Output)1292 HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
1293 {
1294 uint32_t algo;
1295 HAL_StatusTypeDef status = HAL_OK;
1296
1297 if (hcryp->State == HAL_CRYP_STATE_READY)
1298 {
1299 /* Change state Busy */
1300 hcryp->State = HAL_CRYP_STATE_BUSY;
1301
1302 /* Process locked */
1303 __HAL_LOCK(hcryp);
1304
1305 /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/
1306 hcryp->CrypInCount = 0U;
1307 hcryp->CrypOutCount = 0U;
1308 hcryp->pCrypInBuffPtr = Input;
1309 hcryp->pCrypOutBuffPtr = Output;
1310
1311 /* Calculate Size parameter in Byte*/
1312 if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
1313 {
1314 hcryp->Size = Size * 4U;
1315 }
1316 else
1317 {
1318 hcryp->Size = Size;
1319 }
1320
1321 #if defined (CRYP)
1322
1323 /* Set encryption operating mode*/
1324 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_ENCRYPT);
1325
1326 /* algo get algorithm selected */
1327 algo = (hcryp->Instance->CR & CRYP_CR_ALGOMODE);
1328
1329 switch (algo)
1330 {
1331 case CRYP_DES_ECB:
1332 case CRYP_DES_CBC:
1333 case CRYP_TDES_ECB:
1334 case CRYP_TDES_CBC:
1335
1336 /*Set Key */
1337 hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey);
1338 hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1);
1339 if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
1340 {
1341 hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2);
1342 hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 3);
1343 hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 4);
1344 hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 5);
1345 }
1346 /* Set the Initialization Vector*/
1347 if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
1348 {
1349 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
1350 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
1351 }
1352
1353 /* Flush FIFO */
1354 HAL_CRYP_FIFO_FLUSH(hcryp);
1355
1356 /* Set the phase */
1357 hcryp->Phase = CRYP_PHASE_PROCESS;
1358
1359 /* Enable interrupts */
1360 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
1361
1362 /* Enable CRYP to start DES/TDES process*/
1363 __HAL_CRYP_ENABLE(hcryp);
1364 break;
1365
1366 case CRYP_AES_ECB:
1367 case CRYP_AES_CBC:
1368 case CRYP_AES_CTR:
1369
1370 status = CRYP_AES_Encrypt_IT(hcryp);
1371 break;
1372
1373 case CRYP_AES_GCM:
1374
1375 status = CRYP_AESGCM_Process_IT(hcryp) ;
1376 break;
1377
1378 case CRYP_AES_CCM:
1379
1380 status = CRYP_AESCCM_Process_IT(hcryp);
1381 break;
1382
1383 default:
1384 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
1385 /* Change the CRYP peripheral state */
1386 hcryp->State = HAL_CRYP_STATE_READY;
1387 /* Process unlocked */
1388 __HAL_UNLOCK(hcryp);
1389 status = HAL_ERROR;
1390 break;
1391 }
1392
1393 #else /* AES */
1394
1395 /* Set encryption operating mode*/
1396 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
1397
1398 /* algo get algorithm selected */
1399 algo = hcryp->Instance->CR & AES_CR_CHMOD;
1400
1401 switch (algo)
1402 {
1403 case CRYP_AES_ECB:
1404 case CRYP_AES_CBC:
1405 case CRYP_AES_CTR:
1406
1407 /* AES encryption */
1408 status = CRYP_AES_Encrypt_IT(hcryp);
1409 break;
1410
1411 case CRYP_AES_GCM_GMAC:
1412
1413 /* AES GCM encryption */
1414 status = CRYP_AESGCM_Process_IT(hcryp) ;
1415 break;
1416
1417 case CRYP_AES_CCM:
1418
1419 /* AES CCM encryption */
1420 status = CRYP_AESCCM_Process_IT(hcryp);
1421 break;
1422
1423 default:
1424 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
1425 /* Change the CRYP peripheral state */
1426 hcryp->State = HAL_CRYP_STATE_READY;
1427 /* Process unlocked */
1428 __HAL_UNLOCK(hcryp);
1429 status = HAL_ERROR;
1430 break;
1431 }
1432 #endif /*end AES or CRYP*/
1433
1434 }
1435 else
1436 {
1437 /* Busy error code field */
1438 hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
1439 status = HAL_ERROR;
1440 }
1441
1442 /* Return function status */
1443 return status;
1444 }
1445
1446 /**
1447 * @brief Decryption in itnterrupt mode.
1448 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
1449 * the configuration information for CRYP module
1450 * @param Input: Pointer to the input buffer (ciphertext )
1451 * @param Size: Length of the plaintext buffer in word.
1452 * @param Output: Pointer to the output buffer(plaintext)
1453 * @retval HAL status
1454 */
HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef * hcryp,uint32_t * Input,uint16_t Size,uint32_t * Output)1455 HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
1456 {
1457 uint32_t algo;
1458 HAL_StatusTypeDef status = HAL_OK;
1459
1460 if (hcryp->State == HAL_CRYP_STATE_READY)
1461 {
1462 /* Change state Busy */
1463 hcryp->State = HAL_CRYP_STATE_BUSY;
1464
1465 /* Process locked */
1466 __HAL_LOCK(hcryp);
1467
1468 /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/
1469 hcryp->CrypInCount = 0U;
1470 hcryp->CrypOutCount = 0U;
1471 hcryp->pCrypInBuffPtr = Input;
1472 hcryp->pCrypOutBuffPtr = Output;
1473
1474 /* Calculate Size parameter in Byte*/
1475 if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
1476 {
1477 hcryp->Size = Size * 4U;
1478 }
1479 else
1480 {
1481 hcryp->Size = Size;
1482 }
1483
1484 #if defined (CRYP)
1485
1486 /* Set decryption operating mode*/
1487 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_DECRYPT);
1488
1489 /* algo get algorithm selected */
1490 algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE;
1491
1492 switch (algo)
1493 {
1494 case CRYP_DES_ECB:
1495 case CRYP_DES_CBC:
1496 case CRYP_TDES_ECB:
1497 case CRYP_TDES_CBC:
1498
1499 /*Set Key */
1500 hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey);
1501 hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1);
1502 if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
1503 {
1504 hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2);
1505 hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 3);
1506 hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 4);
1507 hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 5);
1508 }
1509
1510 /* Set the Initialization Vector*/
1511 if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
1512 {
1513 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
1514 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
1515 }
1516 /* Flush FIFO */
1517 HAL_CRYP_FIFO_FLUSH(hcryp);
1518
1519 /* Set the phase */
1520 hcryp->Phase = CRYP_PHASE_PROCESS;
1521
1522 /* Enable interrupts */
1523 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
1524
1525 /* Enable CRYP and start DES/TDES process*/
1526 __HAL_CRYP_ENABLE(hcryp);
1527
1528 break;
1529
1530 case CRYP_AES_ECB:
1531 case CRYP_AES_CBC:
1532 case CRYP_AES_CTR:
1533
1534 /* AES decryption */
1535 status = CRYP_AES_Decrypt_IT(hcryp);
1536 break;
1537
1538 case CRYP_AES_GCM:
1539
1540 /* AES GCM decryption */
1541 status = CRYP_AESGCM_Process_IT(hcryp) ;
1542 break;
1543
1544 case CRYP_AES_CCM:
1545
1546 /* AES CCMdecryption */
1547 status = CRYP_AESCCM_Process_IT(hcryp);
1548 break;
1549
1550 default:
1551 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
1552 /* Change the CRYP peripheral state */
1553 hcryp->State = HAL_CRYP_STATE_READY;
1554 /* Process unlocked */
1555 __HAL_UNLOCK(hcryp);
1556 status = HAL_ERROR;
1557 break;
1558 }
1559
1560 #else /*AES*/
1561
1562 /* Set decryption operating mode*/
1563 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
1564
1565 /* algo get algorithm selected */
1566 algo = hcryp->Instance->CR & AES_CR_CHMOD;
1567
1568 switch (algo)
1569 {
1570 case CRYP_AES_ECB:
1571 case CRYP_AES_CBC:
1572 case CRYP_AES_CTR:
1573
1574 /* AES decryption */
1575 status = CRYP_AES_Decrypt_IT(hcryp);
1576 break;
1577
1578 case CRYP_AES_GCM_GMAC:
1579
1580 /* AES GCM decryption */
1581 status = CRYP_AESGCM_Process_IT(hcryp) ;
1582 break;
1583
1584 case CRYP_AES_CCM:
1585
1586 /* AES CCM decryption */
1587 status = CRYP_AESCCM_Process_IT(hcryp);
1588 break;
1589
1590 default:
1591 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
1592 /* Change the CRYP peripheral state */
1593 hcryp->State = HAL_CRYP_STATE_READY;
1594 /* Process unlocked */
1595 __HAL_UNLOCK(hcryp);
1596 status = HAL_ERROR;
1597 break;
1598 }
1599 #endif /* End AES or CRYP */
1600
1601 }
1602 else
1603 {
1604 /* Busy error code field */
1605 hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
1606 status = HAL_ERROR;
1607 }
1608
1609 /* Return function status */
1610 return status;
1611 }
1612
1613 /**
1614 * @brief Encryption in DMA mode.
1615 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
1616 * the configuration information for CRYP module
1617 * @param Input: Pointer to the input buffer (plaintext)
1618 * @param Size: Length of the plaintext buffer in word.
1619 * @param Output: Pointer to the output buffer(ciphertext)
1620 * @retval HAL status
1621 */
HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef * hcryp,uint32_t * Input,uint16_t Size,uint32_t * Output)1622 HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
1623 {
1624 uint32_t algo;
1625 HAL_StatusTypeDef status = HAL_OK;
1626 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
1627
1628 if (hcryp->State == HAL_CRYP_STATE_READY)
1629 {
1630 /* Change state Busy */
1631 hcryp->State = HAL_CRYP_STATE_BUSY;
1632
1633 /* Process locked */
1634 __HAL_LOCK(hcryp);
1635
1636 /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr and pCrypOutBuffPtr parameters*/
1637 hcryp->CrypInCount = 0U;
1638 hcryp->CrypOutCount = 0U;
1639 hcryp->pCrypInBuffPtr = Input;
1640 hcryp->pCrypOutBuffPtr = Output;
1641
1642 /* Calculate Size parameter in Byte*/
1643 if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
1644 {
1645 hcryp->Size = Size * 4U;
1646 }
1647 else
1648 {
1649 hcryp->Size = Size;
1650 }
1651
1652 #if defined (CRYP)
1653
1654 /* Set encryption operating mode*/
1655 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_ENCRYPT);
1656
1657 /* algo get algorithm selected */
1658 algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE;
1659
1660 switch (algo)
1661 {
1662 case CRYP_DES_ECB:
1663 case CRYP_DES_CBC:
1664 case CRYP_TDES_ECB:
1665 case CRYP_TDES_CBC:
1666
1667 /*Set Key */
1668 hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey);
1669 hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1);
1670 if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
1671 {
1672 hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2);
1673 hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 3);
1674 hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 4);
1675 hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 5);
1676 }
1677
1678 /* Set the Initialization Vector*/
1679 if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
1680 {
1681 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
1682 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
1683 }
1684
1685 /* Flush FIFO */
1686 HAL_CRYP_FIFO_FLUSH(hcryp);
1687
1688 /* Set the phase */
1689 hcryp->Phase = CRYP_PHASE_PROCESS;
1690
1691 /* Start DMA process transfer for DES/TDES */
1692 CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), ((uint16_t)(hcryp->Size) / 4U),
1693 (uint32_t)(hcryp->pCrypOutBuffPtr));
1694 break;
1695
1696 case CRYP_AES_ECB:
1697 case CRYP_AES_CBC:
1698 case CRYP_AES_CTR:
1699
1700 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
1701 {
1702 if (hcryp->KeyIVConfig == 1U)
1703 {
1704 /* If the Key and IV configuration has to be done only once
1705 and if it has already been done, skip it */
1706 DoKeyIVConfig = 0U;
1707 }
1708 else
1709 {
1710 /* If the Key and IV configuration has to be done only once
1711 and if it has not been done already, do it and set KeyIVConfig
1712 to keep track it won't have to be done again next time */
1713 hcryp->KeyIVConfig = 1U;
1714 }
1715 }
1716
1717 if (DoKeyIVConfig == 1U)
1718 {
1719 /* Set the Key*/
1720 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
1721
1722 /* Set the Initialization Vector*/
1723 if (hcryp->Init.Algorithm != CRYP_AES_ECB)
1724 {
1725 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
1726 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1U);
1727 hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2U);
1728 hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3U);
1729 }
1730 } /* if (DoKeyIVConfig == 1U) */
1731
1732 /* Set the phase */
1733 hcryp->Phase = CRYP_PHASE_PROCESS;
1734
1735 /* Start DMA process transfer for AES */
1736 CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), ((uint16_t)(hcryp->Size) / 4U),
1737 (uint32_t)(hcryp->pCrypOutBuffPtr));
1738 break;
1739
1740 case CRYP_AES_GCM:
1741 /* AES GCM encryption */
1742 status = CRYP_AESGCM_Process_DMA(hcryp) ;
1743 break;
1744
1745 case CRYP_AES_CCM:
1746 /* AES CCM encryption */
1747 status = CRYP_AESCCM_Process_DMA(hcryp);
1748 break;
1749
1750 default:
1751 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
1752 /* Change the CRYP peripheral state */
1753 hcryp->State = HAL_CRYP_STATE_READY;
1754 /* Process unlocked */
1755 __HAL_UNLOCK(hcryp);
1756 status = HAL_ERROR;
1757 break;
1758 }
1759
1760 #else /*AES*/
1761 /* Set encryption operating mode*/
1762 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
1763
1764 /* algo get algorithm selected */
1765 algo = hcryp->Instance->CR & AES_CR_CHMOD;
1766
1767 switch (algo)
1768 {
1769
1770 case CRYP_AES_ECB:
1771 case CRYP_AES_CBC:
1772 case CRYP_AES_CTR:
1773
1774 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
1775 {
1776 if (hcryp->KeyIVConfig == 1U)
1777 {
1778 /* If the Key and IV configuration has to be done only once
1779 and if it has already been done, skip it */
1780 DoKeyIVConfig = 0U;
1781 }
1782 else
1783 {
1784 /* If the Key and IV configuration has to be done only once
1785 and if it has not been done already, do it and set KeyIVConfig
1786 to keep track it won't have to be done again next time */
1787 hcryp->KeyIVConfig = 1U;
1788 }
1789 }
1790
1791 if (DoKeyIVConfig == 1U)
1792 {
1793 /* Set the Key*/
1794 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
1795
1796 /* Set the Initialization Vector*/
1797 if (hcryp->Init.Algorithm != CRYP_AES_ECB)
1798 {
1799 hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
1800 hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1);
1801 hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2);
1802 hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3);
1803 }
1804 } /* if (DoKeyIVConfig == 1U) */
1805 /* Set the phase */
1806 hcryp->Phase = CRYP_PHASE_PROCESS;
1807
1808 /* Start DMA process transfer for AES */
1809 CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size / 4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
1810 break;
1811
1812 case CRYP_AES_GCM_GMAC:
1813 /* AES GCM encryption */
1814 status = CRYP_AESGCM_Process_DMA(hcryp) ;
1815 break;
1816
1817 case CRYP_AES_CCM:
1818 /* AES CCM encryption */
1819 status = CRYP_AESCCM_Process_DMA(hcryp);
1820 break;
1821
1822 default:
1823 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
1824 /* Change the CRYP peripheral state */
1825 hcryp->State = HAL_CRYP_STATE_READY;
1826 /* Process unlocked */
1827 __HAL_UNLOCK(hcryp);
1828 status = HAL_ERROR;
1829 break;
1830 }
1831 #endif /* End AES or CRYP */
1832
1833 }
1834 else
1835 {
1836 /* Busy error code field */
1837 hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
1838 status = HAL_ERROR;
1839 }
1840
1841 /* Return function status */
1842 return status;
1843 }
1844
1845 /**
1846 * @brief Decryption in DMA mode.
1847 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
1848 * the configuration information for CRYP module
1849 * @param Input: Pointer to the input buffer (ciphertext )
1850 * @param Size: Length of the plaintext buffer in word
1851 * @param Output: Pointer to the output buffer(plaintext)
1852 * @retval HAL status
1853 */
HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef * hcryp,uint32_t * Input,uint16_t Size,uint32_t * Output)1854 HAL_StatusTypeDef HAL_CRYP_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output)
1855 {
1856 uint32_t algo;
1857 HAL_StatusTypeDef status = HAL_OK;
1858
1859 if (hcryp->State == HAL_CRYP_STATE_READY)
1860 {
1861
1862 /* Change state Busy */
1863 hcryp->State = HAL_CRYP_STATE_BUSY;
1864
1865 /* Process locked */
1866 __HAL_LOCK(hcryp);
1867
1868 /* Reset CrypInCount, CrypOutCount and Initialize pCrypInBuffPtr, pCrypOutBuffPtr and Size parameters*/
1869 hcryp->CrypInCount = 0U;
1870 hcryp->CrypOutCount = 0U;
1871 hcryp->pCrypInBuffPtr = Input;
1872 hcryp->pCrypOutBuffPtr = Output;
1873
1874 /* Calculate Size parameter in Byte*/
1875 if (hcryp->Init.DataWidthUnit == CRYP_DATAWIDTHUNIT_WORD)
1876 {
1877 hcryp->Size = Size * 4U;
1878 }
1879 else
1880 {
1881 hcryp->Size = Size;
1882 }
1883
1884 #if defined (CRYP)
1885
1886 /* Set decryption operating mode*/
1887 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGODIR, CRYP_OPERATINGMODE_DECRYPT);
1888
1889 /* algo get algorithm selected */
1890 algo = hcryp->Instance->CR & CRYP_CR_ALGOMODE;
1891
1892 switch (algo)
1893 {
1894 case CRYP_DES_ECB:
1895 case CRYP_DES_CBC:
1896 case CRYP_TDES_ECB:
1897 case CRYP_TDES_CBC:
1898
1899 /*Set Key */
1900 hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey);
1901 hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1);
1902 if ((hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
1903 {
1904 hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2);
1905 hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 3);
1906 hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 4);
1907 hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 5);
1908 }
1909
1910 /* Set the Initialization Vector*/
1911 if ((hcryp->Init.Algorithm == CRYP_DES_CBC) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
1912 {
1913 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
1914 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
1915 }
1916
1917 /* Flush FIFO */
1918 HAL_CRYP_FIFO_FLUSH(hcryp);
1919
1920 /* Set the phase */
1921 hcryp->Phase = CRYP_PHASE_PROCESS;
1922
1923 /* Start DMA process transfer for DES/TDES */
1924 CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), ((uint16_t)(hcryp->Size) / 4U),
1925 (uint32_t)(hcryp->pCrypOutBuffPtr));
1926 break;
1927
1928 case CRYP_AES_ECB:
1929 case CRYP_AES_CBC:
1930 case CRYP_AES_CTR:
1931
1932 /* AES decryption */
1933 status = CRYP_AES_Decrypt_DMA(hcryp);
1934 break;
1935
1936 case CRYP_AES_GCM:
1937 /* AES GCM decryption */
1938 status = CRYP_AESGCM_Process_DMA(hcryp) ;
1939 break;
1940
1941 case CRYP_AES_CCM:
1942 /* AES CCM decryption */
1943 status = CRYP_AESCCM_Process_DMA(hcryp);
1944 break;
1945
1946 default:
1947 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
1948 /* Change the CRYP peripheral state */
1949 hcryp->State = HAL_CRYP_STATE_READY;
1950 /* Process unlocked */
1951 __HAL_UNLOCK(hcryp);
1952 status = HAL_ERROR;
1953 break;
1954 }
1955
1956 #else /*AES*/
1957
1958 /* Set decryption operating mode*/
1959 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
1960
1961 /* algo get algorithm selected */
1962 algo = hcryp->Instance->CR & AES_CR_CHMOD;
1963
1964 switch (algo)
1965 {
1966
1967 case CRYP_AES_ECB:
1968 case CRYP_AES_CBC:
1969 case CRYP_AES_CTR:
1970
1971 /* AES decryption */
1972 status = CRYP_AES_Decrypt_DMA(hcryp);
1973 break;
1974
1975 case CRYP_AES_GCM_GMAC:
1976 /* AES GCM decryption */
1977 status = CRYP_AESGCM_Process_DMA(hcryp) ;
1978 break;
1979
1980 case CRYP_AES_CCM:
1981 /* AES CCM decryption */
1982 status = CRYP_AESCCM_Process_DMA(hcryp);
1983 break;
1984
1985 default:
1986 hcryp->ErrorCode |= HAL_CRYP_ERROR_NOT_SUPPORTED;
1987 /* Change the CRYP peripheral state */
1988 hcryp->State = HAL_CRYP_STATE_READY;
1989 /* Process unlocked */
1990 __HAL_UNLOCK(hcryp);
1991 status = HAL_ERROR;
1992 break;
1993 }
1994 #endif /* End AES or CRYP */
1995 }
1996 else
1997 {
1998 /* Busy error code field */
1999 hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
2000 status = HAL_ERROR;
2001 }
2002
2003 /* Return function status */
2004 return status;
2005 }
2006
2007 /**
2008 * @}
2009 */
2010
2011 /** @defgroup CRYP_Exported_Functions_Group3 CRYP IRQ handler management
2012 * @brief CRYP IRQ handler.
2013 *
2014 @verbatim
2015 ==============================================================================
2016 ##### CRYP IRQ handler management #####
2017 ==============================================================================
2018 [..] This section provides CRYP IRQ handler and callback functions.
2019 (+) HAL_CRYP_IRQHandler CRYP interrupt request
2020 (+) HAL_CRYP_InCpltCallback input data transfer complete callback
2021 (+) HAL_CRYP_OutCpltCallback output data transfer complete callback
2022 (+) HAL_CRYP_ErrorCallback CRYP error callback
2023 (+) HAL_CRYP_GetState return the CRYP state
2024 (+) HAL_CRYP_GetError return the CRYP error code
2025 @endverbatim
2026 * @{
2027 */
2028
2029 /**
2030 * @brief This function handles cryptographic interrupt request.
2031 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
2032 * the configuration information for CRYP module
2033 * @retval None
2034 */
HAL_CRYP_IRQHandler(CRYP_HandleTypeDef * hcryp)2035 void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp)
2036 {
2037
2038 #if defined (CRYP)
2039
2040 uint32_t itstatus = hcryp->Instance->MISR;
2041
2042 if ((itstatus & (CRYP_IT_INI | CRYP_IT_OUTI)) != 0U)
2043 {
2044 if ((hcryp->Init.Algorithm == CRYP_DES_ECB) || (hcryp->Init.Algorithm == CRYP_DES_CBC)
2045 || (hcryp->Init.Algorithm == CRYP_TDES_ECB) || (hcryp->Init.Algorithm == CRYP_TDES_CBC))
2046 {
2047 CRYP_TDES_IT(hcryp); /* DES or TDES*/
2048 }
2049 else if ((hcryp->Init.Algorithm == CRYP_AES_ECB) || (hcryp->Init.Algorithm == CRYP_AES_CBC)
2050 || (hcryp->Init.Algorithm == CRYP_AES_CTR))
2051 {
2052 CRYP_AES_IT(hcryp); /*AES*/
2053 }
2054
2055 else if ((hcryp->Init.Algorithm == CRYP_AES_GCM) || (hcryp->Init.Algorithm == CRYP_CR_ALGOMODE_AES_CCM))
2056 {
2057 /* if header phase */
2058 if ((hcryp->Instance->CR & CRYP_PHASE_HEADER) == CRYP_PHASE_HEADER)
2059 {
2060 CRYP_GCMCCM_SetHeaderPhase_IT(hcryp);
2061 }
2062 else /* if payload phase */
2063 {
2064 CRYP_GCMCCM_SetPayloadPhase_IT(hcryp);
2065 }
2066 }
2067
2068 else
2069 {
2070 /* Nothing to do */
2071 }
2072 }
2073
2074 #else /*AES*/
2075 if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_IT_CCF) != RESET)
2076 {
2077 if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_CCFIE) != RESET)
2078 {
2079
2080 /* Clear computation complete flag */
2081 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
2082
2083 if (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)
2084 {
2085
2086 /* if header phase */
2087 if ((hcryp->Instance->CR & CRYP_PHASE_HEADER) == CRYP_PHASE_HEADER)
2088 {
2089 CRYP_GCMCCM_SetHeaderPhase_IT(hcryp);
2090 }
2091 else /* if payload phase */
2092 {
2093 CRYP_GCMCCM_SetPayloadPhase_IT(hcryp);
2094 }
2095 }
2096 else if (hcryp->Init.Algorithm == CRYP_AES_CCM)
2097 {
2098 /* if header phase */
2099 if (hcryp->Init.HeaderSize >= hcryp->CrypHeaderCount)
2100 {
2101 CRYP_GCMCCM_SetHeaderPhase_IT(hcryp);
2102 }
2103 else /* if payload phase */
2104 {
2105 CRYP_GCMCCM_SetPayloadPhase_IT(hcryp);
2106 }
2107 }
2108 else /* AES Algorithm ECB,CBC or CTR*/
2109 {
2110 CRYP_AES_IT(hcryp);
2111 }
2112 }
2113 }
2114 /* Check if error occurred */
2115 if (__HAL_CRYP_GET_IT_SOURCE(hcryp, CRYP_IT_ERRIE) != RESET)
2116 {
2117 /* If write Error occurred */
2118 if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_IT_WRERR) != RESET)
2119 {
2120 hcryp->ErrorCode |= HAL_CRYP_ERROR_WRITE;
2121 }
2122 /* If read Error occurred */
2123 if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_IT_RDERR) != RESET)
2124 {
2125 hcryp->ErrorCode |= HAL_CRYP_ERROR_READ;
2126 }
2127 }
2128 #endif /* End AES or CRYP */
2129 }
2130
2131 /**
2132 * @brief Return the CRYP error code.
2133 * @param hcryp : pointer to a CRYP_HandleTypeDef structure that contains
2134 * the configuration information for the CRYP IP
2135 * @retval CRYP error code
2136 */
HAL_CRYP_GetError(CRYP_HandleTypeDef * hcryp)2137 uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp)
2138 {
2139 return hcryp->ErrorCode;
2140 }
2141
2142 /**
2143 * @brief Returns the CRYP state.
2144 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
2145 * the configuration information for CRYP module.
2146 * @retval HAL state
2147 */
HAL_CRYP_GetState(CRYP_HandleTypeDef * hcryp)2148 HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp)
2149 {
2150 return hcryp->State;
2151 }
2152
2153 /**
2154 * @brief Input FIFO transfer completed callback.
2155 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
2156 * the configuration information for CRYP module.
2157 * @retval None
2158 */
HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef * hcryp)2159 __weak void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp)
2160 {
2161 /* Prevent unused argument(s) compilation warning */
2162 UNUSED(hcryp);
2163
2164 /* NOTE : This function should not be modified, when the callback is needed,
2165 the HAL_CRYP_InCpltCallback can be implemented in the user file
2166 */
2167 }
2168
2169 /**
2170 * @brief Output FIFO transfer completed callback.
2171 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
2172 * the configuration information for CRYP module.
2173 * @retval None
2174 */
HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef * hcryp)2175 __weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp)
2176 {
2177 /* Prevent unused argument(s) compilation warning */
2178 UNUSED(hcryp);
2179
2180 /* NOTE : This function should not be modified, when the callback is needed,
2181 the HAL_CRYP_OutCpltCallback can be implemented in the user file
2182 */
2183 }
2184
2185 /**
2186 * @brief CRYP error callback.
2187 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
2188 * the configuration information for CRYP module.
2189 * @retval None
2190 */
HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef * hcryp)2191 __weak void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp)
2192 {
2193 /* Prevent unused argument(s) compilation warning */
2194 UNUSED(hcryp);
2195
2196 /* NOTE : This function Should not be modified, when the callback is needed,
2197 the HAL_CRYP_ErrorCallback could be implemented in the user file
2198 */
2199 }
2200 /**
2201 * @}
2202 */
2203
2204 /* Private functions ---------------------------------------------------------*/
2205 /** @addtogroup CRYP_Private_Functions
2206 * @{
2207 */
2208
2209 #if defined (CRYP)
2210
2211 /**
2212 * @brief Encryption in ECB/CBC Algorithm with DES/TDES standard.
2213 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
2214 * the configuration information for CRYP module
2215 * @param Timeout: specify Timeout value
2216 * @retval HAL status
2217 */
CRYP_TDES_Process(CRYP_HandleTypeDef * hcryp,uint32_t Timeout)2218 static HAL_StatusTypeDef CRYP_TDES_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
2219 {
2220 uint32_t temp[2]; /* Temporary CrypOutBuff */
2221 uint16_t incount; /* Temporary CrypInCount Value */
2222 uint16_t outcount; /* Temporary CrypOutCount Value */
2223 uint32_t i;
2224
2225 /* Enable CRYP */
2226 __HAL_CRYP_ENABLE(hcryp);
2227 /*Temporary CrypOutCount Value*/
2228 outcount = hcryp->CrypOutCount;
2229
2230 /*Start processing*/
2231 while ((hcryp->CrypInCount < (hcryp->Size / 4U)) && (outcount < (hcryp->Size / 4U)))
2232 {
2233 /* Temporary CrypInCount Value */
2234 incount = hcryp->CrypInCount;
2235 /* Write plain data and get cipher data */
2236 if (((hcryp->Instance->SR & CRYP_FLAG_IFNF) != 0x0U) && (incount < (hcryp->Size / 4U)))
2237 {
2238 /* Write the input block in the IN FIFO */
2239 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
2240 hcryp->CrypInCount++;
2241 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
2242 hcryp->CrypInCount++;
2243 }
2244
2245 /* Wait for OFNE flag to be raised */
2246 if (CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
2247 {
2248 /* Disable the CRYP peripheral clock */
2249 __HAL_CRYP_DISABLE(hcryp);
2250
2251 /* Change state & errorCode*/
2252 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
2253 hcryp->State = HAL_CRYP_STATE_READY;
2254
2255 /* Process unlocked */
2256 __HAL_UNLOCK(hcryp);
2257 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
2258 /*Call registered error callback*/
2259 hcryp->ErrorCallback(hcryp);
2260 #else
2261 /*Call legacy weak error callback*/
2262 HAL_CRYP_ErrorCallback(hcryp);
2263 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
2264 }
2265
2266 /*Temporary CrypOutCount Value*/
2267 outcount = hcryp->CrypOutCount;
2268
2269 if (((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U) && (outcount < (hcryp->Size / 4U)))
2270 {
2271 /* Read the output block from the Output FIFO and put them in temporary Buffer then get CrypOutBuff from temporary buffer */
2272 for (i = 0U; i < 2U; i++)
2273 {
2274 temp[i] = hcryp->Instance->DOUT;
2275 }
2276 i = 0U;
2277 while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 2U))
2278 {
2279 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
2280 hcryp->CrypOutCount++;
2281 i++;
2282 }
2283 }
2284 /*Temporary CrypOutCount Value*/
2285 outcount = hcryp->CrypOutCount;
2286 }
2287 /* Disable CRYP */
2288 __HAL_CRYP_DISABLE(hcryp);
2289 /* Change the CRYP state */
2290 hcryp->State = HAL_CRYP_STATE_READY;
2291
2292 /* Return function status */
2293 return HAL_OK;
2294 }
2295
2296 /**
2297 * @brief CRYP block input/output data handling under interruption with DES/TDES standard.
2298 * @note The function is called under interruption only, once
2299 * interruptions have been enabled by CRYP_Decrypt_IT() and CRYP_Encrypt_IT().
2300 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
2301 * the configuration information for CRYP module.
2302 * @retval none
2303 */
CRYP_TDES_IT(CRYP_HandleTypeDef * hcryp)2304 static void CRYP_TDES_IT(CRYP_HandleTypeDef *hcryp)
2305 {
2306 uint32_t temp[2]; /* Temporary CrypOutBuff */
2307 uint32_t i;
2308
2309 if (hcryp->State == HAL_CRYP_STATE_BUSY)
2310 {
2311 if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_INI) != 0x0U)
2312 {
2313 if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_INRIS) != 0x0U)
2314 {
2315 /* Write input block in the IN FIFO */
2316 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
2317 hcryp->CrypInCount++;
2318 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
2319 hcryp->CrypInCount++;
2320
2321 if (hcryp->CrypInCount == ((uint16_t)(hcryp->Size) / 4U))
2322 {
2323 /* Disable interruption */
2324 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
2325 /* Call the input data transfer complete callback */
2326 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
2327 /*Call registered Input complete callback*/
2328 hcryp->InCpltCallback(hcryp);
2329 #else
2330 /*Call legacy weak Input complete callback*/
2331 HAL_CRYP_InCpltCallback(hcryp);
2332 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
2333 }
2334 }
2335 }
2336 if (__HAL_CRYP_GET_IT(hcryp, CRYP_IT_OUTI) != 0x0U)
2337 {
2338 if (__HAL_CRYP_GET_FLAG(hcryp, CRYP_FLAG_OUTRIS) != 0x0U)
2339 {
2340 /* Read the output block from the Output FIFO and put them in temporary Buffer then get CrypOutBuff from temporary buffer */
2341 for (i = 0U; i < 2U; i++)
2342 {
2343 temp[i] = hcryp->Instance->DOUT;
2344 }
2345 i = 0U;
2346 while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 2U))
2347 {
2348 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
2349 hcryp->CrypOutCount++;
2350 i++;
2351 }
2352 if (hcryp->CrypOutCount == ((uint16_t)(hcryp->Size) / 4U))
2353 {
2354 /* Disable interruption */
2355 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
2356
2357 /* Disable CRYP */
2358 __HAL_CRYP_DISABLE(hcryp);
2359
2360 /* Process unlocked */
2361 __HAL_UNLOCK(hcryp);
2362
2363 /* Change the CRYP state */
2364 hcryp->State = HAL_CRYP_STATE_READY;
2365 /* Call output transfer complete callback */
2366 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
2367 /*Call registered Output complete callback*/
2368 hcryp->OutCpltCallback(hcryp);
2369 #else
2370 /*Call legacy weak Output complete callback*/
2371 HAL_CRYP_OutCpltCallback(hcryp);
2372 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
2373 }
2374 }
2375 }
2376 }
2377 else
2378 {
2379 /* Process unlocked */
2380 __HAL_UNLOCK(hcryp);
2381 /* Busy error code field */
2382 hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
2383 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
2384 /*Call registered error callback*/
2385 hcryp->ErrorCallback(hcryp);
2386 #else
2387 /*Call legacy weak error callback*/
2388 HAL_CRYP_ErrorCallback(hcryp);
2389 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
2390 }
2391 }
2392
2393 #endif /* CRYP */
2394
2395 /**
2396 * @brief Encryption in ECB/CBC & CTR Algorithm with AES Standard
2397 * @param hcryp: pointer to a CRYP_HandleTypeDef structure
2398 * @param Timeout: specify Timeout value
2399 * @retval HAL status
2400 */
CRYP_AES_Encrypt(CRYP_HandleTypeDef * hcryp,uint32_t Timeout)2401 static HAL_StatusTypeDef CRYP_AES_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
2402 {
2403 uint16_t outcount; /* Temporary CrypOutCount Value */
2404 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
2405
2406 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
2407 {
2408 if (hcryp->KeyIVConfig == 1U)
2409 {
2410 /* If the Key and IV configuration has to be done only once
2411 and if it has already been done, skip it */
2412 DoKeyIVConfig = 0U;
2413 }
2414 else
2415 {
2416 /* If the Key and IV configuration has to be done only once
2417 and if it has not been done already, do it and set KeyIVConfig
2418 to keep track it won't have to be done again next time */
2419 hcryp->KeyIVConfig = 1U;
2420 }
2421 }
2422
2423 if (DoKeyIVConfig == 1U)
2424 {
2425
2426 /* Set the Key*/
2427 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2428
2429 if (hcryp->Init.Algorithm != CRYP_AES_ECB)
2430 {
2431 /* Set the Initialization Vector*/
2432 #if defined (AES)
2433 hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
2434 hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1);
2435 hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2);
2436 hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3);
2437 #else /* CRYP */
2438 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
2439 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
2440 hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
2441 hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
2442 #endif /* End AES or CRYP */
2443 }
2444 } /* if (DoKeyIVConfig == 1U) */
2445
2446 /* Set the phase */
2447 hcryp->Phase = CRYP_PHASE_PROCESS;
2448
2449 /* Enable CRYP */
2450 __HAL_CRYP_ENABLE(hcryp);
2451
2452 /*Temporary CrypOutCount Value*/
2453 outcount = hcryp->CrypOutCount;
2454
2455 while ((hcryp->CrypInCount < (hcryp->Size / 4U)) && (outcount < (hcryp->Size / 4U)))
2456 {
2457 /* Write plain Ddta and get cipher data */
2458 CRYP_AES_ProcessData(hcryp, Timeout);
2459 /*Temporary CrypOutCount Value*/
2460 outcount = hcryp->CrypOutCount;
2461 }
2462
2463 /* Disable CRYP */
2464 __HAL_CRYP_DISABLE(hcryp);
2465
2466 /* Change the CRYP state */
2467 hcryp->State = HAL_CRYP_STATE_READY;
2468
2469 /* Return function status */
2470 return HAL_OK;
2471 }
2472
2473 /**
2474 * @brief Encryption in ECB/CBC & CTR mode with AES Standard using interrupt mode
2475 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
2476 * the configuration information for CRYP module
2477 * @retval HAL status
2478 */
CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef * hcryp)2479 static HAL_StatusTypeDef CRYP_AES_Encrypt_IT(CRYP_HandleTypeDef *hcryp)
2480 {
2481 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
2482
2483 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
2484 {
2485 if (hcryp->KeyIVConfig == 1U)
2486 {
2487 /* If the Key and IV configuration has to be done only once
2488 and if it has already been done, skip it */
2489 DoKeyIVConfig = 0U;
2490 }
2491 else
2492 {
2493 /* If the Key and IV configuration has to be done only once
2494 and if it has not been done already, do it and set KeyIVConfig
2495 to keep track it won't have to be done again next time */
2496 hcryp->KeyIVConfig = 1U;
2497 }
2498 }
2499
2500 if (DoKeyIVConfig == 1U)
2501 {
2502 /* Set the Key*/
2503 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2504
2505 if (hcryp->Init.Algorithm != CRYP_AES_ECB)
2506 {
2507 /* Set the Initialization Vector*/
2508 #if defined (AES)
2509 hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
2510 hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1);
2511 hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2);
2512 hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3);
2513
2514 #else /* CRYP */
2515 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
2516 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
2517 hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
2518 hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
2519 #endif /* End AES or CRYP */
2520 }
2521 } /* if (DoKeyIVConfig == 1U) */
2522
2523 /* Set the phase */
2524 hcryp->Phase = CRYP_PHASE_PROCESS;
2525
2526 if (hcryp->Size != 0U)
2527 {
2528 #if defined (AES)
2529
2530 /* Enable computation complete flag and error interrupts */
2531 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
2532
2533 /* Enable CRYP */
2534 __HAL_CRYP_ENABLE(hcryp);
2535
2536 /* Write the input block in the IN FIFO */
2537 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
2538 hcryp->CrypInCount++;
2539 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
2540 hcryp->CrypInCount++;
2541 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
2542 hcryp->CrypInCount++;
2543 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
2544 hcryp->CrypInCount++;
2545
2546 #else /* CRYP */
2547
2548 /* Enable interrupts */
2549 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
2550
2551 /* Enable CRYP */
2552 __HAL_CRYP_ENABLE(hcryp);
2553
2554 #endif /* End AES or CRYP */
2555 }
2556 else
2557 {
2558 /* Change the CRYP state */
2559 hcryp->State = HAL_CRYP_STATE_READY;
2560
2561 /* Process unlocked */
2562 __HAL_UNLOCK(hcryp);
2563 }
2564
2565 /* Return function status */
2566 return HAL_OK;
2567 }
2568
2569 /**
2570 * @brief Decryption in ECB/CBC & CTR mode with AES Standard
2571 * @param hcryp: pointer to a CRYP_HandleTypeDef structure
2572 * @param Timeout: Specify Timeout value
2573 * @retval HAL status
2574 */
CRYP_AES_Decrypt(CRYP_HandleTypeDef * hcryp,uint32_t Timeout)2575 static HAL_StatusTypeDef CRYP_AES_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
2576 {
2577 uint16_t outcount; /* Temporary CrypOutCount Value */
2578 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
2579
2580 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
2581 {
2582 if (hcryp->KeyIVConfig == 1U)
2583 {
2584 /* If the Key and IV configuration has to be done only once
2585 and if it has already been done, skip it */
2586 DoKeyIVConfig = 0U;
2587 }
2588 else
2589 {
2590 /* If the Key and IV configuration has to be done only once
2591 and if it has not been done already, do it and set KeyIVConfig
2592 to keep track it won't have to be done again next time */
2593 hcryp->KeyIVConfig = 1U;
2594 }
2595 }
2596
2597 if (DoKeyIVConfig == 1U)
2598 {
2599 /* Key preparation for ECB/CBC */
2600 if (hcryp->Init.Algorithm != CRYP_AES_CTR)
2601 {
2602 #if defined (AES)
2603 if (hcryp->AutoKeyDerivation == DISABLE)/*Mode 2 Key preparation*/
2604 {
2605 /* Set key preparation for decryption operating mode*/
2606 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION);
2607
2608 /* Set the Key*/
2609 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2610
2611 /* Enable CRYP */
2612 __HAL_CRYP_ENABLE(hcryp);
2613
2614 /* Wait for CCF flag to be raised */
2615 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
2616 {
2617 /* Disable the CRYP peripheral clock */
2618 __HAL_CRYP_DISABLE(hcryp);
2619
2620 /* Change state & error code*/
2621 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
2622 hcryp->State = HAL_CRYP_STATE_READY;
2623
2624 /* Process unlocked */
2625 __HAL_UNLOCK(hcryp);
2626 return HAL_ERROR;
2627 }
2628 /* Clear CCF Flag */
2629 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
2630
2631 /* Return to decryption operating mode(Mode 3)*/
2632 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
2633 }
2634 else /*Mode 4 : decryption & Key preparation*/
2635 {
2636 /* Set the Key*/
2637 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2638
2639 /* Set decryption & Key preparation operating mode*/
2640 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT);
2641 }
2642 #else /* CRYP */
2643 /* change ALGOMODE to key preparation for decryption*/
2644 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_CR_ALGOMODE_AES_KEY);
2645
2646 /* Set the Key*/
2647 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2648
2649 /* Enable CRYP */
2650 __HAL_CRYP_ENABLE(hcryp);
2651
2652 /* Wait for BUSY flag to be raised */
2653 if (CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK)
2654 {
2655 /* Disable the CRYP peripheral clock */
2656 __HAL_CRYP_DISABLE(hcryp);
2657
2658 /* Change state */
2659 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
2660 hcryp->State = HAL_CRYP_STATE_READY;
2661
2662 /* Process unlocked */
2663 __HAL_UNLOCK(hcryp);
2664 return HAL_ERROR;
2665 }
2666 /* Turn back to ALGOMODE of the configuration */
2667 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm);
2668
2669 #endif /* End AES or CRYP */
2670 }
2671 else /*Algorithm CTR */
2672 {
2673 /* Set the Key*/
2674 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2675 }
2676
2677 /* Set IV */
2678 if (hcryp->Init.Algorithm != CRYP_AES_ECB)
2679 {
2680 /* Set the Initialization Vector*/
2681 #if defined (AES)
2682 hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
2683 hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1);
2684 hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2);
2685 hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3);
2686 #else /* CRYP */
2687 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
2688 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
2689 hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
2690 hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
2691 #endif /* End AES or CRYP */
2692 }
2693 } /* if (DoKeyIVConfig == 1U) */
2694 /* Set the phase */
2695 hcryp->Phase = CRYP_PHASE_PROCESS;
2696
2697 /* Enable CRYP */
2698 __HAL_CRYP_ENABLE(hcryp);
2699
2700 /*Temporary CrypOutCount Value*/
2701 outcount = hcryp->CrypOutCount;
2702
2703 while ((hcryp->CrypInCount < (hcryp->Size / 4U)) && (outcount < (hcryp->Size / 4U)))
2704 {
2705 /* Write plain data and get cipher data */
2706 CRYP_AES_ProcessData(hcryp, Timeout);
2707 /*Temporary CrypOutCount Value*/
2708 outcount = hcryp->CrypOutCount;
2709 }
2710
2711 /* Disable CRYP */
2712 __HAL_CRYP_DISABLE(hcryp);
2713
2714 /* Change the CRYP state */
2715 hcryp->State = HAL_CRYP_STATE_READY;
2716
2717 /* Return function status */
2718 return HAL_OK;
2719 }
2720 /**
2721 * @brief Decryption in ECB/CBC & CTR mode with AES Standard using interrupt mode
2722 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
2723 * the configuration information for CRYP module
2724 * @retval HAL status
2725 */
CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef * hcryp)2726 static HAL_StatusTypeDef CRYP_AES_Decrypt_IT(CRYP_HandleTypeDef *hcryp)
2727 {
2728 __IO uint32_t count = 0U;
2729 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
2730
2731 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
2732 {
2733 if (hcryp->KeyIVConfig == 1U)
2734 {
2735 /* If the Key and IV configuration has to be done only once
2736 and if it has already been done, skip it */
2737 DoKeyIVConfig = 0U;
2738 }
2739 else
2740 {
2741 /* If the Key and IV configuration has to be done only once
2742 and if it has not been done already, do it and set KeyIVConfig
2743 to keep track it won't have to be done again next time */
2744 hcryp->KeyIVConfig = 1U;
2745 }
2746 }
2747
2748 if (DoKeyIVConfig == 1U)
2749 {
2750 /* Key preparation for ECB/CBC */
2751 if (hcryp->Init.Algorithm != CRYP_AES_CTR)
2752 {
2753 #if defined (AES)
2754 if (hcryp->AutoKeyDerivation == DISABLE)/*Mode 2 Key preparation*/
2755 {
2756 /* Set key preparation for decryption operating mode*/
2757 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION);
2758
2759 /* Set the Key*/
2760 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2761
2762 /* Enable CRYP */
2763 __HAL_CRYP_ENABLE(hcryp);
2764
2765 /* Wait for CCF flag to be raised */
2766 count = CRYP_TIMEOUT_KEYPREPARATION;
2767 do
2768 {
2769 count-- ;
2770 if (count == 0U)
2771 {
2772 /* Disable the CRYP peripheral clock */
2773 __HAL_CRYP_DISABLE(hcryp);
2774
2775 /* Change state */
2776 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
2777 hcryp->State = HAL_CRYP_STATE_READY;
2778
2779 /* Process unlocked */
2780 __HAL_UNLOCK(hcryp);
2781 return HAL_ERROR;
2782 }
2783 } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
2784
2785 /* Clear CCF Flag */
2786 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
2787
2788 /* Return to decryption operating mode(Mode 3)*/
2789 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
2790 }
2791 else /*Mode 4 : decryption & key preparation*/
2792 {
2793 /* Set the Key*/
2794 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2795
2796 /* Set decryption & key preparation operating mode*/
2797 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT);
2798 }
2799 #else /* CRYP */
2800
2801 /* change ALGOMODE to key preparation for decryption*/
2802 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_CR_ALGOMODE_AES_KEY);
2803
2804 /* Set the Key*/
2805 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2806
2807 /* Enable CRYP */
2808 __HAL_CRYP_ENABLE(hcryp);
2809
2810 /* Wait for BUSY flag to be raised */
2811 count = CRYP_TIMEOUT_KEYPREPARATION;
2812 do
2813 {
2814 count-- ;
2815 if (count == 0U)
2816 {
2817 /* Change state */
2818 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
2819 hcryp->State = HAL_CRYP_STATE_READY;
2820
2821 /* Process unlocked */
2822 __HAL_UNLOCK(hcryp);
2823 return HAL_ERROR;
2824 }
2825 } while (HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY));
2826
2827 /* Turn back to ALGOMODE of the configuration */
2828 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm);
2829
2830 #endif /* End AES or CRYP */
2831 }
2832
2833 else /*Algorithm CTR */
2834 {
2835 /* Set the Key*/
2836 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2837 }
2838
2839 /* Set IV */
2840 if (hcryp->Init.Algorithm != CRYP_AES_ECB)
2841 {
2842 /* Set the Initialization Vector*/
2843 #if defined (AES)
2844 hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
2845 hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1);
2846 hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2);
2847 hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3);
2848 #else /* CRYP */
2849 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
2850 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
2851 hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
2852 hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
2853 #endif /* End AES or CRYP */
2854 }
2855 } /* if (DoKeyIVConfig == 1U) */
2856
2857 /* Set the phase */
2858 hcryp->Phase = CRYP_PHASE_PROCESS;
2859 if (hcryp->Size != 0U)
2860 {
2861
2862 #if defined (AES)
2863
2864 /* Enable computation complete flag and error interrupts */
2865 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
2866
2867 /* Enable CRYP */
2868 __HAL_CRYP_ENABLE(hcryp);
2869
2870 /* Write the input block in the IN FIFO */
2871 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
2872 hcryp->CrypInCount++;
2873 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
2874 hcryp->CrypInCount++;
2875 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
2876 hcryp->CrypInCount++;
2877 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
2878 hcryp->CrypInCount++;
2879
2880 #else /* CRYP */
2881
2882 /* Enable interrupts */
2883 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
2884
2885 /* Enable CRYP */
2886 __HAL_CRYP_ENABLE(hcryp);
2887
2888 #endif /* End AES or CRYP */
2889 }
2890 else
2891 {
2892 /* Process locked */
2893 __HAL_UNLOCK(hcryp);
2894
2895 /* Change the CRYP state */
2896 hcryp->State = HAL_CRYP_STATE_READY;
2897 }
2898
2899 /* Return function status */
2900 return HAL_OK;
2901 }
2902 /**
2903 * @brief Decryption in ECB/CBC & CTR mode with AES Standard using DMA mode
2904 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
2905 * the configuration information for CRYP module
2906 * @retval HAL status
2907 */
CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef * hcryp)2908 static HAL_StatusTypeDef CRYP_AES_Decrypt_DMA(CRYP_HandleTypeDef *hcryp)
2909 {
2910 __IO uint32_t count = 0U;
2911 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
2912
2913 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
2914 {
2915 if (hcryp->KeyIVConfig == 1U)
2916 {
2917 /* If the Key and IV configuration has to be done only once
2918 and if it has already been done, skip it */
2919 DoKeyIVConfig = 0U;
2920 }
2921 else
2922 {
2923 /* If the Key and IV configuration has to be done only once
2924 and if it has not been done already, do it and set KeyIVConfig
2925 to keep track it won't have to be done again next time */
2926 hcryp->KeyIVConfig = 1U;
2927 }
2928 }
2929 if (DoKeyIVConfig == 1U)
2930 {
2931 /* Key preparation for ECB/CBC */
2932 if (hcryp->Init.Algorithm != CRYP_AES_CTR)
2933 {
2934 #if defined (AES)
2935 if (hcryp->AutoKeyDerivation == DISABLE)/*Mode 2 key preparation*/
2936 {
2937 /* Set key preparation for decryption operating mode*/
2938 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION);
2939
2940 /* Set the Key*/
2941 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2942
2943 /* Enable CRYP */
2944 __HAL_CRYP_ENABLE(hcryp);
2945
2946 /* Wait for CCF flag to be raised */
2947 count = CRYP_TIMEOUT_KEYPREPARATION;
2948 do
2949 {
2950 count-- ;
2951 if (count == 0U)
2952 {
2953 /* Disable the CRYP peripheral clock */
2954 __HAL_CRYP_DISABLE(hcryp);
2955
2956 /* Change state */
2957 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
2958 hcryp->State = HAL_CRYP_STATE_READY;
2959
2960 /* Process unlocked */
2961 __HAL_UNLOCK(hcryp);
2962 return HAL_ERROR;
2963 }
2964 } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
2965
2966 /* Clear CCF Flag */
2967 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
2968
2969 /* Return to decryption operating mode(Mode 3)*/
2970 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_DECRYPT);
2971 }
2972 else /*Mode 4 : decryption & key preparation*/
2973 {
2974 /* Set the Key*/
2975 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2976
2977 /* Set decryption & Key preparation operating mode*/
2978 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_KEYDERIVATION_DECRYPT);
2979 }
2980 #else /* CRYP */
2981 /* change ALGOMODE to key preparation for decryption*/
2982 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_CR_ALGOMODE_AES_KEY);
2983
2984 /* Set the Key*/
2985 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
2986
2987 /* Enable CRYP */
2988 __HAL_CRYP_ENABLE(hcryp);
2989
2990 /* Wait for BUSY flag to be raised */
2991 count = CRYP_TIMEOUT_KEYPREPARATION;
2992 do
2993 {
2994 count-- ;
2995 if (count == 0U)
2996 {
2997 /* Disable the CRYP peripheral clock */
2998 __HAL_CRYP_DISABLE(hcryp);
2999
3000 /* Change state */
3001 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
3002 hcryp->State = HAL_CRYP_STATE_READY;
3003
3004 /* Process unlocked */
3005 __HAL_UNLOCK(hcryp);
3006 return HAL_ERROR;
3007 }
3008 } while (HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY));
3009
3010 /* Turn back to ALGOMODE of the configuration */
3011 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, hcryp->Init.Algorithm);
3012
3013 #endif /* End AES or CRYP */
3014 }
3015 else /*Algorithm CTR */
3016 {
3017 /* Set the Key*/
3018 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
3019 }
3020
3021 if (hcryp->Init.Algorithm != CRYP_AES_ECB)
3022 {
3023 /* Set the Initialization Vector*/
3024 #if defined (AES)
3025 hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
3026 hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1);
3027 hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2);
3028 hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3);
3029 #else /* CRYP */
3030 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
3031 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
3032 hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
3033 hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
3034 #endif /* End AES or CRYP */
3035 }
3036 } /* if (DoKeyIVConfig == 1U) */
3037
3038 /* Set the phase */
3039 hcryp->Phase = CRYP_PHASE_PROCESS;
3040
3041 if (hcryp->Size != 0U)
3042 {
3043 /* Set the input and output addresses and start DMA transfer */
3044 CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size / 4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
3045 }
3046 else
3047 {
3048 /* Process unlocked */
3049 __HAL_UNLOCK(hcryp);
3050
3051 /* Change the CRYP state */
3052 hcryp->State = HAL_CRYP_STATE_READY;
3053 }
3054
3055 /* Return function status */
3056 return HAL_OK;
3057 }
3058
3059
3060 /**
3061 * @brief DMA CRYP input data process complete callback.
3062 * @param hdma: DMA handle
3063 * @retval None
3064 */
CRYP_DMAInCplt(DMA_HandleTypeDef * hdma)3065 static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma)
3066 {
3067 CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3068
3069 /* Disable the DMA transfer for input FIFO request by resetting the DIEN bit
3070 in the DMACR register */
3071 #if defined (CRYP)
3072 hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DIEN);
3073
3074 #else /* AES */
3075 CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAINEN);
3076
3077 /* TinyAES2, No output on CCM AES, unlock should be done when input data process complete */
3078 if ((hcryp->Init.Algorithm & CRYP_AES_CCM) == CRYP_AES_CCM)
3079 {
3080 /* Clear CCF flag */
3081 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
3082
3083 /* Change the CRYP state to ready */
3084 hcryp->State = HAL_CRYP_STATE_READY;
3085
3086 /* Process Unlocked */
3087 __HAL_UNLOCK(hcryp);
3088 }
3089 #endif /* End AES or CRYP */
3090
3091 /* Call input data transfer complete callback */
3092 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3093 /*Call registered Input complete callback*/
3094 hcryp->InCpltCallback(hcryp);
3095 #else
3096 /*Call legacy weak Input complete callback*/
3097 HAL_CRYP_InCpltCallback(hcryp);
3098 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3099 }
3100
3101 /**
3102 * @brief DMA CRYP output data process complete callback.
3103 * @param hdma: DMA handle
3104 * @retval None
3105 */
CRYP_DMAOutCplt(DMA_HandleTypeDef * hdma)3106 static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma)
3107 {
3108 CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3109
3110 /* Disable the DMA transfer for output FIFO request by resetting
3111 the DOEN bit in the DMACR register */
3112
3113 #if defined (CRYP)
3114
3115 hcryp->Instance->DMACR &= (uint32_t)(~CRYP_DMACR_DOEN);
3116 if ((hcryp->Init.Algorithm & CRYP_AES_GCM) != CRYP_AES_GCM)
3117 {
3118 /* Disable CRYP (not allowed in GCM)*/
3119 __HAL_CRYP_DISABLE(hcryp);
3120 }
3121 #else /* AES */
3122
3123 CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAOUTEN);
3124
3125 /* Clear CCF flag */
3126 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
3127
3128 if ((hcryp->Init.Algorithm & CRYP_AES_GCM_GMAC) != CRYP_AES_GCM_GMAC)
3129 {
3130 /* Disable CRYP (not allowed in GCM)*/
3131 __HAL_CRYP_DISABLE(hcryp);
3132 }
3133 #endif /* End AES or CRYP */
3134
3135 /* Change the CRYP state to ready */
3136 hcryp->State = HAL_CRYP_STATE_READY;
3137
3138 /* Process unlocked */
3139 __HAL_UNLOCK(hcryp);
3140 /* Call output data transfer complete callback */
3141 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3142 /*Call registered Output complete callback*/
3143 hcryp->OutCpltCallback(hcryp);
3144 #else
3145 /*Call legacy weak Output complete callback*/
3146 HAL_CRYP_OutCpltCallback(hcryp);
3147 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3148 }
3149
3150 /**
3151 * @brief DMA CRYP communication error callback.
3152 * @param hdma: DMA handle
3153 * @retval None
3154 */
CRYP_DMAError(DMA_HandleTypeDef * hdma)3155 static void CRYP_DMAError(DMA_HandleTypeDef *hdma)
3156 {
3157 CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
3158
3159 /* Change the CRYP peripheral state */
3160 hcryp->State = HAL_CRYP_STATE_READY;
3161
3162 /* DMA error code field */
3163 hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
3164
3165 #if defined (AES)
3166
3167 /* Clear CCF flag */
3168 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
3169
3170 #endif /* AES */
3171
3172 /* Call error callback */
3173 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3174 /*Call registered error callback*/
3175 hcryp->ErrorCallback(hcryp);
3176 #else
3177 /*Call legacy weak error callback*/
3178 HAL_CRYP_ErrorCallback(hcryp);
3179 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3180 }
3181
3182 /**
3183 * @brief Set the DMA configuration and start the DMA transfer
3184 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
3185 * the configuration information for CRYP module
3186 * @param inputaddr: address of the input buffer
3187 * @param Size: size of the input buffer, must be a multiple of 16.
3188 * @param outputaddr: address of the output buffer
3189 * @retval None
3190 */
CRYP_SetDMAConfig(CRYP_HandleTypeDef * hcryp,uint32_t inputaddr,uint16_t Size,uint32_t outputaddr)3191 static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr)
3192 {
3193 /* Set the CRYP DMA transfer complete callback */
3194 hcryp->hdmain->XferCpltCallback = CRYP_DMAInCplt;
3195
3196 /* Set the DMA input error callback */
3197 hcryp->hdmain->XferErrorCallback = CRYP_DMAError;
3198
3199 /* Set the CRYP DMA transfer complete callback */
3200 hcryp->hdmaout->XferCpltCallback = CRYP_DMAOutCplt;
3201
3202 /* Set the DMA output error callback */
3203 hcryp->hdmaout->XferErrorCallback = CRYP_DMAError;
3204
3205 #if defined (CRYP)
3206
3207 /* Enable CRYP */
3208 __HAL_CRYP_ENABLE(hcryp);
3209
3210 /* Enable the input DMA Stream */
3211 if (HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DIN, Size) != HAL_OK)
3212 {
3213 /* DMA error code field */
3214 hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
3215
3216 /* Call error callback */
3217 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3218 /*Call registered error callback*/
3219 hcryp->ErrorCallback(hcryp);
3220 #else
3221 /*Call legacy weak error callback*/
3222 HAL_CRYP_ErrorCallback(hcryp);
3223 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3224 }
3225 /* Enable the output DMA Stream */
3226 if (HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUT, outputaddr, Size) != HAL_OK)
3227 {
3228 /* DMA error code field */
3229 hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
3230
3231 /* Call error callback */
3232 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3233 /*Call registered error callback*/
3234 hcryp->ErrorCallback(hcryp);
3235 #else
3236 /*Call legacy weak error callback*/
3237 HAL_CRYP_ErrorCallback(hcryp);
3238 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3239 }
3240 /* Enable In/Out DMA request */
3241 hcryp->Instance->DMACR = CRYP_DMACR_DOEN | CRYP_DMACR_DIEN;
3242
3243 #else /* AES */
3244
3245 if (((hcryp->Init.Algorithm & CRYP_AES_GCM_GMAC) != CRYP_AES_GCM_GMAC)
3246 && ((hcryp->Init.Algorithm & CRYP_AES_CCM) != CRYP_AES_CCM))
3247 {
3248 /* Enable CRYP (not allowed in GCM & CCM)*/
3249 __HAL_CRYP_ENABLE(hcryp);
3250 }
3251
3252 /* Enable the DMA input stream */
3253 if (HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&hcryp->Instance->DINR, Size) != HAL_OK)
3254 {
3255 /* DMA error code field */
3256 hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
3257
3258 /* Call error callback */
3259 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3260 /*Call registered error callback*/
3261 hcryp->ErrorCallback(hcryp);
3262 #else
3263 /*Call legacy weak error callback*/
3264 HAL_CRYP_ErrorCallback(hcryp);
3265 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3266 }
3267 /* Enable the DMA output stream */
3268 if (HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&hcryp->Instance->DOUTR, outputaddr, Size) != HAL_OK)
3269 {
3270 /* DMA error code field */
3271 hcryp->ErrorCode |= HAL_CRYP_ERROR_DMA;
3272
3273 /* Call error callback */
3274 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3275 /*Call registered error callback*/
3276 hcryp->ErrorCallback(hcryp);
3277 #else
3278 /*Call legacy weak error callback*/
3279 HAL_CRYP_ErrorCallback(hcryp);
3280 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3281 }
3282 /*AES2v1.1.1 : CCM authentication : no init phase, only header and final phase */
3283 /* Enable In and Out DMA requests */
3284 if ((hcryp->Init.Algorithm & CRYP_AES_CCM) == CRYP_AES_CCM)
3285 {
3286 /* Enable only In DMA requests for CCM*/
3287 SET_BIT(hcryp->Instance->CR, (AES_CR_DMAINEN));
3288 }
3289 else
3290 {
3291 /* Enable In and Out DMA requests */
3292 SET_BIT(hcryp->Instance->CR, (AES_CR_DMAINEN | AES_CR_DMAOUTEN));
3293 }
3294 #endif /* End AES or CRYP */
3295 }
3296
3297 /**
3298 * @brief Process Data: Write Input data in polling mode and used in AES functions.
3299 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
3300 * the configuration information for CRYP module
3301 * @param Timeout: Specify Timeout value
3302 * @retval None
3303 */
CRYP_AES_ProcessData(CRYP_HandleTypeDef * hcryp,uint32_t Timeout)3304 static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
3305 {
3306
3307 uint32_t temp[4]; /* Temporary CrypOutBuff */
3308 uint32_t i;
3309 #if defined (CRYP)
3310 uint16_t incount; /* Temporary CrypInCount Value */
3311 uint16_t outcount; /* Temporary CrypOutCount Value */
3312 #endif
3313
3314 #if defined (CRYP)
3315
3316 /*Temporary CrypOutCount Value*/
3317 incount = hcryp->CrypInCount;
3318
3319 if (((hcryp->Instance->SR & CRYP_FLAG_IFNF) != 0x0U) && (incount < (hcryp->Size / 4U)))
3320 {
3321 /* Write the input block in the IN FIFO */
3322 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3323 hcryp->CrypInCount++;
3324 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3325 hcryp->CrypInCount++;
3326 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3327 hcryp->CrypInCount++;
3328 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3329 hcryp->CrypInCount++;
3330 }
3331
3332 /* Wait for OFNE flag to be raised */
3333 if (CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
3334 {
3335 /* Disable the CRYP peripheral clock */
3336 __HAL_CRYP_DISABLE(hcryp);
3337
3338 /* Change state & error code*/
3339 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
3340 hcryp->State = HAL_CRYP_STATE_READY;
3341
3342 /* Process unlocked */
3343 __HAL_UNLOCK(hcryp);
3344 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3345 /*Call registered error callback*/
3346 hcryp->ErrorCallback(hcryp);
3347 #else
3348 /*Call legacy weak error callback*/
3349 HAL_CRYP_ErrorCallback(hcryp);
3350 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3351 }
3352
3353 /*Temporary CrypOutCount Value*/
3354 outcount = hcryp->CrypOutCount;
3355
3356 if (((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U) && (outcount < (hcryp->Size / 4U)))
3357 {
3358 /* Read the output block from the Output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
3359 for (i = 0U; i < 4U; i++)
3360 {
3361 temp[i] = hcryp->Instance->DOUT;
3362 }
3363 i = 0U;
3364 while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 4U))
3365 {
3366 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
3367 hcryp->CrypOutCount++;
3368 i++;
3369 }
3370 }
3371
3372 #else /* AES */
3373
3374 /* Write the input block in the IN FIFO */
3375 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3376 hcryp->CrypInCount++;
3377 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3378 hcryp->CrypInCount++;
3379 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3380 hcryp->CrypInCount++;
3381 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3382 hcryp->CrypInCount++;
3383
3384 /* Wait for CCF flag to be raised */
3385 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
3386 {
3387 /* Disable the CRYP peripheral clock */
3388 __HAL_CRYP_DISABLE(hcryp);
3389
3390 /* Change state */
3391 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
3392 hcryp->State = HAL_CRYP_STATE_READY;
3393
3394 /* Process unlocked */
3395 __HAL_UNLOCK(hcryp);
3396 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3397 /*Call registered error callback*/
3398 hcryp->ErrorCallback(hcryp);
3399 #else
3400 /*Call legacy weak error callback*/
3401 HAL_CRYP_ErrorCallback(hcryp);
3402 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3403 }
3404
3405 /* Clear CCF Flag */
3406 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
3407
3408 /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer*/
3409 for (i = 0U; i < 4U; i++)
3410 {
3411 temp[i] = hcryp->Instance->DOUTR;
3412 }
3413 i = 0U;
3414 while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (i < 4U))
3415 {
3416 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
3417 hcryp->CrypOutCount++;
3418 i++;
3419 }
3420 #endif /* End AES or CRYP */
3421 }
3422
3423 /**
3424 * @brief Handle CRYP block input/output data handling under interruption.
3425 * @note The function is called under interruption only, once
3426 * interruptions have been enabled by HAL_CRYP_Encrypt_IT or HAL_CRYP_Decrypt_IT.
3427 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
3428 * the configuration information for CRYP module.
3429 * @retval HAL status
3430 */
CRYP_AES_IT(CRYP_HandleTypeDef * hcryp)3431 static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp)
3432 {
3433 uint32_t temp[4]; /* Temporary CrypOutBuff */
3434 uint32_t i;
3435 #if defined (CRYP)
3436 uint16_t incount; /* Temporary CrypInCount Value */
3437 uint16_t outcount; /* Temporary CrypOutCount Value */
3438 #endif
3439
3440 if (hcryp->State == HAL_CRYP_STATE_BUSY)
3441 {
3442 #if defined (CRYP)
3443
3444 /*Temporary CrypOutCount Value*/
3445 incount = hcryp->CrypInCount;
3446 if (((hcryp->Instance->SR & CRYP_FLAG_IFNF) != 0x0U) && (incount < (hcryp->Size / 4U)))
3447 {
3448 /* Write the input block in the IN FIFO */
3449 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3450 hcryp->CrypInCount++;
3451 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3452 hcryp->CrypInCount++;
3453 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3454 hcryp->CrypInCount++;
3455 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3456 hcryp->CrypInCount++;
3457 if (hcryp->CrypInCount == ((uint16_t)(hcryp->Size) / 4U))
3458 {
3459 /* Disable interrupts */
3460 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
3461
3462 /* Call the input data transfer complete callback */
3463 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3464 /*Call registered Input complete callback*/
3465 hcryp->InCpltCallback(hcryp);
3466 #else
3467 /*Call legacy weak Input complete callback*/
3468 HAL_CRYP_InCpltCallback(hcryp);
3469 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3470 }
3471 }
3472 /*Temporary CrypOutCount Value*/
3473 outcount = hcryp->CrypOutCount;
3474
3475 if (((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U) && (outcount < (hcryp->Size / 4U)))
3476 {
3477 /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
3478 for (i = 0U; i < 4U; i++)
3479 {
3480 temp[i] = hcryp->Instance->DOUT;
3481 }
3482 i = 0U;
3483 while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 4U))
3484 {
3485 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
3486 hcryp->CrypOutCount++;
3487 i++;
3488 }
3489 if (hcryp->CrypOutCount == ((uint16_t)(hcryp->Size) / 4U))
3490 {
3491 /* Disable interrupts */
3492 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
3493
3494 /* Change the CRYP state */
3495 hcryp->State = HAL_CRYP_STATE_READY;
3496
3497 /* Disable CRYP */
3498 __HAL_CRYP_DISABLE(hcryp);
3499
3500 /* Process unlocked */
3501 __HAL_UNLOCK(hcryp);
3502
3503 /* Call Output transfer complete callback */
3504 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3505 /*Call registered Output complete callback*/
3506 hcryp->OutCpltCallback(hcryp);
3507 #else
3508 /*Call legacy weak Output complete callback*/
3509 HAL_CRYP_OutCpltCallback(hcryp);
3510 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3511 }
3512 }
3513
3514 #else /*AES*/
3515
3516 /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer*/
3517 for (i = 0U; i < 4U; i++)
3518 {
3519 temp[i] = hcryp->Instance->DOUTR;
3520 }
3521 i = 0U;
3522 while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (i < 4U))
3523 {
3524 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
3525 hcryp->CrypOutCount++;
3526 i++;
3527 }
3528
3529 if (hcryp->CrypOutCount == (hcryp->Size / 4U))
3530 {
3531 /* Disable Computation Complete flag and errors interrupts */
3532 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
3533
3534 /* Change the CRYP state */
3535 hcryp->State = HAL_CRYP_STATE_READY;
3536
3537 /* Disable CRYP */
3538 __HAL_CRYP_DISABLE(hcryp);
3539
3540 /* Process Unlocked */
3541 __HAL_UNLOCK(hcryp);
3542
3543 /* Call Output transfer complete callback */
3544 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3545 /*Call registered Output complete callback*/
3546 hcryp->OutCpltCallback(hcryp);
3547 #else
3548 /*Call legacy weak Output complete callback*/
3549 HAL_CRYP_OutCpltCallback(hcryp);
3550 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3551 }
3552 else
3553 {
3554 /* Write the input block in the IN FIFO */
3555 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3556 hcryp->CrypInCount++;
3557 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3558 hcryp->CrypInCount++;
3559 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3560 hcryp->CrypInCount++;
3561 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
3562 hcryp->CrypInCount++;
3563
3564 if (hcryp->CrypInCount == (hcryp->Size / 4U))
3565 {
3566 /* Call Input transfer complete callback */
3567 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
3568 /*Call registered Input complete callback*/
3569 hcryp->InCpltCallback(hcryp);
3570 #else
3571 /*Call legacy weak Input complete callback*/
3572 HAL_CRYP_InCpltCallback(hcryp);
3573 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3574 }
3575 }
3576 #endif /* End AES or CRYP */
3577
3578 }
3579 else
3580 {
3581 /* Busy error code field */
3582 hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY;
3583 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
3584 /*Call registered error callback*/
3585 hcryp->ErrorCallback(hcryp);
3586 #else
3587 /*Call legacy weak error callback*/
3588 HAL_CRYP_ErrorCallback(hcryp);
3589 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
3590 }
3591 }
3592
3593 /**
3594 * @brief Writes Key in Key registers.
3595 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
3596 * the configuration information for CRYP module
3597 * @param KeySize: Size of Key
3598 * @retval None
3599 */
CRYP_SetKey(CRYP_HandleTypeDef * hcryp,uint32_t KeySize)3600 static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint32_t KeySize)
3601 {
3602 #if defined (CRYP)
3603
3604 switch (KeySize)
3605 {
3606 case CRYP_KEYSIZE_256B:
3607 hcryp->Instance->K0LR = *(uint32_t *)(hcryp->Init.pKey);
3608 hcryp->Instance->K0RR = *(uint32_t *)(hcryp->Init.pKey + 1);
3609 hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey + 2);
3610 hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 3);
3611 hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 4);
3612 hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 5);
3613 hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 6);
3614 hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 7);
3615 break;
3616 case CRYP_KEYSIZE_192B:
3617 hcryp->Instance->K1LR = *(uint32_t *)(hcryp->Init.pKey);
3618 hcryp->Instance->K1RR = *(uint32_t *)(hcryp->Init.pKey + 1);
3619 hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey + 2);
3620 hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 3);
3621 hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 4);
3622 hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 5);
3623 break;
3624 case CRYP_KEYSIZE_128B:
3625 hcryp->Instance->K2LR = *(uint32_t *)(hcryp->Init.pKey);
3626 hcryp->Instance->K2RR = *(uint32_t *)(hcryp->Init.pKey + 1);
3627 hcryp->Instance->K3LR = *(uint32_t *)(hcryp->Init.pKey + 2);
3628 hcryp->Instance->K3RR = *(uint32_t *)(hcryp->Init.pKey + 3);
3629
3630 break;
3631 default:
3632 break;
3633 }
3634 #else /*AES*/
3635 switch (KeySize)
3636 {
3637 case CRYP_KEYSIZE_256B:
3638 hcryp->Instance->KEYR7 = *(uint32_t *)(hcryp->Init.pKey);
3639 hcryp->Instance->KEYR6 = *(uint32_t *)(hcryp->Init.pKey + 1);
3640 hcryp->Instance->KEYR5 = *(uint32_t *)(hcryp->Init.pKey + 2);
3641 hcryp->Instance->KEYR4 = *(uint32_t *)(hcryp->Init.pKey + 3);
3642 hcryp->Instance->KEYR3 = *(uint32_t *)(hcryp->Init.pKey + 4);
3643 hcryp->Instance->KEYR2 = *(uint32_t *)(hcryp->Init.pKey + 5);
3644 hcryp->Instance->KEYR1 = *(uint32_t *)(hcryp->Init.pKey + 6);
3645 hcryp->Instance->KEYR0 = *(uint32_t *)(hcryp->Init.pKey + 7);
3646 break;
3647 case CRYP_KEYSIZE_128B:
3648 hcryp->Instance->KEYR3 = *(uint32_t *)(hcryp->Init.pKey);
3649 hcryp->Instance->KEYR2 = *(uint32_t *)(hcryp->Init.pKey + 1);
3650 hcryp->Instance->KEYR1 = *(uint32_t *)(hcryp->Init.pKey + 2);
3651 hcryp->Instance->KEYR0 = *(uint32_t *)(hcryp->Init.pKey + 3);
3652
3653 break;
3654 default:
3655 break;
3656 }
3657 #endif /* End AES or CRYP */
3658 }
3659
3660
3661 /**
3662 * @brief Encryption/Decryption process in AES GCM mode and prepare the authentication TAG
3663 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
3664 * the configuration information for CRYP module
3665 * @param Timeout: Timeout duration
3666 * @retval HAL status
3667 */
CRYP_AESGCM_Process(CRYP_HandleTypeDef * hcryp,uint32_t Timeout)3668 static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
3669 {
3670 uint32_t tickstart;
3671 uint32_t wordsize = (uint32_t)(hcryp->Size) / 4U ;
3672 uint16_t outcount; /* Temporary CrypOutCount Value */
3673 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
3674
3675 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
3676 {
3677 if (hcryp->KeyIVConfig == 1U)
3678 {
3679 /* If the Key and IV configuration has to be done only once
3680 and if it has already been done, skip it */
3681 DoKeyIVConfig = 0U;
3682 hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
3683 }
3684 else
3685 {
3686 /* If the Key and IV configuration has to be done only once
3687 and if it has not been done already, do it and set KeyIVConfig
3688 to keep track it won't have to be done again next time */
3689 hcryp->KeyIVConfig = 1U;
3690 hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
3691 }
3692 }
3693 else
3694 {
3695 hcryp->SizesSum = hcryp->Size;
3696 }
3697
3698 if (DoKeyIVConfig == 1U)
3699 {
3700 /* Reset CrypHeaderCount */
3701 hcryp->CrypHeaderCount = 0U;
3702
3703 /****************************** Init phase **********************************/
3704
3705 CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
3706
3707 /* Set the key */
3708 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
3709
3710 #if defined(CRYP)
3711
3712 /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
3713 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
3714 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
3715 hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
3716 hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
3717
3718 /* Enable the CRYP peripheral */
3719 __HAL_CRYP_ENABLE(hcryp);
3720
3721 /* Get tick */
3722 tickstart = HAL_GetTick();
3723
3724 /*Wait for the CRYPEN bit to be cleared*/
3725 while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
3726 {
3727 /* Check for the Timeout */
3728 if (Timeout != HAL_MAX_DELAY)
3729 {
3730 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
3731 {
3732 /* Disable the CRYP peripheral clock */
3733 __HAL_CRYP_DISABLE(hcryp);
3734
3735 /* Change state */
3736 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
3737 hcryp->State = HAL_CRYP_STATE_READY;
3738
3739 /* Process unlocked */
3740 __HAL_UNLOCK(hcryp);
3741 return HAL_ERROR;
3742 }
3743 }
3744 }
3745
3746 #else /* AES */
3747 /* Workaround 1 : only AES.
3748 Datatype configuration must be 32 bits during Init phase. Only, after Init, and before re
3749 enabling the IP, datatype different from 32 bits can be configured.*/
3750 /* Select DATATYPE 32 */
3751 MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, CRYP_DATATYPE_32B);
3752
3753 /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
3754 hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
3755 hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1);
3756 hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2);
3757 hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3);
3758
3759 /* Enable the CRYP peripheral */
3760 __HAL_CRYP_ENABLE(hcryp);
3761
3762 /* just wait for hash computation */
3763 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
3764 {
3765 /* Change state */
3766 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
3767 hcryp->State = HAL_CRYP_STATE_READY;
3768
3769 /* Process unlocked & return error */
3770 __HAL_UNLOCK(hcryp);
3771 return HAL_ERROR;
3772 }
3773 /* Clear CCF flag */
3774 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
3775
3776 #endif /* End AES or CRYP */
3777
3778 /************************ Header phase *************************************/
3779
3780 if (CRYP_GCMCCM_SetHeaderPhase(hcryp, Timeout) != HAL_OK)
3781 {
3782 return HAL_ERROR;
3783 }
3784
3785 /*************************Payload phase ************************************/
3786
3787 /* Set the phase */
3788 hcryp->Phase = CRYP_PHASE_PROCESS;
3789
3790 #if defined(CRYP)
3791
3792 /* Disable the CRYP peripheral */
3793 __HAL_CRYP_DISABLE(hcryp);
3794
3795 /* Select payload phase once the header phase is performed */
3796 CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
3797
3798 /* Enable the CRYP peripheral */
3799 __HAL_CRYP_ENABLE(hcryp);
3800
3801 #else /* AES */
3802
3803 /* Select payload phase once the header phase is performed */
3804 CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
3805
3806 #endif /* End AES or CRYP */
3807 } /* if (DoKeyIVConfig == 1U) */
3808
3809 if ((hcryp->Size % 16U) != 0U)
3810 {
3811 /* recalculate wordsize */
3812 wordsize = ((wordsize / 4U) * 4U) ;
3813 }
3814
3815 /* Get tick */
3816 tickstart = HAL_GetTick();
3817 /*Temporary CrypOutCount Value*/
3818 outcount = hcryp->CrypOutCount;
3819
3820 /* Write input data and get output Data */
3821 while ((hcryp->CrypInCount < wordsize) && (outcount < wordsize))
3822 {
3823 /* Write plain data and get cipher data */
3824 CRYP_AES_ProcessData(hcryp, Timeout);
3825
3826 /*Temporary CrypOutCount Value*/
3827 outcount = hcryp->CrypOutCount;
3828
3829 /* Check for the Timeout */
3830 if (Timeout != HAL_MAX_DELAY)
3831 {
3832 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
3833 {
3834 /* Disable the CRYP peripheral clock */
3835 __HAL_CRYP_DISABLE(hcryp);
3836
3837 /* Change state & error code */
3838 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
3839 hcryp->State = HAL_CRYP_STATE_READY;
3840
3841 /* Process unlocked */
3842 __HAL_UNLOCK(hcryp);
3843 return HAL_ERROR;
3844 }
3845 }
3846 }
3847
3848 if ((hcryp->Size % 16U) != 0U)
3849 {
3850 /* Workaround 2 : CRYP1 & AES generates correct TAG for GCM mode only when input block size is multiple of
3851 128 bits. If lthe size of the last block of payload is inferior to 128 bits, when GCM encryption
3852 is selected, then the TAG message will be wrong.*/
3853 CRYP_Workaround(hcryp, Timeout);
3854 }
3855
3856 /* Return function status */
3857 return HAL_OK;
3858 }
3859
3860 /**
3861 * @brief Encryption/Decryption process in AES GCM mode and prepare the authentication TAG in interrupt mode
3862 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
3863 * the configuration information for CRYP module
3864 * @retval HAL status
3865 */
CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef * hcryp)3866 static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp)
3867 {
3868 __IO uint32_t count = 0U;
3869 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
3870 #if defined(AES)
3871 uint32_t loopcounter;
3872 uint32_t lastwordsize;
3873 uint32_t npblb;
3874 #endif /* AES */
3875
3876 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
3877 {
3878 if (hcryp->KeyIVConfig == 1U)
3879 {
3880 /* If the Key and IV configuration has to be done only once
3881 and if it has already been done, skip it */
3882 DoKeyIVConfig = 0U;
3883 hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
3884 }
3885 else
3886 {
3887 /* If the Key and IV configuration has to be done only once
3888 and if it has not been done already, do it and set KeyIVConfig
3889 to keep track it won't have to be done again next time */
3890 hcryp->KeyIVConfig = 1U;
3891 hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
3892 }
3893 }
3894 else
3895 {
3896 hcryp->SizesSum = hcryp->Size;
3897 }
3898
3899 /* Configure Key, IV and process message (header and payload) */
3900 if (DoKeyIVConfig == 1U)
3901 {
3902 /* Reset CrypHeaderCount */
3903 hcryp->CrypHeaderCount = 0U;
3904
3905 /******************************* Init phase *********************************/
3906
3907 CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
3908
3909 /* Set the key */
3910 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
3911
3912 #if defined(CRYP)
3913 /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
3914 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
3915 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
3916 hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
3917 hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
3918
3919 /* Enable the CRYP peripheral */
3920 __HAL_CRYP_ENABLE(hcryp);
3921
3922 /*Wait for the CRYPEN bit to be cleared*/
3923 count = CRYP_TIMEOUT_GCMCCMINITPHASE;
3924 do
3925 {
3926 count-- ;
3927 if (count == 0U)
3928 {
3929 /* Disable the CRYP peripheral clock */
3930 __HAL_CRYP_DISABLE(hcryp);
3931
3932 /* Change state */
3933 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
3934 hcryp->State = HAL_CRYP_STATE_READY;
3935
3936 /* Process unlocked */
3937 __HAL_UNLOCK(hcryp);
3938 return HAL_ERROR;
3939 }
3940 } while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN);
3941
3942 #else /* AES */
3943
3944 /* Workaround 1 : only AES
3945 Datatype configuration must be 32 bits during INIT phase. Only, after INIT, and before re
3946 enabling the IP, datatype different from 32 bits can be configured.*/
3947 /* Select DATATYPE 32 */
3948 MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, CRYP_DATATYPE_32B);
3949
3950 /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
3951 hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
3952 hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1);
3953 hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2);
3954 hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3);
3955
3956 /* Enable the CRYP peripheral */
3957 __HAL_CRYP_ENABLE(hcryp);
3958
3959 /* just wait for hash computation */
3960 count = CRYP_TIMEOUT_GCMCCMINITPHASE;
3961 do
3962 {
3963 count-- ;
3964 if (count == 0U)
3965 {
3966 /* Disable the CRYP peripheral clock */
3967 __HAL_CRYP_DISABLE(hcryp);
3968
3969 /* Change state */
3970 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
3971 hcryp->State = HAL_CRYP_STATE_READY;
3972
3973 /* Process unlocked */
3974 __HAL_UNLOCK(hcryp);
3975 return HAL_ERROR;
3976 }
3977 } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
3978
3979 /* Clear CCF flag */
3980 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
3981
3982 #endif /* End AES or CRYP */
3983
3984 /***************************** Header phase *********************************/
3985
3986 #if defined(CRYP)
3987
3988 /* Select header phase */
3989 CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
3990
3991 /* Enable interrupts */
3992 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI);
3993
3994 /* Enable CRYP */
3995 __HAL_CRYP_ENABLE(hcryp);
3996
3997 #else /* AES */
3998
3999 /* Workaround 1: only AES , before re-enabling the IP, datatype can be configured*/
4000 MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType);
4001
4002 /* Select header phase */
4003 CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
4004
4005 /* Enable computation complete flag and error interrupts */
4006 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
4007
4008 /* Enable the CRYP peripheral */
4009 __HAL_CRYP_ENABLE(hcryp);
4010
4011 if (hcryp->Init.HeaderSize == 0U) /*header phase is skipped*/
4012 {
4013 /* Set the phase */
4014 hcryp->Phase = CRYP_PHASE_PROCESS;
4015
4016 /* Select payload phase once the header phase is performed */
4017 MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_PAYLOAD);
4018
4019 /* Write the payload Input block in the IN FIFO */
4020 if (hcryp->Size == 0U)
4021 {
4022 /* Disable interrupts */
4023 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
4024
4025 /* Change the CRYP state */
4026 hcryp->State = HAL_CRYP_STATE_READY;
4027
4028 /* Process unlocked */
4029 __HAL_UNLOCK(hcryp);
4030 }
4031 else if (hcryp->Size >= 16U)
4032 {
4033 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
4034 hcryp->CrypInCount++;
4035 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
4036 hcryp->CrypInCount++;
4037 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
4038 hcryp->CrypInCount++;
4039 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
4040 hcryp->CrypInCount++;
4041 if (hcryp->CrypInCount == (hcryp->Size / 4U))
4042 {
4043 /* Call Input transfer complete callback */
4044 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
4045 /*Call registered Input complete callback*/
4046 hcryp->InCpltCallback(hcryp);
4047 #else
4048 /*Call legacy weak Input complete callback*/
4049 HAL_CRYP_InCpltCallback(hcryp);
4050 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
4051 }
4052 }
4053 else /* Size < 16Bytes : first block is the last block*/
4054 {
4055 /* Workaround not implemented*/
4056 /* Size should be %4 otherwise Tag will be incorrectly generated for GCM Encryption:
4057 Workaround is implemented in polling mode, so if last block of
4058 payload <128bit don't use CRYP_Encrypt_IT otherwise TAG is incorrectly generated for GCM Encryption. */
4059
4060 /* Compute the number of padding bytes in last block of payload */
4061 npblb = 16U - (uint32_t)(hcryp->Size);
4062
4063 /* Number of valid words (lastwordsize) in last block */
4064 if ((npblb % 4U) == 0U)
4065 {
4066 lastwordsize = (16U - npblb) / 4U;
4067 }
4068 else
4069 {
4070 lastwordsize = ((16U - npblb) / 4U) + 1U;
4071 }
4072
4073 /* last block optionally pad the data with zeros*/
4074 for (loopcounter = 0U; loopcounter < lastwordsize ; loopcounter++)
4075 {
4076 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
4077 hcryp->CrypInCount++;
4078 }
4079 while (loopcounter < 4U)
4080 {
4081 /* pad the data with zeros to have a complete block */
4082 hcryp->Instance->DINR = 0x0U;
4083 loopcounter++;
4084 }
4085 }
4086 }
4087 else if ((hcryp->Init.HeaderSize) < 4U)
4088 {
4089 for (loopcounter = 0U; loopcounter < hcryp->Init.HeaderSize ; loopcounter++)
4090 {
4091 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4092 hcryp->CrypHeaderCount++ ;
4093 }
4094 while (loopcounter < 4U)
4095 {
4096 /* pad the data with zeros to have a complete block */
4097 hcryp->Instance->DINR = 0x0U;
4098 loopcounter++;
4099 }
4100 /* Set the phase */
4101 hcryp->Phase = CRYP_PHASE_PROCESS;
4102
4103 /* Select payload phase once the header phase is performed */
4104 CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
4105
4106 /* Call Input transfer complete callback */
4107 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
4108 /*Call registered Input complete callback*/
4109 hcryp->InCpltCallback(hcryp);
4110 #else
4111 /*Call legacy weak Input complete callback*/
4112 HAL_CRYP_InCpltCallback(hcryp);
4113 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
4114 }
4115 else if ((hcryp->Init.HeaderSize) >= 4U)
4116 {
4117 /* Write the input block in the IN FIFO */
4118 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4119 hcryp->CrypHeaderCount++;
4120 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4121 hcryp->CrypHeaderCount++;
4122 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4123 hcryp->CrypHeaderCount++;
4124 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4125 hcryp->CrypHeaderCount++;
4126 }
4127 else
4128 {
4129 /* Nothing to do */
4130 }
4131
4132 #endif /* End AES or CRYP */
4133 } /* end of if (DoKeyIVConfig == 1U) */
4134
4135 /* Return function status */
4136 return HAL_OK;
4137 }
4138
4139
4140 /**
4141 * @brief Encryption/Decryption process in AES GCM mode and prepare the authentication TAG using DMA
4142 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
4143 * the configuration information for CRYP module
4144 * @retval HAL status
4145 */
CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef * hcryp)4146 static HAL_StatusTypeDef CRYP_AESGCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
4147 {
4148 __IO uint32_t count = 0U;
4149 uint32_t wordsize;
4150 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
4151
4152 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
4153 {
4154 if (hcryp->KeyIVConfig == 1U)
4155 {
4156 /* If the Key and IV configuration has to be done only once
4157 and if it has already been done, skip it */
4158 DoKeyIVConfig = 0U;
4159 hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
4160 }
4161 else
4162 {
4163 /* If the Key and IV configuration has to be done only once
4164 and if it has not been done already, do it and set KeyIVConfig
4165 to keep track it won't have to be done again next time */
4166 hcryp->KeyIVConfig = 1U;
4167 hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
4168 }
4169 }
4170 else
4171 {
4172 hcryp->SizesSum = hcryp->Size;
4173 }
4174
4175 if (DoKeyIVConfig == 1U)
4176 {
4177 /* Reset CrypHeaderCount */
4178 hcryp->CrypHeaderCount = 0U;
4179
4180 /*************************** Init phase ************************************/
4181
4182 CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
4183
4184 /* Set the key */
4185 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
4186
4187 #if defined(CRYP)
4188 /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
4189 hcryp->Instance->IV0LR = *(uint32_t *)(hcryp->Init.pInitVect);
4190 hcryp->Instance->IV0RR = *(uint32_t *)(hcryp->Init.pInitVect + 1);
4191 hcryp->Instance->IV1LR = *(uint32_t *)(hcryp->Init.pInitVect + 2);
4192 hcryp->Instance->IV1RR = *(uint32_t *)(hcryp->Init.pInitVect + 3);
4193
4194 /* Enable the CRYP peripheral */
4195 __HAL_CRYP_ENABLE(hcryp);
4196
4197 /*Wait for the CRYPEN bit to be cleared*/
4198 count = CRYP_TIMEOUT_GCMCCMINITPHASE;
4199 do
4200 {
4201 count-- ;
4202 if (count == 0U)
4203 {
4204 /* Disable the CRYP peripheral clock */
4205 __HAL_CRYP_DISABLE(hcryp);
4206
4207 /* Change state */
4208 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4209 hcryp->State = HAL_CRYP_STATE_READY;
4210
4211 /* Process unlocked */
4212 __HAL_UNLOCK(hcryp);
4213 return HAL_ERROR;
4214 }
4215 } while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN);
4216
4217 #else /* AES */
4218
4219 /*Workaround 1 : only AES
4220 Datatype configuration must be 32 bits during Init phase. Only, after Init, and before re
4221 enabling the IP, datatype different from 32 bits can be configured.*/
4222 /* Select DATATYPE 32 */
4223 MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, CRYP_DATATYPE_32B);
4224
4225 /* Set the initialization vector and the counter : Initial Counter Block (ICB)*/
4226 hcryp->Instance->IVR3 = *(uint32_t *)(hcryp->Init.pInitVect);
4227 hcryp->Instance->IVR2 = *(uint32_t *)(hcryp->Init.pInitVect + 1);
4228 hcryp->Instance->IVR1 = *(uint32_t *)(hcryp->Init.pInitVect + 2);
4229 hcryp->Instance->IVR0 = *(uint32_t *)(hcryp->Init.pInitVect + 3);
4230
4231 /* Enable the CRYP peripheral */
4232 __HAL_CRYP_ENABLE(hcryp);
4233
4234 /* just wait for hash computation */
4235 count = CRYP_TIMEOUT_GCMCCMINITPHASE;
4236 do
4237 {
4238 count-- ;
4239 if (count == 0U)
4240 {
4241 /* Disable the CRYP peripheral clock */
4242 __HAL_CRYP_DISABLE(hcryp);
4243
4244 /* Change state */
4245 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4246 hcryp->State = HAL_CRYP_STATE_READY;
4247
4248 /* Process unlocked */
4249 __HAL_UNLOCK(hcryp);
4250 return HAL_ERROR;
4251 }
4252 } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
4253
4254 /* Clear CCF flag */
4255 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
4256
4257 #endif /* End AES or CRYP */
4258
4259 /************************ Header phase *************************************/
4260
4261 if (CRYP_GCMCCM_SetHeaderPhase_DMA(hcryp) != HAL_OK)
4262 {
4263 return HAL_ERROR;
4264 }
4265
4266 /************************ Payload phase ************************************/
4267
4268 /* Set the phase */
4269 hcryp->Phase = CRYP_PHASE_PROCESS;
4270
4271 #if defined(CRYP)
4272
4273 /* Disable the CRYP peripheral */
4274 __HAL_CRYP_DISABLE(hcryp);
4275
4276 #endif /* CRYP */
4277
4278 /* Select payload phase once the header phase is performed */
4279 CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
4280
4281 } /* if (DoKeyIVConfig == 1U) */
4282
4283 if (hcryp->Size != 0U)
4284 {
4285 /* CRYP1 IP V < 2.2.1 Size should be %4 otherwise Tag will be incorrectly generated for GCM Encryption:
4286 Workaround is implemented in polling mode, so if last block of
4287 payload <128bit don't use DMA mode otherwise TAG is incorrectly generated . */
4288 /* Set the input and output addresses and start DMA transfer */
4289 if ((hcryp->Size % 16U) == 0U)
4290 {
4291 CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size / 4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
4292 }
4293 else /*to compute last word<128bits, otherwise it will not be encrypted/decrypted */
4294 {
4295 wordsize = (uint32_t)(hcryp->Size) + (16U - ((uint32_t)(hcryp->Size) % 16U)) ;
4296
4297 /* Set the input and output addresses and start DMA transfer, pCrypOutBuffPtr size should be %4 */
4298 CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), ((uint16_t)wordsize / 4U),
4299 (uint32_t)(hcryp->pCrypOutBuffPtr));
4300 }
4301 }
4302 else
4303 {
4304 /* Process unLocked */
4305 __HAL_UNLOCK(hcryp);
4306
4307 /* Change the CRYP state and phase */
4308 hcryp->State = HAL_CRYP_STATE_READY;
4309 }
4310
4311 /* Return function status */
4312 return HAL_OK;
4313 }
4314
4315
4316 /**
4317 * @brief AES CCM encryption/decryption processing in polling mode
4318 * for TinyAES IP, no encrypt/decrypt performed, only authentication preparation.
4319 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
4320 * the configuration information for CRYP module
4321 * @param Timeout: Timeout duration
4322 * @retval HAL status
4323 */
CRYP_AESCCM_Process(CRYP_HandleTypeDef * hcryp,uint32_t Timeout)4324 static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
4325 {
4326 uint32_t tickstart;
4327 uint32_t wordsize = (uint32_t)(hcryp->Size) / 4U;
4328 uint16_t outcount; /* Temporary CrypOutCount Value */
4329 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
4330 #if defined(AES)
4331 uint32_t loopcounter;
4332 uint32_t npblb;
4333 uint32_t lastwordsize;
4334 #endif /* AES */
4335
4336 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
4337 {
4338 if (hcryp->KeyIVConfig == 1U)
4339 {
4340 /* If the Key and IV configuration has to be done only once
4341 and if it has already been done, skip it */
4342 DoKeyIVConfig = 0U;
4343 hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
4344 }
4345 else
4346 {
4347 /* If the Key and IV configuration has to be done only once
4348 and if it has not been done already, do it and set KeyIVConfig
4349 to keep track it won't have to be done again next time */
4350 hcryp->KeyIVConfig = 1U;
4351 hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
4352 }
4353 }
4354 else
4355 {
4356 hcryp->SizesSum = hcryp->Size;
4357 }
4358
4359 if (DoKeyIVConfig == 1U)
4360 {
4361
4362 /* Reset CrypHeaderCount */
4363 hcryp->CrypHeaderCount = 0U;
4364
4365 #if defined(CRYP)
4366
4367 /********************** Init phase ******************************************/
4368
4369 CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
4370
4371 /* Set the key */
4372 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
4373
4374 /* Set the initialization vector (IV) with CTR1 information */
4375 hcryp->Instance->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0;
4376 hcryp->Instance->IV0RR = hcryp->Init.B0[1];
4377 hcryp->Instance->IV1LR = hcryp->Init.B0[2];
4378 hcryp->Instance->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1) | CRYP_CCM_CTR1_2;
4379
4380
4381 /* Enable the CRYP peripheral */
4382 __HAL_CRYP_ENABLE(hcryp);
4383
4384 /*Write B0 packet into CRYP_DIN Register*/
4385 if (hcryp->Init.DataType == CRYP_DATATYPE_8B)
4386 {
4387 hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0));
4388 hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 1));
4389 hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 2));
4390 hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 3));
4391 }
4392 else if (hcryp->Init.DataType == CRYP_DATATYPE_16B)
4393 {
4394 hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0), 16);
4395 hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 1), 16);
4396 hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 2), 16);
4397 hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 3), 16);
4398 }
4399 else if (hcryp->Init.DataType == CRYP_DATATYPE_1B)
4400 {
4401 hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0));
4402 hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 1));
4403 hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 2));
4404 hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 3));
4405 }
4406 else
4407 {
4408 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0);
4409 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 1);
4410 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 2);
4411 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 3);
4412 }
4413 /* Get tick */
4414 tickstart = HAL_GetTick();
4415
4416 /*Wait for the CRYPEN bit to be cleared*/
4417 while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN)
4418 {
4419 /* Check for the Timeout */
4420 if (Timeout != HAL_MAX_DELAY)
4421 {
4422 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
4423 {
4424 /* Disable the CRYP peripheral clock */
4425 __HAL_CRYP_DISABLE(hcryp);
4426
4427 /* Change state */
4428 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4429 hcryp->State = HAL_CRYP_STATE_READY;
4430
4431 /* Process unlocked */
4432 __HAL_UNLOCK(hcryp);
4433 return HAL_ERROR;
4434 }
4435 }
4436 }
4437 #else /* AES */
4438 /*AES2v1.1.1 : CCM authentication : no init phase, only header and final phase */
4439 /* Select header phase */
4440 CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
4441
4442 /* configured encryption mode */
4443 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
4444
4445 /* Set the key */
4446 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
4447
4448 /* Set the initialization vector with zero values*/
4449 hcryp->Instance->IVR3 = 0U;
4450 hcryp->Instance->IVR2 = 0U;
4451 hcryp->Instance->IVR1 = 0U;
4452 hcryp->Instance->IVR0 = 0U;
4453
4454 /* Enable the CRYP peripheral */
4455 __HAL_CRYP_ENABLE(hcryp);
4456
4457 /*Write the B0 packet into CRYP_DIN*/
4458 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0);
4459 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 1);
4460 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 2);
4461 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 3);
4462
4463 /* wait until the end of computation */
4464 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
4465 {
4466 /* Change state */
4467 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4468 hcryp->State = HAL_CRYP_STATE_READY;
4469
4470 /* Process unlocked & return error */
4471 __HAL_UNLOCK(hcryp);
4472 return HAL_ERROR;
4473 }
4474 /* Clear CCF flag */
4475 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
4476
4477 /* Set the phase */
4478 hcryp->Phase = CRYP_PHASE_PROCESS;
4479
4480 /* From that point the whole message must be processed, first the Header then the payload.
4481 First the Header block(B1) : associated data length expressed in bytes concatenated with Associated Data (A)*/
4482
4483 if (hcryp->Init.HeaderSize != 0U)
4484 {
4485 if ((hcryp->Init.HeaderSize % 4U) == 0U)
4486 {
4487 /* HeaderSize %4, no padding */
4488 for (loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter += 4U)
4489 {
4490 /* Write the Input block in the Data Input register */
4491 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4492 hcryp->CrypHeaderCount++ ;
4493 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4494 hcryp->CrypHeaderCount++ ;
4495 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4496 hcryp->CrypHeaderCount++ ;
4497 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4498 hcryp->CrypHeaderCount++ ;
4499
4500 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
4501 {
4502 /* Disable the CRYP peripheral clock */
4503 __HAL_CRYP_DISABLE(hcryp);
4504
4505 /* Change state */
4506 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4507 hcryp->State = HAL_CRYP_STATE_READY;
4508
4509 /* Process unlocked */
4510 __HAL_UNLOCK(hcryp);
4511 return HAL_ERROR;
4512 }
4513 /* Clear CCF Flag */
4514 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
4515 }
4516 }
4517 else
4518 {
4519 /*Write Header block in the IN FIFO without last block */
4520 for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U))); loopcounter += 4U)
4521 {
4522 /* Write the input block in the data input register */
4523 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4524 hcryp->CrypHeaderCount++ ;
4525 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4526 hcryp->CrypHeaderCount++ ;
4527 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4528 hcryp->CrypHeaderCount++ ;
4529 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4530 hcryp->CrypHeaderCount++ ;
4531
4532 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
4533 {
4534 /* Disable the CRYP peripheral clock */
4535 __HAL_CRYP_DISABLE(hcryp);
4536
4537 /* Change state */
4538 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4539 hcryp->State = HAL_CRYP_STATE_READY;
4540
4541 /* Process unlocked */
4542 __HAL_UNLOCK(hcryp);
4543 return HAL_ERROR;
4544 }
4545 /* Clear CCF Flag */
4546 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
4547 }
4548 /* Last block optionally pad the data with zeros*/
4549 for (loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize % 4U)); loopcounter++)
4550 {
4551 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
4552 hcryp->CrypHeaderCount++ ;
4553 }
4554 while (loopcounter < 4U)
4555 {
4556 /* Pad the data with zeros to have a complete block */
4557 hcryp->Instance->DINR = 0x0U;
4558 loopcounter++;
4559 }
4560
4561 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
4562 {
4563 /* Disable the CRYP peripheral clock */
4564 __HAL_CRYP_DISABLE(hcryp);
4565
4566 /* Change state */
4567 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4568 hcryp->State = HAL_CRYP_STATE_READY;
4569
4570 /* Process unlocked */
4571 __HAL_UNLOCK(hcryp);
4572 return HAL_ERROR;
4573 }
4574 /* Clear CCF flag */
4575 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
4576 }
4577 }
4578 } /* if (DoKeyIVConfig == 1U) */
4579 /* Then the payload: cleartext payload (not the ciphertext payload).
4580 Write input Data, no output Data to get */
4581 if (hcryp->Size != 0U)
4582 {
4583 if ((hcryp->Size % 16U) != 0U)
4584 {
4585 /* recalculate wordsize */
4586 wordsize = ((wordsize / 4U) * 4U) ;
4587 }
4588
4589 /* Get tick */
4590 tickstart = HAL_GetTick();
4591 /*Temporary CrypOutCount Value*/
4592 outcount = hcryp->CrypOutCount;
4593
4594 while ((hcryp->CrypInCount < wordsize) && (outcount < wordsize))
4595 {
4596 /* Write plain data and get cipher data */
4597 CRYP_AES_ProcessData(hcryp, Timeout);
4598
4599 /*Temporary CrypOutCount Value*/
4600 outcount = hcryp->CrypOutCount;
4601
4602 /* Check for the Timeout */
4603 if (Timeout != HAL_MAX_DELAY)
4604 {
4605 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
4606 {
4607 /* Disable the CRYP peripheral clock */
4608 __HAL_CRYP_DISABLE(hcryp);
4609
4610 /* Change state */
4611 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4612 hcryp->State = HAL_CRYP_STATE_READY;
4613
4614 /* Process unlocked */
4615 __HAL_UNLOCK(hcryp);
4616 return HAL_ERROR;
4617 }
4618 }
4619 }
4620
4621 if ((hcryp->Size % 16U) != 0U)
4622 {
4623 /* Compute the number of padding bytes in last block of payload */
4624 npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size);
4625
4626 /* Number of valid words (lastwordsize) in last block */
4627 if ((npblb % 4U) == 0U)
4628 {
4629 lastwordsize = (16U - npblb) / 4U;
4630 }
4631 else
4632 {
4633 lastwordsize = ((16U - npblb) / 4U) + 1U;
4634 }
4635 /* Last block optionally pad the data with zeros*/
4636 for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter ++)
4637 {
4638 /* Write the last input block in the IN FIFO */
4639 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
4640 hcryp->CrypInCount++;
4641 }
4642 while (loopcounter < 4U)
4643 {
4644 /* Pad the data with zeros to have a complete block */
4645 hcryp->Instance->DINR = 0U;
4646 loopcounter++;
4647 }
4648 /* Wait for CCF flag to be raised */
4649 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
4650 {
4651 /* Disable the CRYP peripheral clock */
4652 __HAL_CRYP_DISABLE(hcryp);
4653
4654 /* Change state */
4655 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4656 hcryp->State = HAL_CRYP_STATE_READY;
4657
4658 /* Process unlocked */
4659 __HAL_UNLOCK(hcryp);
4660 return HAL_ERROR;
4661 }
4662 /* Clear CCF flag */
4663 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
4664
4665 }
4666 }
4667 #endif /* End AES or CRYP */
4668
4669 #if defined(CRYP)
4670
4671 /************************* Header phase *************************************/
4672 /* Header block(B1) : associated data length expressed in bytes concatenated
4673 with Associated Data (A)*/
4674
4675 if (CRYP_GCMCCM_SetHeaderPhase(hcryp, Timeout) != HAL_OK)
4676 {
4677 return HAL_ERROR;
4678 }
4679
4680 /********************** Payload phase ***************************************/
4681
4682 /* Set the phase */
4683 hcryp->Phase = CRYP_PHASE_PROCESS;
4684
4685 /* Disable the CRYP peripheral */
4686 __HAL_CRYP_DISABLE(hcryp);
4687
4688 /* Select payload phase once the header phase is performed */
4689 CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
4690
4691 /* Enable the CRYP peripheral */
4692 __HAL_CRYP_ENABLE(hcryp);
4693
4694 } /* if (DoKeyIVConfig == 1U) */
4695
4696 if ((hcryp->Size % 16U) != 0U)
4697 {
4698 /* recalculate wordsize */
4699 wordsize = ((wordsize / 4U) * 4U) ;
4700 }
4701 /* Get tick */
4702 tickstart = HAL_GetTick();
4703 /*Temporary CrypOutCount Value*/
4704 outcount = hcryp->CrypOutCount;
4705
4706 /* Write input data and get output data */
4707 while ((hcryp->CrypInCount < wordsize) && (outcount < wordsize))
4708 {
4709 /* Write plain data and get cipher data */
4710 CRYP_AES_ProcessData(hcryp, Timeout);
4711
4712 /* Check for the Timeout */
4713 if (Timeout != HAL_MAX_DELAY)
4714 {
4715 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
4716 {
4717 /* Disable the CRYP peripheral clock */
4718 __HAL_CRYP_DISABLE(hcryp);
4719
4720 /* Change state */
4721 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4722 hcryp->State = HAL_CRYP_STATE_READY;
4723
4724 /* Process unlocked */
4725 __HAL_UNLOCK(hcryp);
4726 return HAL_ERROR;
4727 }
4728 }
4729 }
4730
4731 if ((hcryp->Size % 16U) != 0U)
4732 {
4733 /* CRYP Workaround : CRYP1 generates correct TAG during CCM decryption only when ciphertext blocks size is multiple of
4734 128 bits. If lthe size of the last block of payload is inferior to 128 bits, when CCM decryption
4735 is selected, then the TAG message will be wrong.*/
4736 CRYP_Workaround(hcryp, Timeout);
4737 }
4738 #endif /* CRYP */
4739
4740 /* Return function status */
4741 return HAL_OK;
4742 }
4743
4744 /**
4745 * @brief AES CCM encryption/decryption process in interrupt mode
4746 * for TinyAES IP, no encrypt/decrypt performed, only authentication preparation.
4747 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
4748 * the configuration information for CRYP module
4749 * @retval HAL status
4750 */
4751 static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp)
4752 {
4753 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
4754 #if defined(CRYP)
4755 __IO uint32_t count = 0U;
4756 #endif /* CRYP */
4757
4758 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
4759 {
4760 if (hcryp->KeyIVConfig == 1U)
4761 {
4762 /* If the Key and IV configuration has to be done only once
4763 and if it has already been done, skip it */
4764 DoKeyIVConfig = 0U;
4765 hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
4766 }
4767 else
4768 {
4769 /* If the Key and IV configuration has to be done only once
4770 and if it has not been done already, do it and set KeyIVConfig
4771 to keep track it won't have to be done again next time */
4772 hcryp->KeyIVConfig = 1U;
4773 hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
4774 }
4775 }
4776 else
4777 {
4778 hcryp->SizesSum = hcryp->Size;
4779 }
4780
4781 /* Configure Key, IV and process message (header and payload) */
4782 if (DoKeyIVConfig == 1U)
4783 {
4784 /* Reset CrypHeaderCount */
4785 hcryp->CrypHeaderCount = 0U;
4786
4787 #if defined(CRYP)
4788
4789 /************ Init phase ************/
4790
4791 CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
4792
4793 /* Set the key */
4794 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
4795
4796 /* Set the initialization vector (IV) with CTR1 information */
4797 hcryp->Instance->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0;
4798 hcryp->Instance->IV0RR = hcryp->Init.B0[1];
4799 hcryp->Instance->IV1LR = hcryp->Init.B0[2];
4800 hcryp->Instance->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1) | CRYP_CCM_CTR1_2;
4801
4802 /* Enable the CRYP peripheral */
4803 __HAL_CRYP_ENABLE(hcryp);
4804
4805 /*Write the B0 packet into CRYP_DIN Register*/
4806 if (hcryp->Init.DataType == CRYP_DATATYPE_8B)
4807 {
4808 hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0));
4809 hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 1));
4810 hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 2));
4811 hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 3));
4812 }
4813 else if (hcryp->Init.DataType == CRYP_DATATYPE_16B)
4814 {
4815 hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0), 16);
4816 hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 1), 16);
4817 hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 2), 16);
4818 hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 3), 16);
4819 }
4820 else if (hcryp->Init.DataType == CRYP_DATATYPE_1B)
4821 {
4822 hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0));
4823 hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 1));
4824 hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 2));
4825 hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 3));
4826 }
4827 else
4828 {
4829 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0);
4830 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 1);
4831 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 2);
4832 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 3);
4833 }
4834 /*Wait for the CRYPEN bit to be cleared*/
4835 count = CRYP_TIMEOUT_GCMCCMINITPHASE;
4836 do
4837 {
4838 count-- ;
4839 if (count == 0U)
4840 {
4841 /* Disable the CRYP peripheral clock */
4842 __HAL_CRYP_DISABLE(hcryp);
4843
4844 /* Change state */
4845 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
4846 hcryp->State = HAL_CRYP_STATE_READY;
4847
4848 /* Process unlocked */
4849 __HAL_UNLOCK(hcryp);
4850 return HAL_ERROR;
4851 }
4852 } while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN);
4853
4854 /* Select header phase */
4855 CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
4856
4857 } /* end of if (DoKeyIVConfig == 1U) */
4858
4859 /* Enable interrupts */
4860 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI);
4861
4862 /* Enable CRYP */
4863 __HAL_CRYP_ENABLE(hcryp);
4864
4865 #else /* AES */
4866
4867 /*AES2v1.1.1 : CCM authentication : no init phase, only header and final phase */
4868 /* Select header phase */
4869 CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
4870
4871 /* configured mode and encryption mode */
4872 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
4873
4874 /* Set the key */
4875 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
4876
4877 /* Set the initialization vector with zero values*/
4878 hcryp->Instance->IVR3 = 0U;
4879 hcryp->Instance->IVR2 = 0U;
4880 hcryp->Instance->IVR1 = 0U;
4881 hcryp->Instance->IVR0 = 0U;
4882
4883 /* Enable interrupts */
4884 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
4885 /* Enable the CRYP peripheral */
4886 __HAL_CRYP_ENABLE(hcryp);
4887
4888 /*Write the B0 packet into CRYP_DIN*/
4889 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0);
4890 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 1);
4891 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 2);
4892 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 3);
4893
4894 } /* end of if (DoKeyIVConfig == 1U) */
4895 #endif /* End AES or CRYP */
4896
4897 /* Return function status */
4898 return HAL_OK;
4899 }
4900 /**
4901 * @brief AES CCM encryption/decryption process in DMA mode
4902 * for TinyAES IP, no encrypt/decrypt performed, only authentication preparation.
4903 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
4904 * the configuration information for CRYP module
4905 * @retval HAL status
4906 */
4907 static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp)
4908 {
4909 uint32_t wordsize;
4910 __IO uint32_t count = 0U;
4911 uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */
4912 #if defined(AES)
4913 uint32_t loopcounter;
4914 uint32_t npblb;
4915 uint32_t lastwordsize;
4916 #endif
4917
4918 if (hcryp->Init.KeyIVConfigSkip == CRYP_KEYIVCONFIG_ONCE)
4919 {
4920 if (hcryp->KeyIVConfig == 1U)
4921 {
4922 /* If the Key and IV configuration has to be done only once
4923 and if it has already been done, skip it */
4924 DoKeyIVConfig = 0U;
4925 hcryp->SizesSum += hcryp->Size; /* Compute message total payload length */
4926 }
4927 else
4928 {
4929 /* If the Key and IV configuration has to be done only once
4930 and if it has not been done already, do it and set KeyIVConfig
4931 to keep track it won't have to be done again next time */
4932 hcryp->KeyIVConfig = 1U;
4933 hcryp->SizesSum = hcryp->Size; /* Merely store payload length */
4934 }
4935 }
4936 else
4937 {
4938 hcryp->SizesSum = hcryp->Size;
4939 }
4940
4941 if (DoKeyIVConfig == 1U)
4942 {
4943
4944 /* Reset CrypHeaderCount */
4945 hcryp->CrypHeaderCount = 0U;
4946
4947 #if defined(CRYP)
4948
4949 /************************** Init phase **************************************/
4950
4951 CRYP_SET_PHASE(hcryp, CRYP_PHASE_INIT);
4952
4953 /* Set the key */
4954 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
4955
4956 /* Set the initialization vector (IV) with CTR1 information */
4957 hcryp->Instance->IV0LR = (hcryp->Init.B0[0]) & CRYP_CCM_CTR1_0;
4958 hcryp->Instance->IV0RR = hcryp->Init.B0[1];
4959 hcryp->Instance->IV1LR = hcryp->Init.B0[2];
4960 hcryp->Instance->IV1RR = (hcryp->Init.B0[3] & CRYP_CCM_CTR1_1) | CRYP_CCM_CTR1_2;
4961
4962 /* Enable the CRYP peripheral */
4963 __HAL_CRYP_ENABLE(hcryp);
4964
4965 /*Write the B0 packet into CRYP_DIN Register*/
4966 if (hcryp->Init.DataType == CRYP_DATATYPE_8B)
4967 {
4968 hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0));
4969 hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 1));
4970 hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 2));
4971 hcryp->Instance->DIN = __REV(*(uint32_t *)(hcryp->Init.B0 + 3));
4972 }
4973 else if (hcryp->Init.DataType == CRYP_DATATYPE_16B)
4974 {
4975 hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0), 16);
4976 hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 1), 16);
4977 hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 2), 16);
4978 hcryp->Instance->DIN = __ROR(*(uint32_t *)(hcryp->Init.B0 + 3), 16);
4979 }
4980 else if (hcryp->Init.DataType == CRYP_DATATYPE_1B)
4981 {
4982 hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0));
4983 hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 1));
4984 hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 2));
4985 hcryp->Instance->DIN = __RBIT(*(uint32_t *)(hcryp->Init.B0 + 3));
4986 }
4987 else
4988 {
4989 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0);
4990 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 1);
4991 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 2);
4992 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.B0 + 3);
4993 }
4994
4995 /*Wait for the CRYPEN bit to be cleared*/
4996 count = CRYP_TIMEOUT_GCMCCMINITPHASE;
4997 do
4998 {
4999 count-- ;
5000 if (count == 0U)
5001 {
5002 /* Disable the CRYP peripheral clock */
5003 __HAL_CRYP_DISABLE(hcryp);
5004
5005 /* Change state */
5006 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5007 hcryp->State = HAL_CRYP_STATE_READY;
5008
5009 /* Process unlocked */
5010 __HAL_UNLOCK(hcryp);
5011 return HAL_ERROR;
5012 }
5013 } while ((hcryp->Instance->CR & CRYP_CR_CRYPEN) == CRYP_CR_CRYPEN);
5014
5015 #else /* AES */
5016
5017 /*AES2v1.1.1 : CCM authentication : no init phase, only header and final phase */
5018 /* Select header phase */
5019 CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
5020
5021 /* configured encryption mode */
5022 MODIFY_REG(hcryp->Instance->CR, AES_CR_MODE, CRYP_OPERATINGMODE_ENCRYPT);
5023
5024 /* Set the key */
5025 CRYP_SetKey(hcryp, hcryp->Init.KeySize);
5026
5027 /* Set the initialization vector with zero values*/
5028 hcryp->Instance->IVR3 = 0U;
5029 hcryp->Instance->IVR2 = 0U;
5030 hcryp->Instance->IVR1 = 0U;
5031 hcryp->Instance->IVR0 = 0U;
5032
5033 /* Enable the CRYP peripheral */
5034 __HAL_CRYP_ENABLE(hcryp);
5035
5036 /*Write the B0 packet into CRYP_DIN*/
5037 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0);
5038 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 1);
5039 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 2);
5040 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.B0 + 3);
5041
5042 count = CRYP_TIMEOUT_GCMCCMINITPHASE;
5043 do
5044 {
5045 count-- ;
5046 if (count == 0U)
5047 {
5048 /* Disable the CRYP peripheral clock */
5049 __HAL_CRYP_DISABLE(hcryp);
5050
5051 /* Change state */
5052 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5053 hcryp->State = HAL_CRYP_STATE_READY;
5054
5055 /* Process Unlocked */
5056 __HAL_UNLOCK(hcryp);
5057 return HAL_ERROR;
5058 }
5059 } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
5060 /* Clear CCF flag */
5061 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
5062
5063 /* Set the phase */
5064 hcryp->Phase = CRYP_PHASE_PROCESS;
5065
5066 /* From that point the whole message must be processed, first the Header then the payload.
5067 First the Header block(B1) : associated data length expressed in bytes concatenated with Associated Data (A)*/
5068
5069 if (hcryp->Init.HeaderSize != 0U)
5070 {
5071 if ((hcryp->Init.HeaderSize % 4U) == 0U)
5072 {
5073 /* HeaderSize %4, no padding */
5074 for (loopcounter = 0U; (loopcounter < hcryp->Init.HeaderSize); loopcounter += 4U)
5075 {
5076 /* Write the Input block in the Data Input register */
5077 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5078 hcryp->CrypHeaderCount++ ;
5079 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5080 hcryp->CrypHeaderCount++ ;
5081 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5082 hcryp->CrypHeaderCount++ ;
5083 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5084 hcryp->CrypHeaderCount++ ;
5085
5086 /* wait until the end of computation */
5087 count = CRYP_TIMEOUT_GCMCCMINITPHASE;
5088 do
5089 {
5090 count-- ;
5091 if (count == 0U)
5092 {
5093 /* Disable the CRYP peripheral clock */
5094 __HAL_CRYP_DISABLE(hcryp);
5095
5096 /* Change state */
5097 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5098 hcryp->State = HAL_CRYP_STATE_READY;
5099
5100 /* Process Unlocked */
5101 __HAL_UNLOCK(hcryp);
5102 return HAL_ERROR;
5103 }
5104 } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
5105 /* Clear CCF flag */
5106 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
5107 }
5108 }
5109 else
5110 {
5111 /*Write Header block in the IN FIFO without last block */
5112 for (loopcounter = 0U; (loopcounter < ((hcryp->Init.HeaderSize) - (hcryp->Init.HeaderSize % 4U))); loopcounter += 4U)
5113 {
5114 /* Write the input block in the data input register */
5115 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5116 hcryp->CrypHeaderCount++ ;
5117 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5118 hcryp->CrypHeaderCount++ ;
5119 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5120 hcryp->CrypHeaderCount++ ;
5121 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5122 hcryp->CrypHeaderCount++ ;
5123
5124 count = CRYP_TIMEOUT_GCMCCMINITPHASE;
5125 do
5126 {
5127 count-- ;
5128 if (count == 0U)
5129 {
5130 /* Disable the CRYP peripheral clock */
5131 __HAL_CRYP_DISABLE(hcryp);
5132
5133 /* Change state */
5134 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5135 hcryp->State = HAL_CRYP_STATE_READY;
5136
5137 /* Process Unlocked */
5138 __HAL_UNLOCK(hcryp);
5139 return HAL_ERROR;
5140 }
5141 } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
5142 /* Clear CCF flag */
5143 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
5144 }
5145 /* Last block optionally pad the data with zeros*/
5146 for (loopcounter = 0U; (loopcounter < (hcryp->Init.HeaderSize % 4U)); loopcounter++)
5147 {
5148 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5149 hcryp->CrypHeaderCount++ ;
5150 }
5151 while (loopcounter < 4U)
5152 {
5153 /* Pad the data with zeros to have a complete block */
5154 hcryp->Instance->DINR = 0x0U;
5155 loopcounter++;
5156 }
5157
5158 count = CRYP_TIMEOUT_GCMCCMINITPHASE;
5159 do
5160 {
5161 count-- ;
5162 if (count == 0U)
5163 {
5164 /* Disable the CRYP peripheral clock */
5165 __HAL_CRYP_DISABLE(hcryp);
5166
5167 /* Change state */
5168 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5169 hcryp->State = HAL_CRYP_STATE_READY;
5170
5171 /* Process Unlocked */
5172 __HAL_UNLOCK(hcryp);
5173 return HAL_ERROR;
5174 }
5175 } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
5176 /* Clear CCF flag */
5177 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
5178 }
5179 }
5180 } /* if (DoKeyIVConfig == 1U) */
5181 /* Then the payload: cleartext payload (not the ciphertext payload).
5182 Write input Data, no output Data to get */
5183 if (hcryp->Size != 0U)
5184 {
5185 if (hcryp->Size >= 16U)
5186 {
5187 if ((hcryp->Size % 16U) == 0U)
5188 {
5189 CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (hcryp->Size / 4U), (uint32_t)(hcryp->pCrypOutBuffPtr));
5190 }
5191 else /*to compute last word<128bits, otherwise it will not be encrypted/decrypted */
5192 {
5193 wordsize = (uint32_t)(hcryp->Size) + (16U - ((uint32_t)(hcryp->Size) % 16U)) ;
5194
5195 /* Set the input and output addresses and start DMA transfer, pCrypOutBuffPtr size should be %4 */
5196 CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), ((uint16_t)wordsize / 4U),
5197 (uint32_t)(hcryp->pCrypOutBuffPtr));
5198 }
5199 }
5200 if ((hcryp->Size < 16U) != 0U)
5201 {
5202 /* Compute the number of padding bytes in last block of payload */
5203 npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size);
5204
5205 /* Number of valid words (lastwordsize) in last block */
5206 if ((npblb % 4U) == 0U)
5207 {
5208 lastwordsize = (16U - npblb) / 4U;
5209 }
5210 else
5211 {
5212 lastwordsize = ((16U - npblb) / 4U) + 1U;
5213 }
5214 /* Last block optionally pad the data with zeros*/
5215 for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter ++)
5216 {
5217 /* Write the last input block in the IN FIFO */
5218 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
5219 hcryp->CrypInCount++;
5220 }
5221 while (loopcounter < 4U)
5222 {
5223 /* Pad the data with zeros to have a complete block */
5224 hcryp->Instance->DINR = 0U;
5225 loopcounter++;
5226 }
5227 count = CRYP_TIMEOUT_GCMCCMINITPHASE;
5228 do
5229 {
5230 count-- ;
5231 if (count == 0U)
5232 {
5233 /* Disable the CRYP peripheral clock */
5234 __HAL_CRYP_DISABLE(hcryp);
5235
5236 /* Change state */
5237 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5238 hcryp->State = HAL_CRYP_STATE_READY;
5239
5240 /* Process Unlocked */
5241 __HAL_UNLOCK(hcryp);
5242 return HAL_ERROR;
5243 }
5244 } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
5245 /* Clear CCF flag */
5246 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
5247
5248 /* Process unlocked */
5249 __HAL_UNLOCK(hcryp);
5250
5251 /* Change the CRYP state and phase */
5252 hcryp->State = HAL_CRYP_STATE_READY;
5253 }
5254 }
5255 else
5256 {
5257 /* Process unLocked */
5258 __HAL_UNLOCK(hcryp);
5259
5260 /* Change the CRYP state and phase */
5261 hcryp->State = HAL_CRYP_STATE_READY;
5262 }
5263 #endif /* AES */
5264 #if defined(CRYP)
5265 /********************* Header phase *****************************************/
5266
5267 if (CRYP_GCMCCM_SetHeaderPhase_DMA(hcryp) != HAL_OK)
5268 {
5269 return HAL_ERROR;
5270 }
5271
5272 /******************** Payload phase *****************************************/
5273
5274 /* Set the phase */
5275 hcryp->Phase = CRYP_PHASE_PROCESS;
5276
5277 /* Disable the CRYP peripheral */
5278 __HAL_CRYP_DISABLE(hcryp);
5279
5280 /* Select payload phase once the header phase is performed */
5281 CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
5282
5283 } /* if (DoKeyIVConfig == 1U) */
5284 if (hcryp->Size != 0U)
5285 {
5286 /* Size should be %4 otherwise Tag will be incorrectly generated for GCM Encryption & CCM Decryption
5287 Workaround is implemented in polling mode, so if last block of
5288 payload <128bit don't use HAL_CRYP_AESGCM_DMA otherwise TAG is incorrectly generated for GCM Encryption. */
5289 /* Set the input and output addresses and start DMA transfer */
5290 if ((hcryp->Size % 16U) == 0U)
5291 {
5292 CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), hcryp->Size / 4U, (uint32_t)(hcryp->pCrypOutBuffPtr));
5293 }
5294 else
5295 {
5296 wordsize = (uint32_t)(hcryp->Size) + 16U - ((uint32_t)(hcryp->Size) % 16U) ;
5297
5298 /* Set the input and output addresses and start DMA transfer, pCrypOutBuffPtr size should be %4*/
5299 CRYP_SetDMAConfig(hcryp, (uint32_t)(hcryp->pCrypInBuffPtr), (uint16_t)wordsize / 4U,
5300 (uint32_t)(hcryp->pCrypOutBuffPtr));
5301 }
5302 }
5303 else /*Size = 0*/
5304 {
5305 /* Process unlocked */
5306 __HAL_UNLOCK(hcryp);
5307
5308 /* Change the CRYP state and phase */
5309 hcryp->State = HAL_CRYP_STATE_READY;
5310 }
5311 #endif /* CRYP */
5312 /* Return function status */
5313 return HAL_OK;
5314 }
5315
5316 /**
5317 * @brief Sets the payload phase in iterrupt mode
5318 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
5319 * the configuration information for CRYP module
5320 * @retval state
5321 */
5322 static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp)
5323 {
5324 uint32_t loopcounter;
5325 uint32_t temp[4]; /* Temporary CrypOutBuff */
5326 uint32_t lastwordsize;
5327 uint32_t npblb;
5328 uint32_t i;
5329 #if defined(AES)
5330 uint16_t outcount; /* Temporary CrypOutCount Value */
5331 #endif /* AES */
5332
5333 /***************************** Payload phase *******************************/
5334
5335 #if defined(CRYP)
5336 if (hcryp->Size == 0U)
5337 {
5338 /* Disable interrupts */
5339 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
5340
5341 /* Process unlocked */
5342 __HAL_UNLOCK(hcryp);
5343
5344 /* Change the CRYP state */
5345 hcryp->State = HAL_CRYP_STATE_READY;
5346 }
5347
5348 else if (((hcryp->Size / 4U) - (hcryp->CrypInCount)) >= 4U)
5349 {
5350 /* Write the input block in the IN FIFO */
5351 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
5352 hcryp->CrypInCount++;
5353 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
5354 hcryp->CrypInCount++;
5355 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
5356 hcryp->CrypInCount++;
5357 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
5358 hcryp->CrypInCount++;
5359 if (((hcryp->Size / 4U) == hcryp->CrypInCount) && ((hcryp->Size % 16U) == 0U))
5360 {
5361 /* Disable interrupts */
5362 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
5363
5364 /* Call the input data transfer complete callback */
5365 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
5366 /*Call registered Input complete callback*/
5367 hcryp->InCpltCallback(hcryp);
5368 #else
5369 /*Call legacy weak Input complete callback*/
5370 HAL_CRYP_InCpltCallback(hcryp);
5371 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
5372 }
5373 if (hcryp->CrypOutCount < (hcryp->Size / 4U))
5374 {
5375 /* Read the output block from the Output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer */
5376 for (i = 0U; i < 4U; i++)
5377 {
5378 temp[i] = hcryp->Instance->DOUT;
5379 }
5380 i = 0U;
5381 while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 4U))
5382 {
5383 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
5384 hcryp->CrypOutCount++;
5385 i++;
5386 }
5387 if (((hcryp->Size / 4U) == hcryp->CrypOutCount) && ((hcryp->Size % 16U) == 0U))
5388 {
5389 /* Disable interrupts */
5390 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI);
5391
5392 /* Change the CRYP state */
5393 hcryp->State = HAL_CRYP_STATE_READY;
5394
5395 /* Disable CRYP */
5396 __HAL_CRYP_DISABLE(hcryp);
5397
5398 /* Process unlocked */
5399 __HAL_UNLOCK(hcryp);
5400
5401 /* Call output transfer complete callback */
5402 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
5403 /*Call registered Output complete callback*/
5404 hcryp->OutCpltCallback(hcryp);
5405 #else
5406 /*Call legacy weak Output complete callback*/
5407 HAL_CRYP_OutCpltCallback(hcryp);
5408 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
5409 }
5410 }
5411 }
5412 else if ((hcryp->Size % 16U) != 0U)
5413 {
5414 /* Size should be %4 in word and %16 in byte otherwise TAG will be incorrectly generated for GCM Encryption & CCM Decryption
5415 Workaround is implemented in polling mode, so if last block of
5416 payload <128bit don't use CRYP_AESGCM_Encrypt_IT otherwise TAG is incorrectly generated. */
5417
5418 /* Compute the number of padding bytes in last block of payload */
5419 npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size);
5420
5421 /* Number of valid words (lastwordsize) in last block */
5422 if ((npblb % 4U) == 0U)
5423 {
5424 lastwordsize = (16U - npblb) / 4U;
5425 }
5426 else
5427 {
5428 lastwordsize = ((16U - npblb) / 4U) + 1U;
5429 }
5430
5431 /* Last block optionally pad the data with zeros*/
5432 for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
5433 {
5434 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
5435 hcryp->CrypInCount++;
5436 }
5437 while (loopcounter < 4U)
5438 {
5439 /* Pad the data with zeros to have a complete block */
5440 hcryp->Instance->DIN = 0x0U;
5441 loopcounter++;
5442 }
5443 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
5444
5445 if ((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U)
5446 {
5447 for (i = 0U; i < 4U; i++)
5448 {
5449 temp[i] = hcryp->Instance->DOUT;
5450 }
5451 if (((hcryp->Size) / 4U) == 0U)
5452 {
5453 for (i = 0U; i < ((uint32_t)(hcryp->Size) % 4U); i++)
5454 {
5455 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
5456 hcryp->CrypOutCount++;
5457 }
5458 }
5459 i = 0x0U;
5460 while (((hcryp->CrypOutCount < ((hcryp->Size) / 4U))) && (i < 4U))
5461 {
5462 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
5463 hcryp->CrypOutCount++;
5464 i++;
5465 }
5466 }
5467 if (hcryp->CrypOutCount >= (hcryp->Size / 4U))
5468 {
5469 /* Disable interrupts */
5470 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_OUTI | CRYP_IT_INI);
5471
5472 /* Change the CRYP peripheral state */
5473 hcryp->State = HAL_CRYP_STATE_READY;
5474
5475 /* Process unlocked */
5476 __HAL_UNLOCK(hcryp);
5477
5478 /* Call output transfer complete callback */
5479 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
5480 /*Call registered Output complete callback*/
5481 hcryp->OutCpltCallback(hcryp);
5482 #else
5483 /*Call legacy weak Output complete callback*/
5484 HAL_CRYP_OutCpltCallback(hcryp);
5485 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
5486 }
5487 }
5488 else
5489 {
5490 /* Nothing to do */
5491 }
5492 #else /* AES */
5493
5494 /* Read the output block from the output FIFO and put them in temporary buffer then get CrypOutBuff from temporary buffer*/
5495 for (i = 0U; i < 4U; i++)
5496 {
5497 temp[i] = hcryp->Instance->DOUTR;
5498 }
5499 i = 0U;
5500 while ((hcryp->CrypOutCount < ((hcryp->Size + 3U) / 4U)) && (i < 4U))
5501 {
5502 *(uint32_t *)(hcryp->pCrypOutBuffPtr + hcryp->CrypOutCount) = temp[i];
5503 hcryp->CrypOutCount++;
5504 i++;
5505 }
5506 /*Temporary CrypOutCount Value*/
5507 outcount = hcryp->CrypOutCount;
5508
5509 if ((hcryp->CrypOutCount >= (hcryp->Size / 4U)) && ((outcount * 4U) >= hcryp->Size))
5510 {
5511 /* Disable computation complete flag and errors interrupts */
5512 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
5513
5514 /* Change the CRYP state */
5515 hcryp->State = HAL_CRYP_STATE_READY;
5516
5517 /* Process unlocked */
5518 __HAL_UNLOCK(hcryp);
5519
5520 /* Call output transfer complete callback */
5521 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
5522 /*Call registered Output complete callback*/
5523 hcryp->OutCpltCallback(hcryp);
5524 #else
5525 /*Call legacy weak Output complete callback*/
5526 HAL_CRYP_OutCpltCallback(hcryp);
5527 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
5528 }
5529
5530 else if (((hcryp->Size / 4U) - (hcryp->CrypInCount)) >= 4U)
5531 {
5532 /* Write the input block in the IN FIFO */
5533 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
5534 hcryp->CrypInCount++;
5535 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
5536 hcryp->CrypInCount++;
5537 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
5538 hcryp->CrypInCount++;
5539 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
5540 hcryp->CrypInCount++;
5541 if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U))
5542 {
5543 /* Call Input transfer complete callback */
5544 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
5545 /*Call registered Input complete callback*/
5546 hcryp->InCpltCallback(hcryp);
5547 #else
5548 /*Call legacy weak Input complete callback*/
5549 HAL_CRYP_InCpltCallback(hcryp);
5550 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
5551 }
5552 }
5553 else /* Last block of payload < 128bit*/
5554 {
5555 /* Workaround not implemented, Size should be %4 otherwise Tag will be incorrectly
5556 generated for GCM Encryption & CCM Decryption. Workaround is implemented in polling mode, so if last block of
5557 payload <128bit don't use CRYP_Encrypt_IT otherwise TAG is incorrectly generated for GCM Encryption & CCM Decryption. */
5558
5559 /* Compute the number of padding bytes in last block of payload */
5560 npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size);
5561
5562 /* Number of valid words (lastwordsize) in last block */
5563 if ((npblb % 4U) == 0U)
5564 {
5565 lastwordsize = (16U - npblb) / 4U;
5566 }
5567 else
5568 {
5569 lastwordsize = ((16U - npblb) / 4U) + 1U;
5570 }
5571
5572 /* Last block optionally pad the data with zeros*/
5573 for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
5574 {
5575 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
5576 hcryp->CrypInCount++;
5577 }
5578 while (loopcounter < 4U)
5579 {
5580 /* pad the data with zeros to have a complete block */
5581 hcryp->Instance->DINR = 0x0U;
5582 loopcounter++;
5583 }
5584 }
5585 #endif /* AES */
5586
5587 }
5588
5589
5590 /**
5591 * @brief Sets the header phase in polling mode
5592 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
5593 * the configuration information for CRYP module(Header & HeaderSize)
5594 * @param Timeout: Timeout value
5595 * @retval state
5596 */
5597 static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
5598 {
5599 uint32_t loopcounter;
5600 uint32_t size_in_bytes;
5601 uint32_t tmp;
5602 uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */
5603 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
5604 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */
5605
5606 /***************************** Header phase for GCM/GMAC or CCM *********************************/
5607
5608 if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
5609 {
5610 size_in_bytes = hcryp->Init.HeaderSize * 4U;
5611 }
5612 else
5613 {
5614 size_in_bytes = hcryp->Init.HeaderSize;
5615 }
5616
5617 if (size_in_bytes != 0U)
5618 {
5619
5620 #if defined(CRYP)
5621
5622 /* Select header phase */
5623 CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
5624
5625 /* Enable the CRYP peripheral */
5626 __HAL_CRYP_ENABLE(hcryp);
5627
5628 if ((size_in_bytes % 16U) == 0U)
5629 {
5630 /* HeaderSize %4, no padding */
5631 for (loopcounter = 0U; (loopcounter < (size_in_bytes / 4U)); loopcounter += 4U)
5632 {
5633 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5634 hcryp->CrypHeaderCount++ ;
5635 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5636 hcryp->CrypHeaderCount++ ;
5637 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5638 hcryp->CrypHeaderCount++ ;
5639 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5640 hcryp->CrypHeaderCount++ ;
5641
5642 /* Wait for IFEM to be raised */
5643 if (CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK)
5644 {
5645 /* Disable the CRYP peripheral clock */
5646 __HAL_CRYP_DISABLE(hcryp);
5647
5648 /* Change state */
5649 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5650 hcryp->State = HAL_CRYP_STATE_READY;
5651
5652 /* Process unlocked */
5653 __HAL_UNLOCK(hcryp);
5654 return HAL_ERROR;
5655 }
5656 }
5657 }
5658 else
5659 {
5660 /*Write header block in the IN FIFO without last block */
5661 for (loopcounter = 0U; (loopcounter < ((size_in_bytes / 16U) * 4U)); loopcounter += 4U)
5662 {
5663 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5664 hcryp->CrypHeaderCount++ ;
5665 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5666 hcryp->CrypHeaderCount++ ;
5667 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5668 hcryp->CrypHeaderCount++ ;
5669 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5670 hcryp->CrypHeaderCount++ ;
5671
5672 /* Wait for IFEM to be raised */
5673 if (CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK)
5674 {
5675 /* Disable the CRYP peripheral clock */
5676 __HAL_CRYP_DISABLE(hcryp);
5677
5678 /* Change state */
5679 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5680 hcryp->State = HAL_CRYP_STATE_READY;
5681
5682 /* Process unlocked */
5683 __HAL_UNLOCK(hcryp);
5684 return HAL_ERROR;
5685 }
5686 }
5687 /* Last block optionally pad the data with zeros*/
5688 for (loopcounter = 0U; (loopcounter < ((size_in_bytes / 4U) % 4U)); loopcounter++)
5689 {
5690 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5691 hcryp->CrypHeaderCount++ ;
5692 }
5693 /* If the header size is a multiple of words */
5694 if ((size_in_bytes % 4U) == 0U)
5695 {
5696 /* Pad the data with zeros to have a complete block */
5697 while (loopcounter < 4U)
5698 {
5699 hcryp->Instance->DIN = 0x0U;
5700 loopcounter++;
5701 }
5702 }
5703 else
5704 {
5705 /* Enter last bytes, padded with zeroes */
5706 tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5707 tmp &= mask[(hcryp->Init.DataType * 2U) + (size_in_bytes % 4U)];
5708 hcryp->Instance->DIN = tmp;
5709 loopcounter++;
5710 /* Pad the data with zeros to have a complete block */
5711 while (loopcounter < 4U)
5712 {
5713 hcryp->Instance->DIN = 0x0U;
5714 loopcounter++;
5715 }
5716 }
5717 /* Wait for CCF IFEM to be raised */
5718 if (CRYP_WaitOnIFEMFlag(hcryp, Timeout) != HAL_OK)
5719 {
5720 /* Disable the CRYP peripheral clock */
5721 __HAL_CRYP_DISABLE(hcryp);
5722
5723 /* Change state */
5724 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5725 hcryp->State = HAL_CRYP_STATE_READY;
5726
5727 /* Process unlocked */
5728 __HAL_UNLOCK(hcryp);
5729 return HAL_ERROR;
5730 }
5731 }
5732 /* Wait until the complete message has been processed */
5733 if (CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK)
5734 {
5735 /* Disable the CRYP peripheral clock */
5736 __HAL_CRYP_DISABLE(hcryp);
5737
5738 /* Change state */
5739 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5740 hcryp->State = HAL_CRYP_STATE_READY;
5741
5742 /* Process unlocked & return error */
5743 __HAL_UNLOCK(hcryp);
5744 return HAL_ERROR;
5745 }
5746
5747 #else /* AES */
5748
5749 if (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)
5750 {
5751 /* Workaround 1 :only AES before re-enabling the IP, datatype can be configured.*/
5752 MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType);
5753
5754 /* Select header phase */
5755 CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
5756
5757 /* Enable the CRYP peripheral */
5758 __HAL_CRYP_ENABLE(hcryp);
5759
5760 }
5761 /* If size_in_bytes is a multiple of blocks (a multiple of four 32-bits words ) */
5762 if ((size_in_bytes % 16U) == 0U)
5763 {
5764 /* No padding */
5765 for (loopcounter = 0U; (loopcounter < (size_in_bytes / 4U)); loopcounter += 4U)
5766 {
5767 /* Write the input block in the data input register */
5768 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5769 hcryp->CrypHeaderCount++ ;
5770 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5771 hcryp->CrypHeaderCount++ ;
5772 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5773 hcryp->CrypHeaderCount++ ;
5774 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5775 hcryp->CrypHeaderCount++ ;
5776
5777 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
5778 {
5779 /* Disable the CRYP peripheral clock */
5780 __HAL_CRYP_DISABLE(hcryp);
5781
5782 /* Change state */
5783 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5784 hcryp->State = HAL_CRYP_STATE_READY;
5785
5786 /* Process unlocked */
5787 __HAL_UNLOCK(hcryp);
5788 return HAL_ERROR;
5789 }
5790 /* Clear CCF flag */
5791 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
5792 }
5793 }
5794 else
5795 {
5796 /*Write header block in the IN FIFO without last block */
5797 for (loopcounter = 0U; (loopcounter < ((size_in_bytes / 16U) * 4U)); loopcounter += 4U)
5798 {
5799 /* Write the input block in the data input register */
5800 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5801 hcryp->CrypHeaderCount++ ;
5802 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5803 hcryp->CrypHeaderCount++ ;
5804 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5805 hcryp->CrypHeaderCount++ ;
5806 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5807 hcryp->CrypHeaderCount++ ;
5808
5809 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
5810 {
5811 /* Disable the CRYP peripheral clock */
5812 __HAL_CRYP_DISABLE(hcryp);
5813
5814 /* Change state */
5815 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5816 hcryp->State = HAL_CRYP_STATE_READY;
5817
5818 /* Process unlocked */
5819 __HAL_UNLOCK(hcryp);
5820 return HAL_ERROR;
5821 }
5822 /* Clear CCF flag */
5823 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
5824 }
5825 /* Write last complete words */
5826 for (loopcounter = 0U; (loopcounter < ((size_in_bytes / 4U) % 4U)); loopcounter++)
5827 {
5828 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5829 hcryp->CrypHeaderCount++ ;
5830 }
5831 /* If the header size is a multiple of words */
5832 if ((size_in_bytes % 4U) == 0U)
5833 {
5834 /* Pad the data with zeros to have a complete block */
5835 while (loopcounter < 4U)
5836 {
5837 hcryp->Instance->DINR = 0x0U;
5838 loopcounter++;
5839 }
5840 }
5841 else
5842 {
5843 /* Enter last bytes, padded with zeroes */
5844 tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5845 tmp &= mask[(hcryp->Init.DataType * 2U) + (size_in_bytes % 4U)];
5846 hcryp->Instance->DINR = tmp;
5847 loopcounter++;
5848 /* Pad the data with zeros to have a complete block */
5849 while (loopcounter < 4U)
5850 {
5851 hcryp->Instance->DINR = 0x0U;
5852 loopcounter++;
5853 }
5854 }
5855
5856 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
5857 {
5858 /* Disable the CRYP peripheral clock */
5859 __HAL_CRYP_DISABLE(hcryp);
5860
5861 /* Change state */
5862 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5863 hcryp->State = HAL_CRYP_STATE_READY;
5864
5865 /* Process unlocked */
5866 __HAL_UNLOCK(hcryp);
5867 return HAL_ERROR;
5868 }
5869 /* Clear CCF flag */
5870 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
5871 }
5872 #endif /* End AES or CRYP */
5873 }
5874 else
5875 {
5876 #if defined(AES)
5877 if (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)
5878 {
5879 /*Workaround 1: only AES, before re-enabling the IP, datatype can be configured.*/
5880 MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType);
5881
5882 /* Select header phase */
5883 CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
5884
5885 /* Enable the CRYP peripheral */
5886 __HAL_CRYP_ENABLE(hcryp);
5887 }
5888 #endif /* AES */
5889 }
5890 /* Return function status */
5891 return HAL_OK;
5892 }
5893
5894 /**
5895 * @brief Sets the header phase when using DMA in process
5896 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
5897 * the configuration information for CRYP module(Header & HeaderSize)
5898 * @retval None
5899 */
5900 static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcryp)
5901 {
5902 __IO uint32_t count = 0U;
5903 uint32_t loopcounter;
5904 uint32_t headersize_in_bytes;
5905 uint32_t tmp;
5906 uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */
5907 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
5908 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */
5909
5910 /***************************** Header phase for GCM/GMAC or CCM *********************************/
5911 if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
5912 {
5913 headersize_in_bytes = hcryp->Init.HeaderSize * 4U;
5914 }
5915 else
5916 {
5917 headersize_in_bytes = hcryp->Init.HeaderSize;
5918 }
5919
5920 if (headersize_in_bytes != 0U)
5921 {
5922
5923 #if defined(CRYP)
5924
5925 /* Select header phase */
5926 CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
5927
5928 /* Enable the CRYP peripheral */
5929 __HAL_CRYP_ENABLE(hcryp);
5930
5931 if ((headersize_in_bytes % 16U) == 0U)
5932 {
5933 /* HeaderSize %4, no padding */
5934 for (loopcounter = 0U; (loopcounter < (headersize_in_bytes / 4U)); loopcounter += 4U)
5935 {
5936 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5937 hcryp->CrypHeaderCount++ ;
5938 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5939 hcryp->CrypHeaderCount++ ;
5940 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5941 hcryp->CrypHeaderCount++ ;
5942 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5943 hcryp->CrypHeaderCount++ ;
5944
5945 /* Wait for IFEM to be raised */
5946 count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
5947 do
5948 {
5949 count-- ;
5950 if (count == 0U)
5951 {
5952 /* Disable the CRYP peripheral clock */
5953 __HAL_CRYP_DISABLE(hcryp);
5954
5955 /* Change state */
5956 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5957 hcryp->State = HAL_CRYP_STATE_READY;
5958
5959 /* Process unlocked */
5960 __HAL_UNLOCK(hcryp);
5961 return HAL_ERROR;
5962 }
5963 } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM));
5964 }
5965 }
5966 else
5967 {
5968 /*Write header block in the IN FIFO without last block */
5969 for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes / 16U) * 4U)); loopcounter += 4U)
5970 {
5971 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5972 hcryp->CrypHeaderCount++ ;
5973 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5974 hcryp->CrypHeaderCount++ ;
5975 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5976 hcryp->CrypHeaderCount++ ;
5977 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
5978 hcryp->CrypHeaderCount++ ;
5979
5980 /* Wait for IFEM to be raised */
5981 count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
5982 do
5983 {
5984 count-- ;
5985 if (count == 0U)
5986 {
5987 /* Disable the CRYP peripheral clock */
5988 __HAL_CRYP_DISABLE(hcryp);
5989
5990 /* Change state */
5991 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
5992 hcryp->State = HAL_CRYP_STATE_READY;
5993
5994 /* Process unlocked */
5995 __HAL_UNLOCK(hcryp);
5996 return HAL_ERROR;
5997 }
5998 } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM));
5999 }
6000 /* Last block optionally pad the data with zeros*/
6001 for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes / 4U) % 4U)); loopcounter++)
6002 {
6003 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6004 hcryp->CrypHeaderCount++ ;
6005 }
6006 /* If the header size is a multiple of words */
6007 if ((headersize_in_bytes % 4U) == 0U)
6008 {
6009 /* Pad the data with zeros to have a complete block */
6010 while (loopcounter < 4U)
6011 {
6012 hcryp->Instance->DIN = 0x0U;
6013 loopcounter++;
6014 }
6015 }
6016 else
6017 {
6018 /* Enter last bytes, padded with zeroes */
6019 tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6020 tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)];
6021 hcryp->Instance->DIN = tmp;
6022 loopcounter++;
6023 /* Pad the data with zeros to have a complete block */
6024 while (loopcounter < 4U)
6025 {
6026 hcryp->Instance->DIN = 0x0U;
6027 loopcounter++;
6028 }
6029 }
6030 /* Wait for IFEM to be raised */
6031 count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
6032 do
6033 {
6034 count-- ;
6035 if (count == 0U)
6036 {
6037 /* Disable the CRYP peripheral clock */
6038 __HAL_CRYP_DISABLE(hcryp);
6039
6040 /* Change state */
6041 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
6042 hcryp->State = HAL_CRYP_STATE_READY;
6043
6044 /* Process unlocked */
6045 __HAL_UNLOCK(hcryp);
6046 return HAL_ERROR;
6047 }
6048 } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM));
6049 }
6050 /* Wait until the complete message has been processed */
6051 count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
6052 do
6053 {
6054 count-- ;
6055 if (count == 0U)
6056 {
6057 /* Disable the CRYP peripheral clock */
6058 __HAL_CRYP_DISABLE(hcryp);
6059
6060 /* Change state */
6061 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
6062 hcryp->State = HAL_CRYP_STATE_READY;
6063
6064 /* Process unlocked */
6065 __HAL_UNLOCK(hcryp);
6066 return HAL_ERROR;
6067 }
6068 } while (HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY));
6069
6070 #else /* AES */
6071
6072 if (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)
6073 {
6074 /* Workaround 1: only AES, before re-enabling the IP, datatype can be configured.*/
6075 MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType);
6076
6077 /* Select header phase */
6078 CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
6079
6080 /* Enable the CRYP peripheral */
6081 __HAL_CRYP_ENABLE(hcryp);
6082 }
6083 if ((headersize_in_bytes % 16U) == 0U)
6084 {
6085 /* HeaderSize %4, no padding */
6086 for (loopcounter = 0U; (loopcounter < (headersize_in_bytes / 4U)); loopcounter += 4U)
6087 {
6088 /* Write the input block in the data input register */
6089 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6090 hcryp->CrypHeaderCount++ ;
6091 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6092 hcryp->CrypHeaderCount++ ;
6093 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6094 hcryp->CrypHeaderCount++ ;
6095 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6096 hcryp->CrypHeaderCount++ ;
6097
6098 /*Wait on CCF flag*/
6099 count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
6100 do
6101 {
6102 count-- ;
6103 if (count == 0U)
6104 {
6105 /* Disable the CRYP peripheral clock */
6106 __HAL_CRYP_DISABLE(hcryp);
6107
6108 /* Change state */
6109 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
6110 hcryp->State = HAL_CRYP_STATE_READY;
6111
6112 /* Process unlocked */
6113 __HAL_UNLOCK(hcryp);
6114 return HAL_ERROR;
6115 }
6116 } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
6117
6118 /* Clear CCF flag */
6119 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
6120 }
6121 }
6122 else
6123 {
6124 /*Write header block in the IN FIFO without last block */
6125 for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes / 16U) * 4U)); loopcounter += 4U)
6126 {
6127 /* Write the Input block in the Data Input register */
6128 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6129 hcryp->CrypHeaderCount++ ;
6130 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6131 hcryp->CrypHeaderCount++ ;
6132 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6133 hcryp->CrypHeaderCount++ ;
6134 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6135 hcryp->CrypHeaderCount++ ;
6136
6137 /*Wait on CCF flag*/
6138 count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
6139 do
6140 {
6141 count-- ;
6142 if (count == 0U)
6143 {
6144 /* Disable the CRYP peripheral clock */
6145 __HAL_CRYP_DISABLE(hcryp);
6146
6147 /* Change state */
6148 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
6149 hcryp->State = HAL_CRYP_STATE_READY;
6150
6151 /* Process unlocked */
6152 __HAL_UNLOCK(hcryp);
6153 return HAL_ERROR;
6154 }
6155 } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
6156
6157 /* Clear CCF flag */
6158 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
6159 }
6160 /* Last block optionally pad the data with zeros*/
6161 for (loopcounter = 0U; (loopcounter < ((headersize_in_bytes /4U) % 4U)); loopcounter++)
6162 {
6163 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6164 hcryp->CrypHeaderCount++ ;
6165 }
6166 /* If the header size is a multiple of words */
6167 if ((headersize_in_bytes % 4U) == 0U)
6168 {
6169 /* Pad the data with zeros to have a complete block */
6170 while (loopcounter < 4U)
6171 {
6172 hcryp->Instance->DINR = 0x0U;
6173 loopcounter++;
6174 }
6175 }
6176 else
6177 {
6178 /* Enter last bytes, padded with zeroes */
6179 tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6180 tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)];
6181 hcryp->Instance->DINR = tmp;
6182 loopcounter++;
6183 /* Pad the data with zeros to have a complete block */
6184 while (loopcounter < 4U)
6185 {
6186 hcryp->Instance->DINR = 0x0U;
6187 loopcounter++;
6188 }
6189 }
6190 /*Wait on CCF flag*/
6191 count = CRYP_TIMEOUT_GCMCCMHEADERPHASE;
6192 do
6193 {
6194 count-- ;
6195 if (count == 0U)
6196 {
6197 /* Disable the CRYP peripheral clock */
6198 __HAL_CRYP_DISABLE(hcryp);
6199
6200 /* Change state */
6201 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
6202 hcryp->State = HAL_CRYP_STATE_READY;
6203
6204 /* Process unlocked */
6205 __HAL_UNLOCK(hcryp);
6206 return HAL_ERROR;
6207 }
6208 } while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF));
6209
6210 /* Clear CCF flag */
6211 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
6212 }
6213 #endif /* End AES or CRYP */
6214 }
6215 else
6216 {
6217 #if defined(AES)
6218 if (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)
6219 {
6220 /*Workaround 1: only AES, before re-enabling the IP, datatype can be configured.*/
6221 MODIFY_REG(hcryp->Instance->CR, AES_CR_DATATYPE, hcryp->Init.DataType);
6222
6223 /* Select header phase */
6224 CRYP_SET_PHASE(hcryp, CRYP_PHASE_HEADER);
6225
6226 /* Enable the CRYP peripheral */
6227 __HAL_CRYP_ENABLE(hcryp);
6228 }
6229 #endif /* AES */
6230 }
6231 /* Return function status */
6232 return HAL_OK;
6233 }
6234
6235 /**
6236 * @brief Sets the header phase in interrupt mode
6237 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
6238 * the configuration information for CRYP module(Header & HeaderSize)
6239 * @retval None
6240 */
6241 static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp)
6242 {
6243 uint32_t loopcounter;
6244 #if defined(AES)
6245 uint32_t lastwordsize;
6246 uint32_t npblb;
6247 #endif
6248 uint32_t headersize_in_bytes;
6249 uint32_t tmp;
6250 uint32_t mask[12] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */
6251 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */
6252 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU}; /* 8-bit data type */
6253
6254 if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD)
6255 {
6256 headersize_in_bytes = hcryp->Init.HeaderSize * 4U;
6257 }
6258 else
6259 {
6260 headersize_in_bytes = hcryp->Init.HeaderSize;
6261 }
6262
6263 /***************************** Header phase *********************************/
6264
6265 #if defined(CRYP)
6266 if (headersize_in_bytes <= ((uint32_t)(hcryp->CrypHeaderCount) * 4U))
6267 {
6268 /* Disable interrupts */
6269 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_INI);
6270
6271 /* Disable the CRYP peripheral */
6272 __HAL_CRYP_DISABLE(hcryp);
6273
6274 /* Set the phase */
6275 hcryp->Phase = CRYP_PHASE_PROCESS;
6276
6277 /* Select payload phase once the header phase is performed */
6278 CRYP_SET_PHASE(hcryp, CRYP_PHASE_PAYLOAD);
6279
6280 /* Enable Interrupts */
6281 __HAL_CRYP_ENABLE_IT(hcryp, CRYP_IT_INI | CRYP_IT_OUTI);
6282
6283 /* Enable the CRYP peripheral */
6284 __HAL_CRYP_ENABLE(hcryp);
6285 }
6286 else if (((headersize_in_bytes / 4U) - (hcryp->CrypHeaderCount)) >= 4U)
6287
6288 {
6289 /* HeaderSize %4, no padding */
6290 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6291 hcryp->CrypHeaderCount++ ;
6292 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6293 hcryp->CrypHeaderCount++ ;
6294 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6295 hcryp->CrypHeaderCount++ ;
6296 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6297 hcryp->CrypHeaderCount++ ;
6298 }
6299 else
6300 {
6301 /* Last block optionally pad the data with zeros*/
6302 for (loopcounter = 0U; loopcounter < ((headersize_in_bytes / 4U) % 4U); loopcounter++)
6303 {
6304 hcryp->Instance->DIN = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6305 hcryp->CrypHeaderCount++ ;
6306 }
6307 if ((headersize_in_bytes % 4U) == 0U)
6308 {
6309 /* Pad the data with zeros to have a complete block */
6310 while (loopcounter < 4U)
6311 {
6312 hcryp->Instance->DIN = 0x0U;
6313 loopcounter++;
6314 hcryp->CrypHeaderCount++;
6315 }
6316 }
6317 else
6318 {
6319 /* Enter last bytes, padded with zeros */
6320 tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6321 tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)];
6322 hcryp->Instance->DIN = tmp;
6323 loopcounter++;
6324 hcryp->CrypHeaderCount++;
6325 /* Pad the data with zeros to have a complete block */
6326 while (loopcounter < 4U)
6327 {
6328 hcryp->Instance->DIN = 0x0U;
6329 loopcounter++;
6330 hcryp->CrypHeaderCount++;
6331 }
6332 }
6333 }
6334 #else /* AES */
6335
6336 if (headersize_in_bytes <= ((uint32_t)(hcryp->CrypHeaderCount) * 4U))
6337 {
6338 /* Set the phase */
6339 hcryp->Phase = CRYP_PHASE_PROCESS;
6340
6341 /* Payload phase not supported in CCM AES2 */
6342 if (hcryp->Init.Algorithm == CRYP_AES_GCM_GMAC)
6343 {
6344 /* Select payload phase once the header phase is performed */
6345 MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_PAYLOAD);
6346 }
6347 if (hcryp->Init.Algorithm == CRYP_AES_CCM)
6348 {
6349 /* Increment CrypHeaderCount to pass in CRYP_GCMCCM_SetPayloadPhase_IT */
6350 hcryp->CrypHeaderCount++;
6351 }
6352 /* Write the payload Input block in the IN FIFO */
6353 if (hcryp->Size == 0U)
6354 {
6355 /* Disable interrupts */
6356 __HAL_CRYP_DISABLE_IT(hcryp, CRYP_IT_CCFIE | CRYP_IT_ERRIE);
6357
6358 /* Change the CRYP state */
6359 hcryp->State = HAL_CRYP_STATE_READY;
6360
6361 /* Process unlocked */
6362 __HAL_UNLOCK(hcryp);
6363 }
6364 else if (hcryp->Size >= 16U)
6365 {
6366 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
6367 hcryp->CrypInCount++;
6368 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
6369 hcryp->CrypInCount++;
6370 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
6371 hcryp->CrypInCount++;
6372 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
6373 hcryp->CrypInCount++;
6374
6375 if ((hcryp->CrypInCount == (hcryp->Size / 4U)) && ((hcryp->Size % 16U) == 0U))
6376 {
6377 /* Call the input data transfer complete callback */
6378 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
6379 /*Call registered Input complete callback*/
6380 hcryp->InCpltCallback(hcryp);
6381 #else
6382 /*Call legacy weak Input complete callback*/
6383 HAL_CRYP_InCpltCallback(hcryp);
6384 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
6385 }
6386 }
6387 else /* Size < 4 words : first block is the last block*/
6388 {
6389 /* Workaround not implemented, Size should be %4 otherwise Tag will be incorrectly
6390 generated for GCM Encryption. Workaround is implemented in polling mode, so if last block of
6391 payload <128bit don't use CRYP_Encrypt_IT otherwise TAG is incorrectly generated for GCM Encryption. */
6392
6393 /* Compute the number of padding bytes in last block of payload */
6394 npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size);
6395
6396 /* Number of valid words (lastwordsize) in last block */
6397 if ((npblb % 4U) == 0U)
6398 {
6399 lastwordsize = (16U - npblb) / 4U;
6400 }
6401 else
6402 {
6403 lastwordsize = ((16U - npblb) / 4U) + 1U;
6404 }
6405
6406 /* Last block optionally pad the data with zeros*/
6407 for (loopcounter = 0U; loopcounter < lastwordsize; loopcounter++)
6408 {
6409 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
6410 hcryp->CrypInCount++;
6411 }
6412 while (loopcounter < 4U)
6413 {
6414 /* Pad the data with zeros to have a complete block */
6415 hcryp->Instance->DINR = 0x0U;
6416 loopcounter++;
6417 }
6418 }
6419 }
6420 else if (((headersize_in_bytes / 4U) - (hcryp->CrypHeaderCount)) >= 4U)
6421 {
6422 /* Write the input block in the IN FIFO */
6423 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6424 hcryp->CrypHeaderCount++;
6425 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6426 hcryp->CrypHeaderCount++;
6427 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6428 hcryp->CrypHeaderCount++;
6429 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6430 hcryp->CrypHeaderCount++;
6431 }
6432 else /*HeaderSize < 4 or HeaderSize >4 & HeaderSize %4 != 0*/
6433 {
6434 /* Last block optionally pad the data with zeros*/
6435 for (loopcounter = 0U; loopcounter < ((headersize_in_bytes / 4U) % 4U); loopcounter++)
6436 {
6437 hcryp->Instance->DINR = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6438 hcryp->CrypHeaderCount++ ;
6439 }
6440 /* If the header size is a multiple of words */
6441 if ((headersize_in_bytes % 4U) == 0U)
6442 {
6443 /* Pad the data with zeros to have a complete block */
6444 while (loopcounter < 4U)
6445 {
6446 hcryp->Instance->DINR = 0x0U;
6447 loopcounter++;
6448 hcryp->CrypHeaderCount++;
6449 }
6450 }
6451 else
6452 {
6453 /* Enter last bytes, padded with zeros */
6454 tmp = *(uint32_t *)(hcryp->Init.Header + hcryp->CrypHeaderCount);
6455 tmp &= mask[(hcryp->Init.DataType * 2U) + (headersize_in_bytes % 4U)];
6456 hcryp->Instance->DINR = tmp;
6457 loopcounter++;
6458 hcryp->CrypHeaderCount++;
6459 /* Pad the data with zeros to have a complete block */
6460 while (loopcounter < 4U)
6461 {
6462 hcryp->Instance->DINR = 0x0U;
6463 loopcounter++;
6464 hcryp->CrypHeaderCount++;
6465 }
6466 }
6467 }
6468 #endif /* End AES or CRYP */
6469 }
6470
6471
6472 /**
6473 * @brief Workaround used for GCM/CCM mode.
6474 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
6475 * the configuration information for CRYP module
6476 * @param Timeout: specify Timeout value
6477 * @retval None
6478 */
6479 static void CRYP_Workaround(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
6480 {
6481 uint32_t lastwordsize;
6482 uint32_t npblb;
6483 #if defined(CRYP)
6484 uint32_t iv1temp;
6485 uint32_t temp[4] = {0};
6486 uint32_t temp2[4] = {0};
6487 #endif /* CRYP */
6488 uint32_t intermediate_data[4] = {0};
6489 uint32_t index;
6490
6491 /* Compute the number of padding bytes in last block of payload */
6492 npblb = ((((uint32_t)(hcryp->Size) / 16U) + 1U) * 16U) - (uint32_t)(hcryp->Size);
6493
6494 /* Number of valid words (lastwordsize) in last block */
6495 if ((npblb % 4U) == 0U)
6496 {
6497 lastwordsize = (16U - npblb) / 4U;
6498 }
6499 else
6500 {
6501 lastwordsize = ((16U - npblb) / 4U) + 1U;
6502 }
6503
6504 #if defined(CRYP)
6505
6506 /* Workaround 2, case GCM encryption */
6507 if (hcryp->Init.Algorithm == CRYP_AES_GCM)
6508 {
6509 if ((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_ENCRYPT)
6510 {
6511 /*Workaround in order to properly compute authentication tags while doing
6512 a GCM encryption with the last block of payload size inferior to 128 bits*/
6513 /* Disable CRYP to start the final phase */
6514 __HAL_CRYP_DISABLE(hcryp);
6515
6516 /*Update CRYP_IV1R register and ALGOMODE*/
6517 hcryp->Instance->IV1RR = ((hcryp->Instance->CSGCMCCM7R) - 1U);
6518 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_AES_CTR);
6519
6520 /* Enable CRYP to start the final phase */
6521 __HAL_CRYP_ENABLE(hcryp);
6522 }
6523 /* Last block optionally pad the data with zeros*/
6524 for (index = 0; index < lastwordsize; index ++)
6525 {
6526 /* Write the last input block in the IN FIFO */
6527 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
6528 hcryp->CrypInCount++;
6529 }
6530 while (index < 4U)
6531 {
6532 /* Pad the data with zeros to have a complete block */
6533 hcryp->Instance->DIN = 0U;
6534 index++;
6535 }
6536 /* Wait for OFNE flag to be raised */
6537 if (CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
6538 {
6539 /* Disable the CRYP peripheral clock */
6540 __HAL_CRYP_DISABLE(hcryp);
6541
6542 /* Change state */
6543 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
6544 hcryp->State = HAL_CRYP_STATE_READY;
6545
6546 /* Process Unlocked */
6547 __HAL_UNLOCK(hcryp);
6548 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
6549 /*Call registered error callback*/
6550 hcryp->ErrorCallback(hcryp);
6551 #else
6552 /*Call legacy weak error callback*/
6553 HAL_CRYP_ErrorCallback(hcryp);
6554 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
6555 }
6556 if ((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U)
6557 {
6558 for (index = 0U; index < 4U; index++)
6559 {
6560 /* Read the output block from the output FIFO */
6561 intermediate_data[index] = hcryp->Instance->DOUT;
6562
6563 /* Intermediate data buffer to be used in for the workaround*/
6564 *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = intermediate_data[index];
6565 hcryp->CrypOutCount++;
6566 }
6567 }
6568
6569 if ((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_ENCRYPT)
6570 {
6571 /*workaround in order to properly compute authentication tags while doing
6572 a GCM encryption with the last block of payload size inferior to 128 bits*/
6573 /* Change the AES mode to GCM mode and Select Final phase */
6574 /* configured CHMOD GCM */
6575 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_AES_GCM);
6576
6577 /* configured final phase */
6578 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH, CRYP_PHASE_FINAL);
6579
6580 if ((hcryp->Instance->CR & CRYP_CR_DATATYPE) == CRYP_DATATYPE_32B)
6581 {
6582 if ((npblb % 4U) == 1U)
6583 {
6584 intermediate_data[lastwordsize - 1U] &= 0xFFFFFF00U;
6585 }
6586 if ((npblb % 4U) == 2U)
6587 {
6588 intermediate_data[lastwordsize - 1U] &= 0xFFFF0000U;
6589 }
6590 if ((npblb % 4U) == 3U)
6591 {
6592 intermediate_data[lastwordsize - 1U] &= 0xFF000000U;
6593 }
6594 }
6595 else if ((hcryp->Instance->CR & CRYP_CR_DATATYPE) == CRYP_DATATYPE_8B)
6596 {
6597 if ((npblb % 4U) == 1U)
6598 {
6599 intermediate_data[lastwordsize - 1U] &= __REV(0xFFFFFF00U);
6600 }
6601 if ((npblb % 4U) == 2U)
6602 {
6603 intermediate_data[lastwordsize - 1U] &= __REV(0xFFFF0000U);
6604 }
6605 if ((npblb % 4U) == 3U)
6606 {
6607 intermediate_data[lastwordsize - 1U] &= __REV(0xFF000000U);
6608 }
6609 }
6610 else if ((hcryp->Instance->CR & CRYP_CR_DATATYPE) == CRYP_DATATYPE_16B)
6611 {
6612 if ((npblb % 4U) == 1U)
6613 {
6614 intermediate_data[lastwordsize - 1U] &= __ROR((0xFFFFFF00U), 16);
6615 }
6616 if ((npblb % 4U) == 2U)
6617 {
6618 intermediate_data[lastwordsize - 1U] &= __ROR((0xFFFF0000U), 16);
6619 }
6620 if ((npblb % 4U) == 3U)
6621 {
6622 intermediate_data[lastwordsize - 1U] &= __ROR((0xFF000000U), 16);
6623 }
6624 }
6625 else /*CRYP_DATATYPE_1B*/
6626 {
6627 if ((npblb % 4U) == 1U)
6628 {
6629 intermediate_data[lastwordsize - 1U] &= __RBIT(0xFFFFFF00U);
6630 }
6631 if ((npblb % 4U) == 2U)
6632 {
6633 intermediate_data[lastwordsize - 1U] &= __RBIT(0xFFFF0000U);
6634 }
6635 if ((npblb % 4U) == 3U)
6636 {
6637 intermediate_data[lastwordsize - 1U] &= __RBIT(0xFF000000U);
6638 }
6639 }
6640 for (index = 0U; index < lastwordsize; index ++)
6641 {
6642 /*Write the intermediate_data in the IN FIFO */
6643 hcryp->Instance->DIN = intermediate_data[index];
6644 }
6645 while (index < 4U)
6646 {
6647 /* Pad the data with zeros to have a complete block */
6648 hcryp->Instance->DIN = 0x0U;
6649 index++;
6650 }
6651 /* Wait for OFNE flag to be raised */
6652 if (CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
6653 {
6654 /* Disable the CRYP peripheral clock */
6655 __HAL_CRYP_DISABLE(hcryp);
6656
6657 /* Change state */
6658 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
6659 hcryp->State = HAL_CRYP_STATE_READY;
6660
6661 /* Process unlocked */
6662 __HAL_UNLOCK(hcryp);
6663 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1)
6664 /*Call registered error callback*/
6665 hcryp->ErrorCallback(hcryp);
6666 #else
6667 /*Call legacy weak error callback*/
6668 HAL_CRYP_ErrorCallback(hcryp);
6669 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
6670 }
6671
6672 if ((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U)
6673 {
6674 for (index = 0U; index < 4U; index++)
6675 {
6676 intermediate_data[index] = hcryp->Instance->DOUT;
6677 }
6678 }
6679 }
6680 } /* End of GCM encryption */
6681 else
6682 {
6683 /* Workaround 2, case CCM decryption, in order to properly compute
6684 authentication tags while doing a CCM decryption with the last block
6685 of payload size inferior to 128 bits*/
6686
6687 if ((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_DECRYPT)
6688 {
6689 iv1temp = hcryp->Instance->CSGCMCCM7R;
6690
6691 /* Disable CRYP to start the final phase */
6692 __HAL_CRYP_DISABLE(hcryp);
6693
6694 temp[0] = hcryp->Instance->CSGCMCCM0R;
6695 temp[1] = hcryp->Instance->CSGCMCCM1R;
6696 temp[2] = hcryp->Instance->CSGCMCCM2R;
6697 temp[3] = hcryp->Instance->CSGCMCCM3R;
6698
6699 hcryp->Instance->IV1RR = iv1temp;
6700
6701 /* Configured CHMOD CTR */
6702 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_AES_CTR);
6703
6704 /* Enable CRYP to start the final phase */
6705 __HAL_CRYP_ENABLE(hcryp);
6706 }
6707 /* Last block optionally pad the data with zeros*/
6708 for (index = 0; index < lastwordsize; index ++)
6709 {
6710 /* Write the last Input block in the IN FIFO */
6711 hcryp->Instance->DIN = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
6712 hcryp->CrypInCount++;
6713 }
6714 while (index < 4U)
6715 {
6716 /* Pad the data with zeros to have a complete block */
6717 hcryp->Instance->DIN = 0U;
6718 index++;
6719 }
6720 /* Wait for OFNE flag to be raised */
6721 if (CRYP_WaitOnOFNEFlag(hcryp, Timeout) != HAL_OK)
6722 {
6723 /* Disable the CRYP peripheral clock */
6724 __HAL_CRYP_DISABLE(hcryp);
6725
6726 /* Change state */
6727 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
6728 hcryp->State = HAL_CRYP_STATE_READY;
6729
6730 /* Process Unlocked */
6731 __HAL_UNLOCK(hcryp);
6732 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
6733 /*Call registered error callback*/
6734 hcryp->ErrorCallback(hcryp);
6735 #else
6736 /*Call legacy weak error callback*/
6737 HAL_CRYP_ErrorCallback(hcryp);
6738 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
6739 }
6740
6741 if ((hcryp->Instance->SR & CRYP_FLAG_OFNE) != 0x0U)
6742 {
6743 for (index = 0U; index < 4U; index++)
6744 {
6745 /* Read the Output block from the Output FIFO */
6746 intermediate_data[index] = hcryp->Instance->DOUT;
6747
6748 /*intermediate data buffer to be used in for the workaround*/
6749 *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = intermediate_data[index];
6750 hcryp->CrypOutCount++;
6751 }
6752 }
6753
6754 if ((hcryp->Instance->CR & CRYP_CR_ALGODIR) == CRYP_OPERATINGMODE_DECRYPT)
6755 {
6756 temp2[0] = hcryp->Instance->CSGCMCCM0R;
6757 temp2[1] = hcryp->Instance->CSGCMCCM1R;
6758 temp2[2] = hcryp->Instance->CSGCMCCM2R;
6759 temp2[3] = hcryp->Instance->CSGCMCCM3R;
6760
6761 /* configured CHMOD CCM */
6762 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_ALGOMODE, CRYP_AES_CCM);
6763
6764 /* configured Header phase */
6765 MODIFY_REG(hcryp->Instance->CR, CRYP_CR_GCM_CCMPH, CRYP_PHASE_HEADER);
6766
6767 /*set to zero the bits corresponding to the padded bits*/
6768 for (index = lastwordsize; index < 4U; index ++)
6769 {
6770 intermediate_data[index] = 0U;
6771 }
6772 if ((npblb % 4U) == 1U)
6773 {
6774 intermediate_data[lastwordsize - 1U] &= 0xFFFFFF00U;
6775 }
6776 if ((npblb % 4U) == 2U)
6777 {
6778 intermediate_data[lastwordsize - 1U] &= 0xFFFF0000U;
6779 }
6780 if ((npblb % 4U) == 3U)
6781 {
6782 intermediate_data[lastwordsize - 1U] &= 0xFF000000U;
6783 }
6784 for (index = 0U; index < 4U ; index ++)
6785 {
6786 intermediate_data[index] ^= temp[index];
6787 intermediate_data[index] ^= temp2[index];
6788 }
6789 for (index = 0U; index < 4U; index ++)
6790 {
6791 /* Write the last Input block in the IN FIFO */
6792 hcryp->Instance->DIN = intermediate_data[index] ;
6793 }
6794
6795 /* Wait for BUSY flag to be raised */
6796 if (CRYP_WaitOnBUSYFlag(hcryp, Timeout) != HAL_OK)
6797 {
6798 /* Disable the CRYP peripheral clock */
6799 __HAL_CRYP_DISABLE(hcryp);
6800
6801 /* Change state */
6802 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
6803 hcryp->State = HAL_CRYP_STATE_READY;
6804
6805 /* Process Unlocked */
6806 __HAL_UNLOCK(hcryp);
6807 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
6808 /*Call registered error callback*/
6809 hcryp->ErrorCallback(hcryp);
6810 #else
6811 /*Call legacy weak error callback*/
6812 HAL_CRYP_ErrorCallback(hcryp);
6813 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
6814 }
6815 }
6816 } /* End of CCM WKA*/
6817
6818 /* Process Unlocked */
6819 __HAL_UNLOCK(hcryp);
6820
6821 #else /* AES */
6822
6823 /*Workaround 2: case GCM encryption, during payload phase and before inserting
6824 the last block of paylaod, which size is inferior to 128 bits */
6825
6826 if ((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT)
6827 {
6828 /* configured CHMOD CTR */
6829 MODIFY_REG(hcryp->Instance->CR, AES_CR_CHMOD, CRYP_AES_CTR);
6830 }
6831 /* last block optionally pad the data with zeros*/
6832 for (index = 0U; index < lastwordsize; index ++)
6833 {
6834 /* Write the last Input block in the IN FIFO */
6835 hcryp->Instance->DINR = *(uint32_t *)(hcryp->pCrypInBuffPtr + hcryp->CrypInCount);
6836 hcryp->CrypInCount++;
6837 }
6838 while (index < 4U)
6839 {
6840 /* pad the data with zeros to have a complete block */
6841 hcryp->Instance->DINR = 0U;
6842 index++;
6843 }
6844 /* Wait for CCF flag to be raised */
6845 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
6846 {
6847 hcryp->State = HAL_CRYP_STATE_READY;
6848 __HAL_UNLOCK(hcryp);
6849 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
6850 /*Call registered error callback*/
6851 hcryp->ErrorCallback(hcryp);
6852 #else
6853 /*Call legacy weak error callback*/
6854 HAL_CRYP_ErrorCallback(hcryp);
6855 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
6856 }
6857
6858 /* Clear CCF Flag */
6859 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
6860
6861 for (index = 0U; index < 4U; index++)
6862 {
6863 /* Read the Output block from the Output FIFO */
6864 intermediate_data[index] = hcryp->Instance->DOUTR;
6865
6866 /*intermediate data buffer to be used in the workaround*/
6867 *(uint32_t *)(hcryp->pCrypOutBuffPtr + (hcryp->CrypOutCount)) = intermediate_data[index];
6868 hcryp->CrypOutCount++;
6869 }
6870
6871 if ((hcryp->Instance->CR & AES_CR_MODE) == CRYP_OPERATINGMODE_ENCRYPT)
6872 {
6873 /* configured CHMOD GCM */
6874 MODIFY_REG(hcryp->Instance->CR, AES_CR_CHMOD, CRYP_AES_GCM_GMAC);
6875
6876 /* Select final phase */
6877 MODIFY_REG(hcryp->Instance->CR, AES_CR_GCMPH, CRYP_PHASE_FINAL);
6878
6879 if ((hcryp->Instance->CR & AES_CR_DATATYPE) == CRYP_DATATYPE_32B)
6880 {
6881 if ((npblb % 4U) == 1U)
6882 {
6883 intermediate_data[lastwordsize - 1U] &= 0xFFFFFF00U;
6884 }
6885 if ((npblb % 4U) == 2U)
6886 {
6887 intermediate_data[lastwordsize - 1U] &= 0xFFFF0000U;
6888 }
6889 if ((npblb % 4U) == 3U)
6890 {
6891 intermediate_data[lastwordsize - 1U] &= 0xFF000000U;
6892 }
6893 }
6894 else if ((hcryp->Instance->CR & AES_CR_DATATYPE) == CRYP_DATATYPE_8B)
6895 {
6896 if ((npblb % 4U) == 1U)
6897 {
6898 intermediate_data[lastwordsize - 1U] &= __REV(0xFFFFFF00U);
6899 }
6900 if ((npblb % 4U) == 2U)
6901 {
6902 intermediate_data[lastwordsize - 1U] &= __REV(0xFFFF0000U);
6903 }
6904 if ((npblb % 4U) == 3U)
6905 {
6906 intermediate_data[lastwordsize - 1U] &= __REV(0xFF000000U);
6907 }
6908 }
6909 else if ((hcryp->Instance->CR & AES_CR_DATATYPE) == CRYP_DATATYPE_16B)
6910 {
6911 if ((npblb % 4U) == 1U)
6912 {
6913 intermediate_data[lastwordsize - 1U] &= __ROR((0xFFFFFF00U), 16);
6914 }
6915 if ((npblb % 4U) == 2U)
6916 {
6917 intermediate_data[lastwordsize - 1U] &= __ROR((0xFFFF0000U), 16);
6918 }
6919 if ((npblb % 4U) == 3U)
6920 {
6921 intermediate_data[lastwordsize - 1U] &= __ROR((0xFF000000U), 16);
6922 }
6923 }
6924 else /*CRYP_DATATYPE_1B*/
6925 {
6926 if ((npblb % 4U) == 1U)
6927 {
6928 intermediate_data[lastwordsize - 1U] &= __RBIT(0xFFFFFF00U);
6929 }
6930 if ((npblb % 4U) == 2U)
6931 {
6932 intermediate_data[lastwordsize - 1U] &= __RBIT(0xFFFF0000U);
6933 }
6934 if ((npblb % 4U) == 3U)
6935 {
6936 intermediate_data[lastwordsize - 1U] &= __RBIT(0xFF000000U);
6937 }
6938 }
6939
6940 /*Write the intermediate_data in the IN FIFO */
6941 for (index = 0U; index < lastwordsize; index ++)
6942 {
6943 hcryp->Instance->DINR = intermediate_data[index];
6944 }
6945 while (index < 4U)
6946 {
6947 /* pad the data with zeros to have a complete block */
6948 hcryp->Instance->DINR = 0U;
6949 index++;
6950 }
6951 /* Wait for CCF flag to be raised */
6952 if (CRYP_WaitOnCCFlag(hcryp, Timeout) != HAL_OK)
6953 {
6954 /* Disable the CRYP peripheral clock */
6955 __HAL_CRYP_DISABLE(hcryp);
6956
6957 /* Change state */
6958 hcryp->ErrorCode |= HAL_CRYP_ERROR_TIMEOUT;
6959 hcryp->State = HAL_CRYP_STATE_READY;
6960
6961 /* Process Unlocked */
6962 __HAL_UNLOCK(hcryp);
6963 #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U)
6964 /*Call registered error callback*/
6965 hcryp->ErrorCallback(hcryp);
6966 #else
6967 /*Call legacy weak error callback*/
6968 HAL_CRYP_ErrorCallback(hcryp);
6969 #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */
6970 }
6971 /* Clear CCF Flag */
6972 __HAL_CRYP_CLEAR_FLAG(hcryp, CRYP_CCF_CLEAR);
6973
6974 for (index = 0U; index < 4U; index++)
6975 {
6976 intermediate_data[index] = hcryp->Instance->DOUTR;
6977 }
6978 }/*End of Workaround 2*/
6979 #endif /* End AES or CRYP */
6980 }
6981
6982 #if defined (CRYP)
6983
6984 /**
6985 * @brief Handle CRYP hardware block Timeout when waiting for IFEM flag to be raised.
6986 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
6987 * the configuration information for CRYP module.
6988 * @param Timeout: Timeout duration.
6989 * @retval HAL status
6990 */
6991 static HAL_StatusTypeDef CRYP_WaitOnIFEMFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
6992 {
6993 uint32_t tickstart;
6994
6995 /* Get timeout */
6996 tickstart = HAL_GetTick();
6997
6998 while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_IFEM))
6999 {
7000 /* Check for the Timeout */
7001 if (Timeout != HAL_MAX_DELAY)
7002 {
7003 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
7004 {
7005 return HAL_ERROR;
7006 }
7007 }
7008 }
7009 return HAL_OK;
7010 }
7011
7012 /**
7013 * @brief Handle CRYP hardware block Timeout when waiting for BUSY flag to be raised.
7014 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
7015 * the configuration information for CRYP module.
7016 * @param Timeout: Timeout duration.
7017 * @retval HAL status
7018 */
7019 static HAL_StatusTypeDef CRYP_WaitOnBUSYFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
7020 {
7021 uint32_t tickstart;
7022
7023 /* Get timeout */
7024 tickstart = HAL_GetTick();
7025
7026 while (HAL_IS_BIT_SET(hcryp->Instance->SR, CRYP_FLAG_BUSY))
7027 {
7028 /* Check for the Timeout */
7029 if (Timeout != HAL_MAX_DELAY)
7030 {
7031 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
7032 {
7033 return HAL_ERROR;
7034 }
7035 }
7036 }
7037 return HAL_OK;
7038 }
7039
7040
7041 /**
7042 * @brief Handle CRYP hardware block Timeout when waiting for OFNE flag to be raised.
7043 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
7044 * the configuration information for CRYP module.
7045 * @param Timeout: Timeout duration.
7046 * @retval HAL status
7047 */
7048 static HAL_StatusTypeDef CRYP_WaitOnOFNEFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
7049 {
7050 uint32_t tickstart;
7051
7052 /* Get timeout */
7053 tickstart = HAL_GetTick();
7054
7055 while (HAL_IS_BIT_CLR(hcryp->Instance->SR, CRYP_FLAG_OFNE))
7056 {
7057 /* Check for the Timeout */
7058 if (Timeout != HAL_MAX_DELAY)
7059 {
7060 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
7061 {
7062 return HAL_ERROR;
7063 }
7064 }
7065 }
7066 return HAL_OK;
7067 }
7068
7069 #else /* AES */
7070
7071 /**
7072 * @brief Handle CRYP hardware block Timeout when waiting for CCF flag to be raised.
7073 * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains
7074 * the configuration information for CRYP module.
7075 * @param Timeout: Timeout duration.
7076 * @retval HAL status
7077 */
7078 static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout)
7079 {
7080 uint32_t tickstart;
7081
7082 /* Get timeout */
7083 tickstart = HAL_GetTick();
7084
7085 while (HAL_IS_BIT_CLR(hcryp->Instance->SR, AES_SR_CCF))
7086 {
7087 /* Check for the Timeout */
7088 if (Timeout != HAL_MAX_DELAY)
7089 {
7090 if (((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U))
7091 {
7092 return HAL_ERROR;
7093 }
7094 }
7095 }
7096 return HAL_OK;
7097 }
7098
7099 #endif /* End AES or CRYP */
7100
7101
7102 /**
7103 * @}
7104 */
7105
7106
7107
7108 /**
7109 * @}
7110 */
7111
7112 /**
7113 * @}
7114 */
7115
7116 #endif /* HAL_CRYP_MODULE_ENABLED */
7117
7118
7119 /**
7120 * @}
7121 */
7122 #endif /* TinyAES or CRYP*/
7123 /**
7124 * @}
7125 */
7126
7127
