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Searched refs:DMA1 (Results 1 – 25 of 109) sorted by relevance

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/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT798S/template/
DRTE_Device.h129 #define RTE_USART8_DMA_TX_DMA_BASE DMA1
132 #define RTE_USART8_DMA_RX_DMA_BASE DMA1
138 #define RTE_USART9_DMA_TX_DMA_BASE DMA1
141 #define RTE_USART9_DMA_RX_DMA_BASE DMA1
147 #define RTE_USART10_DMA_TX_DMA_BASE DMA1
150 #define RTE_USART10_DMA_RX_DMA_BASE DMA1
156 #define RTE_USART11_DMA_TX_DMA_BASE DMA1
159 #define RTE_USART11_DMA_RX_DMA_BASE DMA1
165 #define RTE_USART12_DMA_TX_DMA_BASE DMA1
168 #define RTE_USART12_DMA_RX_DMA_BASE DMA1
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/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT735S/template/
DRTE_Device.h129 #define RTE_USART8_DMA_TX_DMA_BASE DMA1
132 #define RTE_USART8_DMA_RX_DMA_BASE DMA1
138 #define RTE_USART9_DMA_TX_DMA_BASE DMA1
141 #define RTE_USART9_DMA_RX_DMA_BASE DMA1
147 #define RTE_USART10_DMA_TX_DMA_BASE DMA1
150 #define RTE_USART10_DMA_RX_DMA_BASE DMA1
156 #define RTE_USART11_DMA_TX_DMA_BASE DMA1
159 #define RTE_USART11_DMA_RX_DMA_BASE DMA1
165 #define RTE_USART12_DMA_TX_DMA_BASE DMA1
168 #define RTE_USART12_DMA_RX_DMA_BASE DMA1
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/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT758S/template/
DRTE_Device.h129 #define RTE_USART8_DMA_TX_DMA_BASE DMA1
132 #define RTE_USART8_DMA_RX_DMA_BASE DMA1
138 #define RTE_USART9_DMA_TX_DMA_BASE DMA1
141 #define RTE_USART9_DMA_RX_DMA_BASE DMA1
147 #define RTE_USART10_DMA_TX_DMA_BASE DMA1
150 #define RTE_USART10_DMA_RX_DMA_BASE DMA1
156 #define RTE_USART11_DMA_TX_DMA_BASE DMA1
159 #define RTE_USART11_DMA_RX_DMA_BASE DMA1
165 #define RTE_USART12_DMA_TX_DMA_BASE DMA1
168 #define RTE_USART12_DMA_RX_DMA_BASE DMA1
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/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1171/template/
DRTE_Device.h38 #define RTE_USART1_DMA_TX_DMA_BASE DMA1
47 #define RTE_USART1_DMA_RX_DMA_BASE DMA1
57 #define RTE_USART2_DMA_TX_DMA_BASE DMA1
66 #define RTE_USART2_DMA_RX_DMA_BASE DMA1
76 #define RTE_USART3_DMA_TX_DMA_BASE DMA1
85 #define RTE_USART3_DMA_RX_DMA_BASE DMA1
95 #define RTE_USART4_DMA_TX_DMA_BASE DMA1
104 #define RTE_USART4_DMA_RX_DMA_BASE DMA1
114 #define RTE_USART5_DMA_TX_DMA_BASE DMA1
123 #define RTE_USART5_DMA_RX_DMA_BASE DMA1
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/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1175/template/
DRTE_Device.h38 #define RTE_USART1_DMA_TX_DMA_BASE DMA1
47 #define RTE_USART1_DMA_RX_DMA_BASE DMA1
57 #define RTE_USART2_DMA_TX_DMA_BASE DMA1
66 #define RTE_USART2_DMA_RX_DMA_BASE DMA1
76 #define RTE_USART3_DMA_TX_DMA_BASE DMA1
85 #define RTE_USART3_DMA_RX_DMA_BASE DMA1
95 #define RTE_USART4_DMA_TX_DMA_BASE DMA1
104 #define RTE_USART4_DMA_RX_DMA_BASE DMA1
114 #define RTE_USART5_DMA_TX_DMA_BASE DMA1
123 #define RTE_USART5_DMA_RX_DMA_BASE DMA1
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/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1165/template/
DRTE_Device.h38 #define RTE_USART1_DMA_TX_DMA_BASE DMA1
47 #define RTE_USART1_DMA_RX_DMA_BASE DMA1
57 #define RTE_USART2_DMA_TX_DMA_BASE DMA1
66 #define RTE_USART2_DMA_RX_DMA_BASE DMA1
76 #define RTE_USART3_DMA_TX_DMA_BASE DMA1
85 #define RTE_USART3_DMA_RX_DMA_BASE DMA1
95 #define RTE_USART4_DMA_TX_DMA_BASE DMA1
104 #define RTE_USART4_DMA_RX_DMA_BASE DMA1
114 #define RTE_USART5_DMA_TX_DMA_BASE DMA1
123 #define RTE_USART5_DMA_RX_DMA_BASE DMA1
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/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1172/template/
DRTE_Device.h38 #define RTE_USART1_DMA_TX_DMA_BASE DMA1
47 #define RTE_USART1_DMA_RX_DMA_BASE DMA1
57 #define RTE_USART2_DMA_TX_DMA_BASE DMA1
66 #define RTE_USART2_DMA_RX_DMA_BASE DMA1
76 #define RTE_USART3_DMA_TX_DMA_BASE DMA1
85 #define RTE_USART3_DMA_RX_DMA_BASE DMA1
95 #define RTE_USART4_DMA_TX_DMA_BASE DMA1
104 #define RTE_USART4_DMA_RX_DMA_BASE DMA1
114 #define RTE_USART5_DMA_TX_DMA_BASE DMA1
123 #define RTE_USART5_DMA_RX_DMA_BASE DMA1
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/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1173/template/
DRTE_Device.h38 #define RTE_USART1_DMA_TX_DMA_BASE DMA1
47 #define RTE_USART1_DMA_RX_DMA_BASE DMA1
57 #define RTE_USART2_DMA_TX_DMA_BASE DMA1
66 #define RTE_USART2_DMA_RX_DMA_BASE DMA1
76 #define RTE_USART3_DMA_TX_DMA_BASE DMA1
85 #define RTE_USART3_DMA_RX_DMA_BASE DMA1
95 #define RTE_USART4_DMA_TX_DMA_BASE DMA1
104 #define RTE_USART4_DMA_RX_DMA_BASE DMA1
114 #define RTE_USART5_DMA_TX_DMA_BASE DMA1
123 #define RTE_USART5_DMA_RX_DMA_BASE DMA1
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/hal_nxp-latest/mcux/mcux-sdk/drivers/edma/
Dfsl_edma.c818 #elif defined(DMA1) in EDMA_GetInstanceOffset()
819 startInstanceNum = (uint8_t)EDMA_GetInstance(DMA1); in EDMA_GetInstanceOffset()
1574 #if defined(DMA1)
1580 if ((EDMA_GetChannelStatusFlags(DMA1, 0U) & (uint32_t)kEDMA_InterruptFlag) != 0U) in DMA1_04_DriverIRQHandler()
1584 if ((EDMA_GetChannelStatusFlags(DMA1, 4U) & (uint32_t)kEDMA_InterruptFlag) != 0U) in DMA1_04_DriverIRQHandler()
1594 if ((EDMA_GetChannelStatusFlags(DMA1, 1U) & (uint32_t)kEDMA_InterruptFlag) != 0U) in DMA1_15_DriverIRQHandler()
1598 if ((EDMA_GetChannelStatusFlags(DMA1, 5U) & (uint32_t)kEDMA_InterruptFlag) != 0U) in DMA1_15_DriverIRQHandler()
1608 if ((EDMA_GetChannelStatusFlags(DMA1, 2U) & (uint32_t)kEDMA_InterruptFlag) != 0U) in DMA1_26_DriverIRQHandler()
1612 if ((EDMA_GetChannelStatusFlags(DMA1, 6U) & (uint32_t)kEDMA_InterruptFlag) != 0U) in DMA1_26_DriverIRQHandler()
1622 if ((EDMA_GetChannelStatusFlags(DMA1, 3U) & (uint32_t)kEDMA_InterruptFlag) != 0U) in DMA1_37_DriverIRQHandler()
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/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1176/template/
DRTE_Device.h44 #define RTE_USART1_DMA_TX_DMA_BASE DMA1
53 #define RTE_USART1_DMA_RX_DMA_BASE DMA1
65 #define RTE_USART2_DMA_TX_DMA_BASE DMA1
74 #define RTE_USART2_DMA_RX_DMA_BASE DMA1
86 #define RTE_USART3_DMA_TX_DMA_BASE DMA1
95 #define RTE_USART3_DMA_RX_DMA_BASE DMA1
107 #define RTE_USART4_DMA_TX_DMA_BASE DMA1
116 #define RTE_USART4_DMA_RX_DMA_BASE DMA1
128 #define RTE_USART5_DMA_TX_DMA_BASE DMA1
137 #define RTE_USART5_DMA_RX_DMA_BASE DMA1
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/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1166/template/
DRTE_Device.h44 #define RTE_USART1_DMA_TX_DMA_BASE DMA1
53 #define RTE_USART1_DMA_RX_DMA_BASE DMA1
65 #define RTE_USART2_DMA_TX_DMA_BASE DMA1
74 #define RTE_USART2_DMA_RX_DMA_BASE DMA1
86 #define RTE_USART3_DMA_TX_DMA_BASE DMA1
95 #define RTE_USART3_DMA_RX_DMA_BASE DMA1
107 #define RTE_USART4_DMA_TX_DMA_BASE DMA1
116 #define RTE_USART4_DMA_RX_DMA_BASE DMA1
128 #define RTE_USART5_DMA_TX_DMA_BASE DMA1
137 #define RTE_USART5_DMA_RX_DMA_BASE DMA1
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/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U5/template/
DRTE_Device.h31 #define RTE_USART0_DMA_TX_DMA_BASE DMA1
35 #define RTE_USART0_DMA_RX_DMA_BASE DMA1
42 #define RTE_USART1_DMA_TX_DMA_BASE DMA1
46 #define RTE_USART1_DMA_RX_DMA_BASE DMA1
88 #define RTE_I2C0_DMA_TX_DMA_BASE DMA1
92 #define RTE_I2C0_DMA_RX_DMA_BASE DMA1
99 #define RTE_I2C1_DMA_TX_DMA_BASE DMA1
103 #define RTE_I2C1_DMA_RX_DMA_BASE DMA1
150 #define RTE_SPI0_DMA_TX_DMA_BASE DMA1
154 #define RTE_SPI0_DMA_RX_DMA_BASE DMA1
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/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1051/template/
DRTE_Device.h33 #define RTE_USART0_DMA_TX_DMA_BASE DMA1
37 #define RTE_USART0_DMA_RX_DMA_BASE DMA1
44 #define RTE_USART1_DMA_TX_DMA_BASE DMA1
48 #define RTE_USART1_DMA_RX_DMA_BASE DMA1
90 #define RTE_I2C0_DMA_TX_DMA_BASE DMA1
94 #define RTE_I2C0_DMA_RX_DMA_BASE DMA1
101 #define RTE_I2C1_DMA_TX_DMA_BASE DMA1
105 #define RTE_I2C1_DMA_RX_DMA_BASE DMA1
152 #define RTE_SPI0_DMA_TX_DMA_BASE DMA1
156 #define RTE_SPI0_DMA_RX_DMA_BASE DMA1
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/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1041/template/
DRTE_Device.h33 #define RTE_USART0_DMA_TX_DMA_BASE DMA1
37 #define RTE_USART0_DMA_RX_DMA_BASE DMA1
44 #define RTE_USART1_DMA_TX_DMA_BASE DMA1
48 #define RTE_USART1_DMA_RX_DMA_BASE DMA1
90 #define RTE_I2C0_DMA_TX_DMA_BASE DMA1
94 #define RTE_I2C0_DMA_RX_DMA_BASE DMA1
101 #define RTE_I2C1_DMA_TX_DMA_BASE DMA1
105 #define RTE_I2C1_DMA_RX_DMA_BASE DMA1
152 #define RTE_SPI0_DMA_TX_DMA_BASE DMA1
156 #define RTE_SPI0_DMA_RX_DMA_BASE DMA1
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/hal_nxp-latest/mcux/mcux-sdk/devices/MCIMX7U3/template/
DRTE_Device.h31 #define RTE_USART0_DMA_TX_DMA_BASE DMA1
35 #define RTE_USART0_DMA_RX_DMA_BASE DMA1
42 #define RTE_USART1_DMA_TX_DMA_BASE DMA1
46 #define RTE_USART1_DMA_RX_DMA_BASE DMA1
88 #define RTE_I2C0_DMA_TX_DMA_BASE DMA1
92 #define RTE_I2C0_DMA_RX_DMA_BASE DMA1
99 #define RTE_I2C1_DMA_TX_DMA_BASE DMA1
103 #define RTE_I2C1_DMA_RX_DMA_BASE DMA1
150 #define RTE_SPI0_DMA_TX_DMA_BASE DMA1
154 #define RTE_SPI0_DMA_RX_DMA_BASE DMA1
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/hal_nxp-latest/mcux/mcux-sdk/devices/MIMXRT1061/template/
DRTE_Device.h33 #define RTE_USART0_DMA_TX_DMA_BASE DMA1
37 #define RTE_USART0_DMA_RX_DMA_BASE DMA1
44 #define RTE_USART1_DMA_TX_DMA_BASE DMA1
48 #define RTE_USART1_DMA_RX_DMA_BASE DMA1
90 #define RTE_I2C0_DMA_TX_DMA_BASE DMA1
94 #define RTE_I2C0_DMA_RX_DMA_BASE DMA1
101 #define RTE_I2C1_DMA_TX_DMA_BASE DMA1
105 #define RTE_I2C1_DMA_RX_DMA_BASE DMA1
152 #define RTE_SPI0_DMA_TX_DMA_BASE DMA1
156 #define RTE_SPI0_DMA_RX_DMA_BASE DMA1
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/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5536/
DLPC5536_features.h359 (((x) == DMA1) ? (16) : (-1)))
371 (((x) == DMA1) ? (256) : (-1)))
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC5534/
DLPC5534_features.h359 (((x) == DMA1) ? (16) : (-1)))
371 (((x) == DMA1) ? (256) : (-1)))
/hal_nxp-latest/mcux/mcux-sdk/devices/LPC55S36/
DLPC55S36_features.h379 (((x) == DMA1) ? (16) : (-1)))
391 (((x) == DMA1) ? (256) : (-1)))
/hal_nxp-latest/s32/mcux/devices/S32Z270/
DS32Z270_glue_mcux.h279 #define DMA1 ((DMA_Type *)IP_EDMA_1_MP_BASE) macro
309 #define DMA_BASE_PTRS { DMA0, DMA1, DMA4, DMA5 }
/hal_nxp-latest/mcux/mcux-sdk/drivers/lpc_dma/
Dfsl_dma.c76 #if defined(DMA1)
1072 #if defined(DMA1)
1076 DMA_IRQHandle(DMA1); in DMA1_DriverIRQHandler()
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN546/drivers/
Dfsl_edma_soc.h33 DMA0, DMA1 \
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN236/drivers/
Dfsl_edma_soc.h33 DMA0, DMA1 \
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN235/drivers/
Dfsl_edma_soc.h33 DMA0, DMA1 \
/hal_nxp-latest/mcux/mcux-sdk/devices/MCXN946/drivers/
Dfsl_edma_soc.h33 DMA0, DMA1 \

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