1 /* 2 * Copyright (c) 2016, Freescale Semiconductor, Inc. 3 * Copyright 2016-2020 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef _RTE_DEVICE_H 9 #define _RTE_DEVICE_H 10 11 #include "pin_mux.h" 12 13 /* UART Select, LPUART0 - LPUART3. */ 14 /* User needs to provide the implementation of LPUARTX_GetFreq/LPUARTX_InitPins/LPUARTX_DeinitPins for the enabled 15 * LPUART instance. */ 16 #define RTE_USART0 0 17 #define RTE_USART0_DMA_EN 0 18 #define RTE_USART1 0 19 #define RTE_USART1_DMA_EN 0 20 #define RTE_USART2 0 21 #define RTE_USART2_DMA_EN 0 22 #define RTE_USART3 0 23 #define RTE_USART3_DMA_EN 0 24 25 /* UART configuration. */ 26 #define RTE_USART0_PIN_INIT LPUART0_InitPins 27 #define RTE_USART0_PIN_DEINIT LPUART0_DeinitPins 28 #define RTE_USART0_DMA_TX_CH 0 29 #define RTE_USART0_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux1LPUART0Tx 30 #define RTE_USART0_DMA_TX_DMAMUX_BASE DMAMUX1 31 #define RTE_USART0_DMA_TX_DMA_BASE DMA1 32 #define RTE_USART0_DMA_RX_CH 1 33 #define RTE_USART0_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux1LPUART0Rx 34 #define RTE_USART0_DMA_RX_DMAMUX_BASE DMAMUX1 35 #define RTE_USART0_DMA_RX_DMA_BASE DMA1 36 37 #define RTE_USART1_PIN_INIT LPUART1_InitPins 38 #define RTE_USART1_PIN_DEINIT LPUART1_DeinitPins 39 #define RTE_USART1_DMA_TX_CH 2 40 #define RTE_USART1_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux1LPUART1Tx 41 #define RTE_USART1_DMA_TX_DMAMUX_BASE DMAMUX1 42 #define RTE_USART1_DMA_TX_DMA_BASE DMA1 43 #define RTE_USART1_DMA_RX_CH 3 44 #define RTE_USART1_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux1LPUART1Rx 45 #define RTE_USART1_DMA_RX_DMAMUX_BASE DMAMUX1 46 #define RTE_USART1_DMA_RX_DMA_BASE DMA1 47 48 #define RTE_USART2_PIN_INIT LPUART2_InitPins 49 #define RTE_USART2_PIN_DEINIT LPUART2_DeinitPins 50 #define RTE_USART2_DMA_TX_CH 4 51 #define RTE_USART2_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0LPUART2Tx 52 #define RTE_USART2_DMA_TX_DMAMUX_BASE DMAMUX0 53 #define RTE_USART2_DMA_TX_DMA_BASE DMA0 54 #define RTE_USART2_DMA_RX_CH 5 55 #define RTE_USART2_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0LPUART2Rx 56 #define RTE_USART2_DMA_RX_DMAMUX_BASE DMAMUX0 57 #define RTE_USART2_DMA_RX_DMA_BASE DMA0 58 59 #define RTE_USART3_PIN_INIT LPUART3_InitPins 60 #define RTE_USART3_PIN_DEINIT LPUART3_DeinitPins 61 #define RTE_USART3_DMA_TX_CH 6 62 #define RTE_USART3_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0LPUART2Tx 63 #define RTE_USART3_DMA_TX_DMAMUX_BASE DMAMUX0 64 #define RTE_USART3_DMA_TX_DMA_BASE DMA0 65 #define RTE_USART3_DMA_RX_CH 7 66 #define RTE_USART3_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0LPUART3Rx 67 #define RTE_USART3_DMA_RX_DMAMUX_BASE DMAMUX0 68 #define RTE_USART3_DMA_RX_DMA_BASE DMA0 69 70 /* I2C Select, LPI2C0 - LPI2C3. */ 71 /* User needs to provide the implementation of LPI2CX_GetFreq/LPI2CX_InitPins/LPI2CX_DeinitPins for the enabled LPI2C 72 * instance. */ 73 #define RTE_I2C0 1 74 #define RTE_I2C0_DMA_EN 0 75 #define RTE_I2C1 0 76 #define RTE_I2C1_DMA_EN 0 77 #define RTE_I2C2 0 78 #define RTE_I2C2_DMA_EN 0 79 #define RTE_I2C3 1 80 #define RTE_I2C3_DMA_EN 0 81 82 /* LPI2C configuration. */ 83 #define RTE_I2C0_PIN_INIT LPI2C0_InitPins 84 #define RTE_I2C0_PIN_DEINIT LPI2C0_DeinitPins 85 #define RTE_I2C0_DMA_TX_CH 0 86 #define RTE_I2C0_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux1LPI2C0Tx 87 #define RTE_I2C0_DMA_TX_DMAMUX_BASE DMAMUX1 88 #define RTE_I2C0_DMA_TX_DMA_BASE DMA1 89 #define RTE_I2C0_DMA_RX_CH 1 90 #define RTE_I2C0_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux1LPI2C0Rx 91 #define RTE_I2C0_DMA_RX_DMAMUX_BASE DMAMUX1 92 #define RTE_I2C0_DMA_RX_DMA_BASE DMA1 93 94 #define RTE_I2C1_PIN_INIT LPI2C1_InitPins 95 #define RTE_I2C1_PIN_DEINIT LPI2C1_DeinitPins 96 #define RTE_I2C1_DMA_TX_CH 2 97 #define RTE_I2C1_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux1LPI2C1Tx 98 #define RTE_I2C1_DMA_TX_DMAMUX_BASE DMAMUX1 99 #define RTE_I2C1_DMA_TX_DMA_BASE DMA1 100 #define RTE_I2C1_DMA_RX_CH 3 101 #define RTE_I2C1_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux1LPI2C1Rx 102 #define RTE_I2C1_DMA_RX_DMAMUX_BASE DMAMUX1 103 #define RTE_I2C1_DMA_RX_DMA_BASE DMA1 104 105 #define RTE_I2C2_PIN_INIT LPI2C2_InitPins 106 #define RTE_I2C2_PIN_DEINIT LPI2C2_DeinitPins 107 #define RTE_I2C2_DMA_TX_CH 4 108 #define RTE_I2C2_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0LPI2C2Tx 109 #define RTE_I2C2_DMA_TX_DMAMUX_BASE DMAMUX0 110 #define RTE_I2C2_DMA_TX_DMA_BASE DMA0 111 #define RTE_I2C2_DMA_RX_CH 5 112 #define RTE_I2C2_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0LPI2C2Rx 113 #define RTE_I2C2_DMA_RX_DMAMUX_BASE DMAMUX0 114 #define RTE_I2C2_DMA_RX_DMA_BASE DMA0 115 116 #define RTE_I2C3_PIN_INIT LPI2C3_InitPins 117 #define RTE_I2C3_PIN_DEINIT LPI2C3_DeinitPins 118 #define RTE_I2C3_DMA_TX_CH 6 119 #define RTE_I2C3_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0LPI2C3Tx 120 #define RTE_I2C3_DMA_TX_DMAMUX_BASE DMAMUX0 121 #define RTE_I2C3_DMA_TX_DMA_BASE DMA0 122 #define RTE_I2C3_DMA_RX_CH 7 123 #define RTE_I2C3_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0LPI2C3Rx 124 #define RTE_I2C3_DMA_RX_DMAMUX_BASE DMAMUX0 125 #define RTE_I2C3_DMA_RX_DMA_BASE DMA0 126 127 /* UART Select, LPSPI0 - LPSPI3. */ 128 /* User needs to provide the implementation of LPSPIX_GetFreq/LPSPIX_InitPins/LPSPIX_DeinitPins for the enabled LPSPI 129 * instance. */ 130 #define RTE_SPI0 0 131 #define RTE_SPI0_DMA_EN 0 132 #define RTE_SPI1 0 133 #define RTE_SPI1_DMA_EN 0 134 #define RTE_SPI2 0 135 #define RTE_SPI2_DMA_EN 0 136 #define RTE_SPI3 0 137 #define RTE_SPI3_DMA_EN 0 138 139 /* SPI configuration. */ 140 #define RTE_SPI0_PCS_TO_SCK_DELAY 1000 141 #define RTE_SPI0_SCK_TO_PSC_DELAY 1000 142 #define RTE_SPI0_BETWEEN_TRANSFER_DELAY 1000 143 #define RTE_SPI0_MASTER_PCS_PIN_SEL (kLPSPI_MasterPcs0) 144 #define RTE_SPI0_SLAVE_PCS_PIN_SEL (kLPSPI_SlavePcs0) 145 #define RTE_SPI0_PIN_INIT LPSPI0_InitPins 146 #define RTE_SPI0_PIN_DEINIT LPSPI0_DeinitPins 147 #define RTE_SPI0_DMA_TX_CH 0 148 #define RTE_SPI0_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux1LPSPI0Tx 149 #define RTE_SPI0_DMA_TX_DMAMUX_BASE DMAMUX1 150 #define RTE_SPI0_DMA_TX_DMA_BASE DMA1 151 #define RTE_SPI0_DMA_RX_CH 1 152 #define RTE_SPI0_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux1LPSPI0Rx 153 #define RTE_SPI0_DMA_RX_DMAMUX_BASE DMAMUX1 154 #define RTE_SPI0_DMA_RX_DMA_BASE DMA1 155 156 #define RTE_SPI1_PCS_TO_SCK_DELAY 1000 157 #define RTE_SPI1_SCK_TO_PSC_DELAY 1000 158 #define RTE_SPI1_BETWEEN_TRANSFER_DELAY 1000 159 #define RTE_SPI1_MASTER_PCS_PIN_SEL (kLPSPI_MasterPcs0) 160 #define RTE_SPI1_SLAVE_PCS_PIN_SEL (kLPSPI_SlavePcs0) 161 #define RTE_SPI1_PIN_INIT LPSPI1_InitPins 162 #define RTE_SPI1_PIN_DEINIT LPSPI1_DeinitPins 163 #define RTE_SPI1_DMA_TX_CH 2 164 #define RTE_SPI1_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux1LPSPI1Tx 165 #define RTE_SPI1_DMA_TX_DMAMUX_BASE DMAMUX1 166 #define RTE_SPI1_DMA_TX_DMA_BASE DMA1 167 #define RTE_SPI1_DMA_RX_CH 3 168 #define RTE_SPI1_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux1LPSPI1Rx 169 #define RTE_SPI1_DMA_RX_DMAMUX_BASE DMAMUX1 170 #define RTE_SPI1_DMA_RX_DMA_BASE DMA1 171 172 #define RTE_SPI2_PCS_TO_SCK_DELAY 1000 173 #define RTE_SPI2_SCK_TO_PSC_DELAY 1000 174 #define RTE_SPI2_BETWEEN_TRANSFER_DELAY 1000 175 #define RTE_SPI2_MASTER_PCS_PIN_SEL (kLPSPI_MasterPcs0) 176 #define RTE_SPI2_SLAVE_PCS_PIN_SEL (kLPSPI_SlavePcs0) 177 #define RTE_SPI2_PIN_INIT LPSPI2_InitPins 178 #define RTE_SPI2_PIN_DEINIT LPSPI2_DeinitPins 179 #define RTE_SPI2_DMA_TX_CH 4 180 #define RTE_SPI2_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0LPSPI2Tx 181 #define RTE_SPI2_DMA_TX_DMAMUX_BASE DMAMUX0 182 #define RTE_SPI2_DMA_TX_DMA_BASE DMA0 183 #define RTE_SPI2_DMA_RX_CH 5 184 #define RTE_SPI2_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0LPSPI2Rx 185 #define RTE_SPI2_DMA_RX_DMAMUX_BASE DMAMUX0 186 #define RTE_SPI2_DMA_RX_DMA_BASE DMA0 187 188 #define RTE_SPI3_PCS_TO_SCK_DELAY 1000 189 #define RTE_SPI3_SCK_TO_PSC_DELAY 1000 190 #define RTE_SPI3_BETWEEN_TRANSFER_DELAY 1000 191 #define RTE_SPI3_MASTER_PCS_PIN_SEL (kLPSPI_MasterPcs0) 192 #define RTE_SPI3_SLAVE_PCS_PIN_SEL (kLPSPI_SlavePcs0) 193 #define RTE_SPI3_PIN_INIT LPSPI3_InitPins 194 #define RTE_SPI3_PIN_DEINIT LPSPI3_DeinitPins 195 #define RTE_SPI3_DMA_TX_CH 6 196 #define RTE_SPI3_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0LPSPI3Tx 197 #define RTE_SPI3_DMA_TX_DMAMUX_BASE DMAMUX0 198 #define RTE_SPI3_DMA_TX_DMA_BASE DMA0 199 #define RTE_SPI3_DMA_RX_CH 7 200 #define RTE_SPI3_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0LPSPI3Rx 201 #define RTE_SPI3_DMA_RX_DMAMUX_BASE DMAMUX0 202 #define RTE_SPI3_DMA_RX_DMA_BASE DMA0 203 204 #endif /* _RTE_DEVICE_H */ 205
