1 /* 2 * Copyright (c) 2016, Freescale Semiconductor, Inc. 3 * Copyright 2016-2021 NXP 4 * All rights reserved. 5 * 6 * 7 * SPDX-License-Identifier: BSD-3-Clause 8 */ 9 10 #ifndef _RTE_DEVICE_H 11 #define _RTE_DEVICE_H 12 13 #include "pin_mux.h" 14 15 /* UART Select, LPUART0 - LPUART3. */ 16 /* User needs to provide the implementation of LPUARTX_GetFreq/LPUARTX_InitPins/LPUARTX_DeinitPins for the enabled 17 * LPUART instance. */ 18 #define RTE_USART0 0 19 #define RTE_USART0_DMA_EN 0 20 #define RTE_USART1 0 21 #define RTE_USART1_DMA_EN 0 22 #define RTE_USART2 0 23 #define RTE_USART2_DMA_EN 0 24 #define RTE_USART3 0 25 #define RTE_USART3_DMA_EN 0 26 27 /* UART configuration. */ 28 #define RTE_USART0_PIN_INIT LPUART0_InitPins 29 #define RTE_USART0_PIN_DEINIT LPUART0_DeinitPins 30 #define RTE_USART0_DMA_TX_CH 0 31 #define RTE_USART0_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux1LPUART0Tx 32 #define RTE_USART0_DMA_TX_DMAMUX_BASE DMAMUX1 33 #define RTE_USART0_DMA_TX_DMA_BASE DMA1 34 #define RTE_USART0_DMA_RX_CH 1 35 #define RTE_USART0_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux1LPUART0Rx 36 #define RTE_USART0_DMA_RX_DMAMUX_BASE DMAMUX1 37 #define RTE_USART0_DMA_RX_DMA_BASE DMA1 38 39 #define RTE_USART1_PIN_INIT LPUART1_InitPins 40 #define RTE_USART1_PIN_DEINIT LPUART1_DeinitPins 41 #define RTE_USART1_DMA_TX_CH 2 42 #define RTE_USART1_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux1LPUART1Tx 43 #define RTE_USART1_DMA_TX_DMAMUX_BASE DMAMUX1 44 #define RTE_USART1_DMA_TX_DMA_BASE DMA1 45 #define RTE_USART1_DMA_RX_CH 3 46 #define RTE_USART1_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux1LPUART1Rx 47 #define RTE_USART1_DMA_RX_DMAMUX_BASE DMAMUX1 48 #define RTE_USART1_DMA_RX_DMA_BASE DMA1 49 50 #define RTE_USART2_PIN_INIT LPUART2_InitPins 51 #define RTE_USART2_PIN_DEINIT LPUART2_DeinitPins 52 #define RTE_USART2_DMA_TX_CH 4 53 #define RTE_USART2_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0LPUART2Tx 54 #define RTE_USART2_DMA_TX_DMAMUX_BASE DMAMUX0 55 #define RTE_USART2_DMA_TX_DMA_BASE DMA0 56 #define RTE_USART2_DMA_RX_CH 5 57 #define RTE_USART2_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0LPUART2Rx 58 #define RTE_USART2_DMA_RX_DMAMUX_BASE DMAMUX0 59 #define RTE_USART2_DMA_RX_DMA_BASE DMA0 60 61 #define RTE_USART3_PIN_INIT LPUART3_InitPins 62 #define RTE_USART3_PIN_DEINIT LPUART3_DeinitPins 63 #define RTE_USART3_DMA_TX_CH 6 64 #define RTE_USART3_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0LPUART2Tx 65 #define RTE_USART3_DMA_TX_DMAMUX_BASE DMAMUX0 66 #define RTE_USART3_DMA_TX_DMA_BASE DMA0 67 #define RTE_USART3_DMA_RX_CH 7 68 #define RTE_USART3_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0LPUART3Rx 69 #define RTE_USART3_DMA_RX_DMAMUX_BASE DMAMUX0 70 #define RTE_USART3_DMA_RX_DMA_BASE DMA0 71 72 /* I2C Select, LPI2C0 - LPI2C3. */ 73 /* User needs to provide the implementation of LPI2CX_GetFreq/LPI2CX_InitPins/LPI2CX_DeinitPins for the enabled LPI2C 74 * instance. */ 75 #define RTE_I2C0 0 76 #define RTE_I2C0_DMA_EN 0 77 #define RTE_I2C1 0 78 #define RTE_I2C1_DMA_EN 0 79 #define RTE_I2C2 0 80 #define RTE_I2C2_DMA_EN 0 81 #define RTE_I2C3 0 82 #define RTE_I2C3_DMA_EN 0 83 84 /* LPI2C configuration. */ 85 #define RTE_I2C0_PIN_INIT LPI2C0_InitPins 86 #define RTE_I2C0_PIN_DEINIT LPI2C0_DeinitPins 87 #define RTE_I2C0_DMA_TX_CH 0 88 #define RTE_I2C0_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux1LPI2C0Tx 89 #define RTE_I2C0_DMA_TX_DMAMUX_BASE DMAMUX1 90 #define RTE_I2C0_DMA_TX_DMA_BASE DMA1 91 #define RTE_I2C0_DMA_RX_CH 1 92 #define RTE_I2C0_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux1LPI2C0Rx 93 #define RTE_I2C0_DMA_RX_DMAMUX_BASE DMAMUX1 94 #define RTE_I2C0_DMA_RX_DMA_BASE DMA1 95 96 #define RTE_I2C1_PIN_INIT LPI2C1_InitPins 97 #define RTE_I2C1_PIN_DEINIT LPI2C1_DeinitPins 98 #define RTE_I2C1_DMA_TX_CH 2 99 #define RTE_I2C1_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux1LPI2C1Tx 100 #define RTE_I2C1_DMA_TX_DMAMUX_BASE DMAMUX1 101 #define RTE_I2C1_DMA_TX_DMA_BASE DMA1 102 #define RTE_I2C1_DMA_RX_CH 3 103 #define RTE_I2C1_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux1LPI2C1Rx 104 #define RTE_I2C1_DMA_RX_DMAMUX_BASE DMAMUX1 105 #define RTE_I2C1_DMA_RX_DMA_BASE DMA1 106 107 #define RTE_I2C2_PIN_INIT LPI2C2_InitPins 108 #define RTE_I2C2_PIN_DEINIT LPI2C2_DeinitPins 109 #define RTE_I2C2_DMA_TX_CH 4 110 #define RTE_I2C2_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0LPI2C2Tx 111 #define RTE_I2C2_DMA_TX_DMAMUX_BASE DMAMUX0 112 #define RTE_I2C2_DMA_TX_DMA_BASE DMA0 113 #define RTE_I2C2_DMA_RX_CH 5 114 #define RTE_I2C2_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0LPI2C2Rx 115 #define RTE_I2C2_DMA_RX_DMAMUX_BASE DMAMUX0 116 #define RTE_I2C2_DMA_RX_DMA_BASE DMA0 117 118 #define RTE_I2C3_PIN_INIT LPI2C3_InitPins 119 #define RTE_I2C3_PIN_DEINIT LPI2C3_DeinitPins 120 #define RTE_I2C3_DMA_TX_CH 6 121 #define RTE_I2C3_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0LPI2C3Tx 122 #define RTE_I2C3_DMA_TX_DMAMUX_BASE DMAMUX0 123 #define RTE_I2C3_DMA_TX_DMA_BASE DMA0 124 #define RTE_I2C3_DMA_RX_CH 7 125 #define RTE_I2C3_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0LPI2C3Rx 126 #define RTE_I2C3_DMA_RX_DMAMUX_BASE DMAMUX0 127 #define RTE_I2C3_DMA_RX_DMA_BASE DMA0 128 129 /* UART Select, LPSPI0 - LPSPI3. */ 130 /* User needs to provide the implementation of SPIX_GetFreq/SPIX_InitPins/SPIX_DeinitPins for the enabled SPI instance. 131 */ 132 #define RTE_SPI0 0 133 #define RTE_SPI0_DMA_EN 0 134 #define RTE_SPI1 0 135 #define RTE_SPI1_DMA_EN 0 136 #define RTE_SPI2 0 137 #define RTE_SPI2_DMA_EN 0 138 #define RTE_SPI3 0 139 #define RTE_SPI3_DMA_EN 0 140 141 /* SPI configuration. */ 142 #define RTE_SPI0_PCS_TO_SCK_DELAY 1000 143 #define RTE_SPI0_SCK_TO_PSC_DELAY 1000 144 #define RTE_SPI0_BETWEEN_TRANSFER_DELAY 1000 145 #define RTE_SPI0_MASTER_PCS_PIN_SEL (kLPSPI_MasterPcs0) 146 #define RTE_SPI0_SLAVE_PCS_PIN_SEL (kLPSPI_SlavePcs0) 147 #define RTE_SPI0_PIN_INIT SPI0_InitPins 148 #define RTE_SPI0_PIN_DEINIT SPI0_DeinitPins 149 #define RTE_SPI0_DMA_TX_CH 0 150 #define RTE_SPI0_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux1LPSPI0Tx 151 #define RTE_SPI0_DMA_TX_DMAMUX_BASE DMAMUX1 152 #define RTE_SPI0_DMA_TX_DMA_BASE DMA1 153 #define RTE_SPI0_DMA_RX_CH 1 154 #define RTE_SPI0_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux1LPSPI0Rx 155 #define RTE_SPI0_DMA_RX_DMAMUX_BASE DMAMUX1 156 #define RTE_SPI0_DMA_RX_DMA_BASE DMA1 157 158 #define RTE_SPI1_PCS_TO_SCK_DELAY 1000 159 #define RTE_SPI1_SCK_TO_PSC_DELAY 1000 160 #define RTE_SPI1_BETWEEN_TRANSFER_DELAY 1000 161 #define RTE_SPI1_MASTER_PCS_PIN_SEL (kLPSPI_MasterPcs0) 162 #define RTE_SPI1_SLAVE_PCS_PIN_SEL (kLPSPI_SlavePcs0) 163 #define RTE_SPI1_PIN_INIT SPI1_InitPins 164 #define RTE_SPI1_PIN_DEINIT SPI1_DeinitPins 165 #define RTE_SPI1_DMA_TX_CH 2 166 #define RTE_SPI1_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux1LPSPI1Tx 167 #define RTE_SPI1_DMA_TX_DMAMUX_BASE DMAMUX1 168 #define RTE_SPI1_DMA_TX_DMA_BASE DMA1 169 #define RTE_SPI1_DMA_RX_CH 3 170 #define RTE_SPI1_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux1LPSPI1Rx 171 #define RTE_SPI1_DMA_RX_DMAMUX_BASE DMAMUX1 172 #define RTE_SPI1_DMA_RX_DMA_BASE DMA1 173 174 #define RTE_SPI2_PCS_TO_SCK_DELAY 1000 175 #define RTE_SPI2_SCK_TO_PSC_DELAY 1000 176 #define RTE_SPI2_BETWEEN_TRANSFER_DELAY 1000 177 #define RTE_SPI2_MASTER_PCS_PIN_SEL (kLPSPI_MasterPcs0) 178 #define RTE_SPI2_SLAVE_PCS_PIN_SEL (kLPSPI_SlavePcs0) 179 #define RTE_SPI2_PIN_INIT SPI2_InitPins 180 #define RTE_SPI2_PIN_DEINIT SPI2_DeinitPins 181 #define RTE_SPI2_DMA_TX_CH 4 182 #define RTE_SPI2_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0LPSPI2Tx 183 #define RTE_SPI2_DMA_TX_DMAMUX_BASE DMAMUX0 184 #define RTE_SPI2_DMA_TX_DMA_BASE DMA0 185 #define RTE_SPI2_DMA_RX_CH 5 186 #define RTE_SPI2_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0LPSPI2Rx 187 #define RTE_SPI2_DMA_RX_DMAMUX_BASE DMAMUX0 188 #define RTE_SPI2_DMA_RX_DMA_BASE DMA0 189 190 #define RTE_SPI3_PCS_TO_SCK_DELAY 1000 191 #define RTE_SPI3_SCK_TO_PSC_DELAY 1000 192 #define RTE_SPI3_BETWEEN_TRANSFER_DELAY 1000 193 #define RTE_SPI3_MASTER_PCS_PIN_SEL (kLPSPI_MasterPcs0) 194 #define RTE_SPI3_SLAVE_PCS_PIN_SEL (kLPSPI_SlavePcs0) 195 #define RTE_SPI3_PIN_INIT SPI3_InitPins 196 #define RTE_SPI3_PIN_DEINIT SPI3_DeinitPins 197 #define RTE_SPI3_DMA_TX_CH 6 198 #define RTE_SPI3_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0LPSPI3Tx 199 #define RTE_SPI3_DMA_TX_DMAMUX_BASE DMAMUX0 200 #define RTE_SPI3_DMA_TX_DMA_BASE DMA0 201 #define RTE_SPI3_DMA_RX_CH 7 202 #define RTE_SPI3_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0LPSPI3Rx 203 #define RTE_SPI3_DMA_RX_DMAMUX_BASE DMAMUX0 204 #define RTE_SPI3_DMA_RX_DMA_BASE DMA0 205 206 /* ENET configuration. */ 207 #define RTE_ENET 1 208 #define RTE_ENET_PHY_ADDRESS 2 209 #define RTE_ENET_MII 0 210 #define RTE_ENET_RMII 1 211 212 #endif /* _RTE_DEVICE_H */ 213
