1 /*
2  * Copyright 2023 NXP
3  * All rights reserved.
4  *
5  * SPDX-License-Identifier: BSD-3-Clause
6  */
7 #ifndef _FSL_EDMA_SOC_H_
8 #define _FSL_EDMA_SOC_H_
9 
10 #include "fsl_common.h"
11 
12 /*!
13  * @addtogroup edma_soc
14  * @{
15  */
16 
17 /*******************************************************************************
18  * Definitions
19  ******************************************************************************/
20 /*! @name Driver version */
21 /*@{*/
22 /*! @brief Driver version 1.0.0. */
23 #define FSL_EDMA_SOC_DRIVER_VERSION (MAKE_VERSION(1, 0, 0))
24 /*@}*/
25 
26 /*!@brief DMA IP version */
27 #define FSL_EDMA_SOC_IP_DMA3 (1)
28 #define FSL_EDMA_SOC_IP_DMA4 (0)
29 
30 /*!@brief DMA base table */
31 #define EDMA_BASE_PTRS \
32     {                  \
33         DMA0, DMA1     \
34     }
35 
36 #define EDMA_CHN_IRQS                                                                                               \
37     {                                                                                                               \
38         {EDMA_0_CH0_IRQn,  EDMA_0_CH1_IRQn,  EDMA_0_CH2_IRQn,  EDMA_0_CH3_IRQn, EDMA_0_CH4_IRQn,  EDMA_0_CH5_IRQn,  \
39          EDMA_0_CH6_IRQn,  EDMA_0_CH7_IRQn,  EDMA_0_CH8_IRQn,  EDMA_0_CH9_IRQn, EDMA_0_CH10_IRQn, EDMA_0_CH11_IRQn, \
40          EDMA_0_CH12_IRQn, EDMA_0_CH13_IRQn, EDMA_0_CH14_IRQn, EDMA_0_CH15_IRQn},                                   \
41         {                                                                                                           \
42             EDMA_1_CH0_IRQn, EDMA_1_CH1_IRQn, EDMA_1_CH2_IRQn, EDMA_1_CH3_IRQn, EDMA_1_CH4_IRQn, EDMA_1_CH5_IRQn,   \
43                 EDMA_1_CH6_IRQn, EDMA_1_CH7_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn,               \
44                 NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn            \
45         }                                                                                                           \
46     }
47 
48 /*!@brief EDMA base address convert macro */
49 #define EDMA_CHANNEL_OFFSET           0x1000U
50 #define EDMA_CHANNEL_ARRAY_STEP(base) (0x1000U)
51 
52 /*******************************************************************************
53  * API
54  ******************************************************************************/
55 
56 #ifdef __cplusplus
57 extern "C" {
58 #endif
59 
60 #ifdef __cplusplus
61 }
62 #endif
63 
64 /*!
65  * @}
66  */
67 
68 #endif /* _FSL_EDMA_SOC_H_ */
69