1 /* 2 * Copyright 2024 NXP 3 * 4 * SPDX-License-Identifier: BSD-3-Clause 5 */ 6 7 #ifndef _RTE_DEVICE_H 8 #define _RTE_DEVICE_H 9 10 #include "pin_mux.h" 11 12 /* LPUART Select, LPUART0-13(cm33_core0), LPUART17-20(cm33_core1). */ 13 /* User needs to provide the implementation of LPUARTX_GetFreq/LPUARTX_InitPins/LPUARTX_DeinitPins for the enabled 14 * LPUART instance. */ 15 #define RTE_USART0 0 16 #define RTE_USART0_DMA_EN 0 17 #define RTE_USART1 0 18 #define RTE_USART1_DMA_EN 0 19 #define RTE_USART2 0 20 #define RTE_USART2_DMA_EN 0 21 #define RTE_USART3 0 22 #define RTE_USART3_DMA_EN 0 23 #define RTE_USART4 0 24 #define RTE_USART4_DMA_EN 0 25 #define RTE_USART5 0 26 #define RTE_USART5_DMA_EN 0 27 #define RTE_USART6 0 28 #define RTE_USART6_DMA_EN 0 29 #define RTE_USART7 0 30 #define RTE_USART7_DMA_EN 0 31 #define RTE_USART8 0 32 #define RTE_USART8_DMA_EN 0 33 #define RTE_USART9 0 34 #define RTE_USART9_DMA_EN 0 35 #define RTE_USART10 0 36 #define RTE_USART10_DMA_EN 0 37 #define RTE_USART11 0 38 #define RTE_USART11_DMA_EN 0 39 #define RTE_USART12 0 40 #define RTE_USART12_DMA_EN 0 41 #define RTE_USART13 0 42 #define RTE_USART13_DMA_EN 0 43 #define RTE_USART17 0 44 #define RTE_USART17_DMA_EN 0 45 #define RTE_USART18 0 46 #define RTE_USART18_DMA_EN 0 47 #define RTE_USART19 0 48 #define RTE_USART19_DMA_EN 0 49 #define RTE_USART20 0 50 #define RTE_USART20_DMA_EN 0 51 52 /* USART configuration. */ 53 #define RTE_USART0_PIN_INIT LPUART0_InitPins 54 #define RTE_USART0_PIN_DEINIT LPUART0_DeinitPins 55 #define RTE_USART0_DMA_TX_CH 0 56 #define RTE_USART0_DMA_TX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm0Tx 57 #define RTE_USART0_DMA_TX_DMA_BASE DMA0 58 #define RTE_USART0_DMA_RX_CH 1 59 #define RTE_USART0_DMA_RX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm0Rx 60 #define RTE_USART0_DMA_RX_DMA_BASE DMA0 61 62 #define RTE_USART1_PIN_INIT LPUART1_InitPins 63 #define RTE_USART1_PIN_DEINIT LPUART1_DeinitPins 64 #define RTE_USART1_DMA_TX_CH 2 65 #define RTE_USART1_DMA_TX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm1Tx 66 #define RTE_USART1_DMA_TX_DMA_BASE DMA0 67 #define RTE_USART1_DMA_RX_CH 3 68 #define RTE_USART1_DMA_RX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm1Rx 69 #define RTE_USART1_DMA_RX_DMA_BASE DMA0 70 71 #define RTE_USART2_PIN_INIT LPUART2_InitPins 72 #define RTE_USART2_PIN_DEINIT LPUART2_DeinitPins 73 #define RTE_USART2_DMA_TX_CH 4 74 #define RTE_USART2_DMA_TX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm2Tx 75 #define RTE_USART2_DMA_TX_DMA_BASE DMA0 76 #define RTE_USART2_DMA_RX_CH 5 77 #define RTE_USART2_DMA_RX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm2Rx 78 #define RTE_USART2_DMA_RX_DMA_BASE DMA0 79 80 #define RTE_USART3_PIN_INIT LPUART3_InitPins 81 #define RTE_USART3_PIN_DEINIT LPUART3_DeinitPins 82 #define RTE_USART3_DMA_TX_CH 6 83 #define RTE_USART3_DMA_TX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm3Tx 84 #define RTE_USART3_DMA_TX_DMA_BASE DMA0 85 #define RTE_USART3_DMA_RX_CH 7 86 #define RTE_USART3_DMA_RX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm3Rx 87 #define RTE_USART3_DMA_RX_DMA_BASE DMA0 88 89 #define RTE_USART4_PIN_INIT LPUART4_InitPins 90 #define RTE_USART4_PIN_DEINIT LPUART4_DeinitPins 91 #define RTE_USART4_DMA_TX_CH 8 92 #define RTE_USART4_DMA_TX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm4Tx 93 #define RTE_USART4_DMA_TX_DMA_BASE DMA0 94 #define RTE_USART4_DMA_RX_CH 9 95 #define RTE_USART4_DMA_RX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm4Rx 96 #define RTE_USART4_DMA_RX_DMA_BASE DMA0 97 98 #define RTE_USART5_PIN_INIT LPUART5_InitPins 99 #define RTE_USART5_PIN_DEINIT LPUART5_DeinitPins 100 #define RTE_USART5_DMA_TX_CH 10 101 #define RTE_USART5_DMA_TX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm5Tx 102 #define RTE_USART5_DMA_TX_DMA_BASE DMA0 103 #define RTE_USART5_DMA_RX_CH 11 104 #define RTE_USART5_DMA_RX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm5Rx 105 #define RTE_USART5_DMA_RX_DMA_BASE DMA0 106 107 #define RTE_USART6_PIN_INIT LPUART6_InitPins 108 #define RTE_USART6_PIN_DEINIT LPUART6_DeinitPins 109 #define RTE_USART6_DMA_TX_CH 12 110 #define RTE_USART6_DMA_TX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm6Tx 111 #define RTE_USART6_DMA_TX_DMA_BASE DMA0 112 #define RTE_USART6_DMA_RX_CH 13 113 #define RTE_USART6_DMA_RX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm6Rx 114 #define RTE_USART6_DMA_RX_DMA_BASE DMA0 115 116 #define RTE_USART7_PIN_INIT LPUART7_InitPins 117 #define RTE_USART7_PIN_DEINIT LPUART7_DeinitPins 118 #define RTE_USART7_DMA_TX_CH 14 119 #define RTE_USART7_DMA_TX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm7Tx 120 #define RTE_USART7_DMA_TX_DMA_BASE DMA0 121 #define RTE_USART7_DMA_RX_CH 15 122 #define RTE_USART7_DMA_RX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm7Rx 123 #define RTE_USART7_DMA_RX_DMA_BASE DMA0 124 125 #define RTE_USART8_PIN_INIT LPUART8_InitPins 126 #define RTE_USART8_PIN_DEINIT LPUART8_DeinitPins 127 #define RTE_USART8_DMA_TX_CH 0 128 #define RTE_USART8_DMA_TX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm8Tx 129 #define RTE_USART8_DMA_TX_DMA_BASE DMA1 130 #define RTE_USART8_DMA_RX_CH 1 131 #define RTE_USART8_DMA_RX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm8Rx 132 #define RTE_USART8_DMA_RX_DMA_BASE DMA1 133 134 #define RTE_USART9_PIN_INIT LPUART9_InitPins 135 #define RTE_USART9_PIN_DEINIT LPUART9_DeinitPins 136 #define RTE_USART9_DMA_TX_CH 2 137 #define RTE_USART9_DMA_TX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm9Tx 138 #define RTE_USART9_DMA_TX_DMA_BASE DMA1 139 #define RTE_USART9_DMA_RX_CH 3 140 #define RTE_USART9_DMA_RX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm9Rx 141 #define RTE_USART9_DMA_RX_DMA_BASE DMA1 142 143 #define RTE_USART10_PIN_INIT LPUART10_InitPins 144 #define RTE_USART10_PIN_DEINIT LPUART10_DeinitPins 145 #define RTE_USART10_DMA_TX_CH 4 146 #define RTE_USART10_DMA_TX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm10Tx 147 #define RTE_USART10_DMA_TX_DMA_BASE DMA1 148 #define RTE_USART10_DMA_RX_CH 5 149 #define RTE_USART10_DMA_RX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm10Rx 150 #define RTE_USART10_DMA_RX_DMA_BASE DMA1 151 152 #define RTE_USART11_PIN_INIT LPUART11_InitPins 153 #define RTE_USART11_PIN_DEINIT LPUART11_DeinitPins 154 #define RTE_USART11_DMA_TX_CH 6 155 #define RTE_USART11_DMA_TX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm11Tx 156 #define RTE_USART11_DMA_TX_DMA_BASE DMA1 157 #define RTE_USART11_DMA_RX_CH 7 158 #define RTE_USART11_DMA_RX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm11Rx 159 #define RTE_USART11_DMA_RX_DMA_BASE DMA1 160 161 #define RTE_USART12_PIN_INIT LPUART12_InitPins 162 #define RTE_USART12_PIN_DEINIT LPUART12_DeinitPins 163 #define RTE_USART12_DMA_TX_CH 8 164 #define RTE_USART12_DMA_TX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm12Tx 165 #define RTE_USART12_DMA_TX_DMA_BASE DMA1 166 #define RTE_USART12_DMA_RX_CH 9 167 #define RTE_USART12_DMA_RX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm12Rx 168 #define RTE_USART12_DMA_RX_DMA_BASE DMA1 169 170 #define RTE_USART13_PIN_INIT LPUART13_InitPins 171 #define RTE_USART13_PIN_DEINIT LPUART13_DeinitPins 172 #define RTE_USART13_DMA_TX_CH 10 173 #define RTE_USART13_DMA_TX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm13Tx 174 #define RTE_USART13_DMA_TX_DMA_BASE DMA1 175 #define RTE_USART13_DMA_RX_CH 11 176 #define RTE_USART13_DMA_RX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm13Rx 177 #define RTE_USART13_DMA_RX_DMA_BASE DMA1 178 179 #define RTE_USART17_PIN_INIT LPUART17_InitPins 180 #define RTE_USART17_PIN_DEINIT LPUART17_DeinitPins 181 #define RTE_USART17_DMA_TX_CH 0 182 #define RTE_USART17_DMA_TX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm17Tx 183 #define RTE_USART17_DMA_TX_DMA_BASE DMA2 184 #define RTE_USART17_DMA_RX_CH 1 185 #define RTE_USART17_DMA_RX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm17Rx 186 #define RTE_USART17_DMA_RX_DMA_BASE DMA2 187 188 #define RTE_USART18_PIN_INIT LPUART18_InitPins 189 #define RTE_USART18_PIN_DEINIT LPUART18_DeinitPins 190 #define RTE_USART18_DMA_TX_CH 2 191 #define RTE_USART18_DMA_TX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm18Tx 192 #define RTE_USART18_DMA_TX_DMA_BASE DMA2 193 #define RTE_USART18_DMA_RX_CH 3 194 #define RTE_USART18_DMA_RX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm18Rx 195 #define RTE_USART18_DMA_RX_DMA_BASE DMA2 196 197 #define RTE_USART19_PIN_INIT LPUART19_InitPins 198 #define RTE_USART19_PIN_DEINIT LPUART19_DeinitPins 199 #define RTE_USART19_DMA_TX_CH 4 200 #define RTE_USART19_DMA_TX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm19Tx 201 #define RTE_USART19_DMA_TX_DMA_BASE DMA2 202 #define RTE_USART19_DMA_RX_CH 5 203 #define RTE_USART19_DMA_RX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm19Rx 204 #define RTE_USART19_DMA_RX_DMA_BASE DMA2 205 206 #define RTE_USART20_PIN_INIT LPUART20_InitPins 207 #define RTE_USART20_PIN_DEINIT LPUART20_DeinitPins 208 #define RTE_USART20_DMA_TX_CH 6 209 #define RTE_USART20_DMA_TX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm20Tx 210 #define RTE_USART20_DMA_TX_DMA_BASE DMA2 211 #define RTE_USART20_DMA_RX_CH 7 212 #define RTE_USART20_DMA_RX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm20Rx 213 #define RTE_USART20_DMA_RX_DMA_BASE DMA2 214 215 /* I2C Select, I2C0-I2C13,I2C15, I2C17-I2C20 */ 216 /* User needs to provide the implementation of LPI2CX_GetFreq/LPI2CX_InitPins/LPI2CX_DeinitPins for the enabled I2C 217 * instance. 218 */ 219 #define RTE_I2C0 0 220 #define RTE_I2C0_DMA_EN 0 221 #define RTE_I2C1 0 222 #define RTE_I2C1_DMA_EN 0 223 #define RTE_I2C2 0 224 #define RTE_I2C2_DMA_EN 0 225 #define RTE_I2C3 0 226 #define RTE_I2C3_DMA_EN 0 227 #define RTE_I2C4 0 228 #define RTE_I2C4_DMA_EN 0 229 #define RTE_I2C5 0 230 #define RTE_I2C5_DMA_EN 0 231 #define RTE_I2C6 0 232 #define RTE_I2C6_DMA_EN 0 233 #define RTE_I2C7 0 234 #define RTE_I2C7_DMA_EN 0 235 #define RTE_I2C8 0 236 #define RTE_I2C8_DMA_EN 0 237 #define RTE_I2C9 0 238 #define RTE_I2C9_DMA_EN 0 239 #define RTE_I2C10 0 240 #define RTE_I2C10_DMA_EN 0 241 #define RTE_I2C11 0 242 #define RTE_I2C11_DMA_EN 0 243 #define RTE_I2C12 0 244 #define RTE_I2C12_DMA_EN 0 245 #define RTE_I2C13 0 246 #define RTE_I2C13_DMA_EN 0 247 #define RTE_I2C15 0 248 #define RTE_I2C15_DMA_EN 0 249 #define RTE_I2C17 0 250 #define RTE_I2C17_DMA_EN 0 251 #define RTE_I2C18 0 252 #define RTE_I2C18_DMA_EN 0 253 #define RTE_I2C19 0 254 #define RTE_I2C19_DMA_EN 0 255 #define RTE_I2C20 0 256 #define RTE_I2C20_DMA_EN 0 257 258 /*I2C configuration*/ 259 #define RTE_I2C0_PIN_INIT LPI2C0_InitPins 260 #define RTE_I2C0_PIN_DEINIT LPI2C0_DeinitPins 261 #define RTE_I2C0_DMA_TX_CH 0 262 #define RTE_I2C0_DMA_TX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm0Tx 263 #define RTE_I2C0_DMA_TX_DMA_BASE DMA0 264 #define RTE_I2C0_DMA_RX_CH 1 265 #define RTE_I2C0_DMA_RX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm0Rx 266 #define RTE_I2C0_DMA_RX_DMA_BASE DMA0 267 268 #define RTE_I2C1_PIN_INIT LPI2C1_InitPins 269 #define RTE_I2C1_PIN_DEINIT LPI2C1_DeinitPins 270 #define RTE_I2C1_DMA_TX_CH 2 271 #define RTE_I2C1_DMA_TX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm1Tx 272 #define RTE_I2C1_DMA_TX_DMA_BASE DMA0 273 #define RTE_I2C1_DMA_RX_CH 3 274 #define RTE_I2C1_DMA_RX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm1Rx 275 #define RTE_I2C1_DMA_RX_DMA_BASE DMA0 276 277 #define RTE_I2C2_PIN_INIT LPI2C2_InitPins 278 #define RTE_I2C2_PIN_DEINIT LPI2C2_DeinitPins 279 #define RTE_I2C2_DMA_TX_CH 4 280 #define RTE_I2C2_DMA_TX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm2Tx 281 #define RTE_I2C2_DMA_TX_DMA_BASE DMA0 282 #define RTE_I2C2_DMA_RX_CH 5 283 #define RTE_I2C2_DMA_RX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm2Rx 284 #define RTE_I2C2_DMA_RX_DMA_BASE DMA0 285 286 #define RTE_I2C3_PIN_INIT LPI2C3_InitPins 287 #define RTE_I2C3_PIN_DEINIT LPI2C3_DeinitPins 288 #define RTE_I2C3_DMA_TX_CH 6 289 #define RTE_I2C3_DMA_TX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm3Tx 290 #define RTE_I2C3_DMA_TX_DMA_BASE DMA0 291 #define RTE_I2C3_DMA_RX_CH 7 292 #define RTE_I2C3_DMA_RX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm3Rx 293 #define RTE_I2C3_DMA_RX_DMA_BASE DMA0 294 295 #define RTE_I2C4_PIN_INIT LPI2C4_InitPins 296 #define RTE_I2C4_PIN_DEINIT LPI2C4_DeinitPins 297 #define RTE_I2C4_DMA_TX_CH 8 298 #define RTE_I2C4_DMA_TX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm4Tx 299 #define RTE_I2C4_DMA_TX_DMA_BASE DMA0 300 #define RTE_I2C4_DMA_RX_CH 9 301 #define RTE_I2C4_DMA_RX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm4Rx 302 #define RTE_I2C4_DMA_RX_DMA_BASE DMA0 303 304 #define RTE_I2C5_PIN_INIT LPI2C5_InitPins 305 #define RTE_I2C5_PIN_DEINIT LPI2C5_DeinitPins 306 #define RTE_I2C5_DMA_TX_CH 10 307 #define RTE_I2C5_DMA_TX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm5Tx 308 #define RTE_I2C5_DMA_TX_DMA_BASE DMA0 309 #define RTE_I2C5_DMA_RX_CH 11 310 #define RTE_I2C5_DMA_RX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm5Rx 311 #define RTE_I2C5_DMA_RX_DMA_BASE DMA0 312 313 #define RTE_I2C6_PIN_INIT LPI2C6_InitPins 314 #define RTE_I2C6_PIN_DEINIT LPI2C6_DeinitPins 315 #define RTE_I2C6_DMA_TX_CH 12 316 #define RTE_I2C6_DMA_TX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm6Tx 317 #define RTE_I2C6_DMA_TX_DMA_BASE DMA0 318 #define RTE_I2C6_DMA_RX_CH 13 319 #define RTE_I2C6_DMA_RX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm6Rx 320 #define RTE_I2C6_DMA_RX_DMA_BASE DMA0 321 322 #define RTE_I2C7_PIN_INIT LPI2C7_InitPins 323 #define RTE_I2C7_PIN_DEINIT LPI2C7_DeinitPins 324 #define RTE_I2C7_DMA_TX_CH 14 325 #define RTE_I2C7_DMA_TX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm7Tx 326 #define RTE_I2C7_DMA_TX_DMA_BASE DMA0 327 #define RTE_I2C7_DMA_RX_CH 15 328 #define RTE_I2C7_DMA_RX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm7Rx 329 #define RTE_I2C7_DMA_RX_DMA_BASE DMA0 330 331 #define RTE_I2C8_PIN_INIT LPI2C8_InitPins 332 #define RTE_I2C8_PIN_DEINIT LPI2C8_DeinitPins 333 #define RTE_I2C8_DMA_TX_CH 0 334 #define RTE_I2C8_DMA_TX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm8Tx 335 #define RTE_I2C8_DMA_TX_DMA_BASE DMA1 336 #define RTE_I2C8_DMA_RX_CH 1 337 #define RTE_I2C8_DMA_RX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm8Rx 338 #define RTE_I2C8_DMA_RX_DMA_BASE DMA1 339 340 #define RTE_I2C9_PIN_INIT LPI2C9_InitPins 341 #define RTE_I2C9_PIN_DEINIT LPI2C9_DeinitPins 342 #define RTE_I2C9_DMA_TX_CH 2 343 #define RTE_I2C9_DMA_TX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm9Tx 344 #define RTE_I2C9_DMA_TX_DMA_BASE DMA1 345 #define RTE_I2C9_DMA_RX_CH 3 346 #define RTE_I2C9_DMA_RX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm9Rx 347 #define RTE_I2C9_DMA_RX_DMA_BASE DMA1 348 349 #define RTE_I2C10_PIN_INIT LPI2C10_InitPins 350 #define RTE_I2C10_PIN_DEINIT LPI2C10_DeinitPins 351 #define RTE_I2C10_DMA_TX_CH 4 352 #define RTE_I2C10_DMA_TX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm10Tx 353 #define RTE_I2C10_DMA_TX_DMA_BASE DMA1 354 #define RTE_I2C10_DMA_RX_CH 5 355 #define RTE_I2C10_DMA_RX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm10Rx 356 #define RTE_I2C10_DMA_RX_DMA_BASE DMA1 357 358 #define RTE_I2C11_PIN_INIT LPI2C11_InitPins 359 #define RTE_I2C11_PIN_DEINIT LPI2C11_DeinitPins 360 #define RTE_I2C11_DMA_TX_CH 6 361 #define RTE_I2C11_DMA_TX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm11Tx 362 #define RTE_I2C11_DMA_TX_DMA_BASE DMA1 363 #define RTE_I2C11_DMA_RX_CH 7 364 #define RTE_I2C11_DMA_RX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm11Rx 365 #define RTE_I2C11_DMA_RX_DMA_BASE DMA1 366 367 #define RTE_I2C12_PIN_INIT LPI2C12_InitPins 368 #define RTE_I2C12_PIN_DEINIT LPI2C12_DeinitPins 369 #define RTE_I2C12_DMA_TX_CH 8 370 #define RTE_I2C12_DMA_TX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm12Tx 371 #define RTE_I2C12_DMA_TX_DMA_BASE DMA1 372 #define RTE_I2C12_DMA_RX_CH 9 373 #define RTE_I2C12_DMA_RX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm12Rx 374 #define RTE_I2C12_DMA_RX_DMA_BASE DMA1 375 376 #define RTE_I2C13_PIN_INIT LPI2C13_InitPins 377 #define RTE_I2C13_PIN_DEINIT LPI2C13_DeinitPins 378 #define RTE_I2C13_DMA_TX_CH 10 379 #define RTE_I2C13_DMA_TX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm13Tx 380 #define RTE_I2C13_DMA_TX_DMA_BASE DMA1 381 #define RTE_I2C13_DMA_RX_CH 11 382 #define RTE_I2C13_DMA_RX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm13Rx 383 #define RTE_I2C13_DMA_RX_DMA_BASE DMA1 384 385 #define RTE_I2C15_PIN_INIT LPI2C15_InitPins 386 #define RTE_I2C15_PIN_DEINIT LPI2C15_DeinitPins 387 #define RTE_I2C15_DMA_TX_CH 12 388 #define RTE_I2C15_DMA_TX_PERI_SEL (uint16_t) kDmaRequestMuxLpi2c15Tx 389 #define RTE_I2C15_DMA_TX_DMA_BASE DMA1 390 #define RTE_I2C15_DMA_RX_CH 13 391 #define RTE_I2C15_DMA_RX_PERI_SEL (uint16_t) kDmaRequestMuxLpi2c15Rx 392 #define RTE_I2C15_DMA_RX_DMA_BASE DMA1 393 394 #define RTE_I2C17_PIN_INIT LPI2C17_InitPins 395 #define RTE_I2C17_PIN_DEINIT LPI2C17_DeinitPins 396 #define RTE_I2C17_DMA_TX_CH 0 397 #define RTE_I2C17_DMA_TX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm17Tx 398 #define RTE_I2C17_DMA_TX_DMA_BASE DMA2 399 #define RTE_I2C17_DMA_RX_CH 1 400 #define RTE_I2C17_DMA_RX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm17Rx 401 #define RTE_I2C17_DMA_RX_DMA_BASE DMA2 402 403 #define RTE_I2C18_PIN_INIT LPI2C18_InitPins 404 #define RTE_I2C18_PIN_DEINIT LPI2C18_DeinitPins 405 #define RTE_I2C18_DMA_TX_CH 2 406 #define RTE_I2C18_DMA_TX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm18Tx 407 #define RTE_I2C18_DMA_TX_DMA_BASE DMA2 408 #define RTE_I2C18_DMA_RX_CH 3 409 #define RTE_I2C18_DMA_RX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm18Rx 410 #define RTE_I2C18_DMA_RX_DMA_BASE DMA2 411 412 #define RTE_I2C19_PIN_INIT LPI2C19_InitPins 413 #define RTE_I2C19_PIN_DEINIT LPI2C19_DeinitPins 414 #define RTE_I2C19_DMA_TX_CH 4 415 #define RTE_I2C19_DMA_TX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm19Tx 416 #define RTE_I2C19_DMA_TX_DMA_BASE DMA2 417 #define RTE_I2C19_DMA_RX_CH 5 418 #define RTE_I2C19_DMA_RX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm19Rx 419 #define RTE_I2C19_DMA_RX_DMA_BASE DMA2 420 421 #define RTE_I2C20_PIN_INIT LPI2C20_InitPins 422 #define RTE_I2C20_PIN_DEINIT LPI2C20_DeinitPins 423 #define RTE_I2C20_DMA_TX_CH 6 424 #define RTE_I2C20_DMA_TX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm20Tx 425 #define RTE_I2C20_DMA_TX_DMA_BASE DMA2 426 #define RTE_I2C20_DMA_RX_CH 7 427 #define RTE_I2C20_DMA_RX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm20Rx 428 #define RTE_I2C20_DMA_RX_DMA_BASE DMA2 429 430 /* SPI select, SPI0-SPI14, SPI16, SPI17-SPI20.*/ 431 /* User needs to provide the implementation of LPSPIX_GetFreq/LPSPIX_InitPins/LPSPIX_DeinitPins for the enabled SPI 432 * instance. 433 */ 434 #define RTE_SPI0 0 435 #define RTE_SPI0_DMA_EN 0 436 #define RTE_SPI1 0 437 #define RTE_SPI1_DMA_EN 0 438 #define RTE_SPI2 0 439 #define RTE_SPI2_DMA_EN 0 440 #define RTE_SPI3 0 441 #define RTE_SPI3_DMA_EN 0 442 #define RTE_SPI4 0 443 #define RTE_SPI4_DMA_EN 0 444 #define RTE_SPI5 0 445 #define RTE_SPI5_DMA_EN 0 446 #define RTE_SPI6 0 447 #define RTE_SPI6_DMA_EN 0 448 #define RTE_SPI7 0 449 #define RTE_SPI7_DMA_EN 0 450 #define RTE_SPI8 0 451 #define RTE_SPI8_DMA_EN 0 452 #define RTE_SPI9 0 453 #define RTE_SPI9_DMA_EN 0 454 #define RTE_SPI10 0 455 #define RTE_SPI10_DMA_EN 0 456 #define RTE_SPI11 0 457 #define RTE_SPI11_DMA_EN 0 458 #define RTE_SPI12 0 459 #define RTE_SPI12_DMA_EN 0 460 #define RTE_SPI13 0 461 #define RTE_SPI13_DMA_EN 0 462 #define RTE_SPI14 0 463 #define RTE_SPI14_DMA_EN 0 464 #define RTE_SPI16 0 465 #define RTE_SPI16_DMA_EN 0 466 #define RTE_SPI17 0 467 #define RTE_SPI17_DMA_EN 0 468 #define RTE_SPI18 0 469 #define RTE_SPI18_DMA_EN 0 470 #define RTE_SPI19 0 471 #define RTE_SPI19_DMA_EN 0 472 #define RTE_SPI20 0 473 #define RTE_SPI20_DMA_EN 0 474 475 /* SPI configuration. */ 476 #define RTE_SPI0_PIN_INIT LPSPI0_InitPins 477 #define RTE_SPI0_PIN_DEINIT LPSPI0_DeinitPins 478 #define RTE_SPI0_DMA_TX_CH 0 479 #define RTE_SPI0_DMA_TX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm0Tx 480 #define RTE_SPI0_DMA_TX_DMA_BASE DMA0 481 #define RTE_SPI0_DMA_RX_CH 1 482 #define RTE_SPI0_DMA_RX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm0Rx 483 #define RTE_SPI0_DMA_RX_DMA_BASE DMA0 484 485 #define RTE_SPI1_PIN_INIT LPSPI1_InitPins 486 #define RTE_SPI1_PIN_DEINIT LPSPI1_DeinitPins 487 #define RTE_SPI1_DMA_TX_CH 2 488 #define RTE_SPI1_DMA_TX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm1Tx 489 #define RTE_SPI1_DMA_TX_DMA_BASE DMA0 490 #define RTE_SPI1_DMA_RX_CH 3 491 #define RTE_SPI1_DMA_RX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm1Rx 492 #define RTE_SPI1_DMA_RX_DMA_BASE DMA0 493 494 #define RTE_SPI2_PIN_INIT LPSPI2_InitPins 495 #define RTE_SPI2_PIN_DEINIT LPSPI2_DeinitPins 496 #define RTE_SPI2_DMA_TX_CH 4 497 #define RTE_SPI2_DMA_TX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm2Tx 498 #define RTE_SPI2_DMA_TX_DMA_BASE DMA0 499 #define RTE_SPI2_DMA_RX_CH 5 500 #define RTE_SPI2_DMA_RX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm2Rx 501 #define RTE_SPI2_DMA_RX_DMA_BASE DMA0 502 503 #define RTE_SPI3_PIN_INIT LPSPI3_InitPins 504 #define RTE_SPI3_PIN_DEINIT LPSPI3_DeinitPins 505 #define RTE_SPI3_DMA_TX_CH 6 506 #define RTE_SPI3_DMA_TX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm3Tx 507 #define RTE_SPI3_DMA_TX_DMA_BASE DMA0 508 #define RTE_SPI3_DMA_RX_CH 7 509 #define RTE_SPI3_DMA_RX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm3Rx 510 #define RTE_SPI3_DMA_RX_DMA_BASE DMA0 511 512 #define RTE_SPI4_PIN_INIT LPSPI4_InitPins 513 #define RTE_SPI4_PIN_DEINIT LPSPI4_DeinitPins 514 #define RTE_SPI4_DMA_TX_CH 8 515 #define RTE_SPI4_DMA_TX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm4Tx 516 #define RTE_SPI4_DMA_TX_DMA_BASE DMA0 517 #define RTE_SPI4_DMA_RX_CH 9 518 #define RTE_SPI4_DMA_RX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm4Rx 519 #define RTE_SPI4_DMA_RX_DMA_BASE DMA0 520 521 #define RTE_SPI5_PIN_INIT LPSPI5_InitPins 522 #define RTE_SPI5_PIN_DEINIT LPSPI5_DeinitPins 523 #define RTE_SPI5_DMA_TX_CH 10 524 #define RTE_SPI5_DMA_TX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm5Tx 525 #define RTE_SPI5_DMA_TX_DMA_BASE DMA0 526 #define RTE_SPI5_DMA_RX_CH 11 527 #define RTE_SPI5_DMA_RX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm5Rx 528 #define RTE_SPI5_DMA_RX_DMA_BASE DMA0 529 530 #define RTE_SPI6_PIN_INIT LPSPI6_InitPins 531 #define RTE_SPI6_PIN_DEINIT LPSPI6_DeinitPins 532 #define RTE_SPI6_DMA_TX_CH 12 533 #define RTE_SPI6_DMA_TX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm6Tx 534 #define RTE_SPI6_DMA_TX_DMA_BASE DMA0 535 #define RTE_SPI6_DMA_RX_CH 13 536 #define RTE_SPI6_DMA_RX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm6Rx 537 #define RTE_SPI6_DMA_RX_DMA_BASE DMA0 538 539 #define RTE_SPI7_PIN_INIT LPSPI7_InitPins 540 #define RTE_SPI7_PIN_DEINIT LPSPI7_DeinitPins 541 #define RTE_SPI7_DMA_TX_CH 14 542 #define RTE_SPI7_DMA_TX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm7Tx 543 #define RTE_SPI7_DMA_TX_DMA_BASE DMA0 544 #define RTE_SPI7_DMA_RX_CH 15 545 #define RTE_SPI7_DMA_RX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm7Rx 546 #define RTE_SPI7_DMA_RX_DMA_BASE DMA0 547 548 #define RTE_SPI8_PIN_INIT LPSPI8_InitPins 549 #define RTE_SPI8_PIN_DEINIT LPSPI8_DeinitPins 550 #define RTE_SPI8_DMA_TX_CH 0 551 #define RTE_SPI8_DMA_TX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm8Tx 552 #define RTE_SPI8_DMA_TX_DMA_BASE DMA1 553 #define RTE_SPI8_DMA_RX_CH 1 554 #define RTE_SPI8_DMA_RX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm8Rx 555 #define RTE_SPI8_DMA_RX_DMA_BASE DMA1 556 557 #define RTE_SPI9_PIN_INIT LPSPI9_InitPins 558 #define RTE_SPI9_PIN_DEINIT LPSPI9_DeinitPins 559 #define RTE_SPI9_DMA_TX_CH 2 560 #define RTE_SPI9_DMA_TX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm9Tx 561 #define RTE_SPI9_DMA_TX_DMA_BASE DMA1 562 #define RTE_SPI9_DMA_RX_CH 3 563 #define RTE_SPI9_DMA_RX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm9Rx 564 #define RTE_SPI9_DMA_RX_DMA_BASE DMA1 565 566 #define RTE_SPI10_PIN_INIT LPSPI10_InitPins 567 #define RTE_SPI10_PIN_DEINIT LPSPI10_DeinitPins 568 #define RTE_SPI10_DMA_TX_CH 4 569 #define RTE_SPI10_DMA_TX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm10Tx 570 #define RTE_SPI10_DMA_TX_DMA_BASE DMA1 571 #define RTE_SPI10_DMA_RX_CH 5 572 #define RTE_SPI10_DMA_RX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm10Rx 573 #define RTE_SPI10_DMA_RX_DMA_BASE DMA1 574 575 #define RTE_SPI11_PIN_INIT LPSPI11_InitPins 576 #define RTE_SPI11_PIN_DEINIT LPSPI11_DeinitPins 577 #define RTE_SPI11_DMA_TX_CH 6 578 #define RTE_SPI11_DMA_TX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm11Tx 579 #define RTE_SPI11_DMA_TX_DMA_BASE DMA1 580 #define RTE_SPI11_DMA_RX_CH 7 581 #define RTE_SPI11_DMA_RX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm11Rx 582 #define RTE_SPI11_DMA_RX_DMA_BASE DMA1 583 584 #define RTE_SPI12_PIN_INIT LPSPI12_InitPins 585 #define RTE_SPI12_PIN_DEINIT LPSPI12_DeinitPins 586 #define RTE_SPI12_DMA_TX_CH 8 587 #define RTE_SPI12_DMA_TX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm12Tx 588 #define RTE_SPI12_DMA_TX_DMA_BASE DMA1 589 #define RTE_SPI12_DMA_RX_CH 9 590 #define RTE_SPI12_DMA_RX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm12Rx 591 #define RTE_SPI12_DMA_RX_DMA_BASE DMA1 592 593 #define RTE_SPI13_PIN_INIT LPSPI13_InitPins 594 #define RTE_SPI13_PIN_DEINIT LPSPI13_DeinitPins 595 #define RTE_SPI13_DMA_TX_CH 10 596 #define RTE_SPI13_DMA_TX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm13Tx 597 #define RTE_SPI13_DMA_TX_DMA_BASE DMA1 598 #define RTE_SPI13_DMA_RX_CH 11 599 #define RTE_SPI13_DMA_RX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm13Rx 600 #define RTE_SPI13_DMA_RX_DMA_BASE DMA1 601 602 #define RTE_SPI14_PIN_INIT LPSPI14_InitPins 603 #define RTE_SPI14_PIN_DEINIT LPSPI14_DeinitPins 604 #define RTE_SPI14_DMA_TX_CH 12 605 #define RTE_SPI14_DMA_TX_PERI_SEL (uint16_t) kDmaRequestMuxLpspi14Tx 606 #define RTE_SPI14_DMA_TX_DMA_BASE DMA1 607 #define RTE_SPI14_DMA_RX_CH 13 608 #define RTE_SPI14_DMA_RX_PERI_SEL (uint16_t) kDmaRequestMuxLpspi14Rx 609 #define RTE_SPI14_DMA_RX_DMA_BASE DMA1 610 611 #define RTE_SPI16_PIN_INIT LPSPI16_InitPins 612 #define RTE_SPI16_PIN_DEINIT LPSPI16_DeinitPins 613 #define RTE_SPI16_DMA_TX_CH 14 614 #define RTE_SPI16_DMA_TX_PERI_SEL (uint16_t) kDmaRequestMuxLpspi16Tx 615 #define RTE_SPI16_DMA_TX_DMA_BASE DMA1 616 #define RTE_SPI16_DMA_RX_CH 15 617 #define RTE_SPI16_DMA_RX_PERI_SEL (uint16_t) kDmaRequestMuxLpspi16Rx 618 #define RTE_SPI16_DMA_RX_DMA_BASE DMA1 619 620 #define RTE_SPI17_PIN_INIT LPSPI17_InitPins 621 #define RTE_SPI17_PIN_DEINIT LPSPI17_DeinitPins 622 #define RTE_SPI17_DMA_TX_CH 0 623 #define RTE_SPI17_DMA_TX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm17Tx 624 #define RTE_SPI17_DMA_TX_DMA_BASE DMA2 625 #define RTE_SPI17_DMA_RX_CH 1 626 #define RTE_SPI17_DMA_RX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm17Rx 627 #define RTE_SPI17_DMA_RX_DMA_BASE DMA2 628 629 #define RTE_SPI18_PIN_INIT LPSPI18_InitPins 630 #define RTE_SPI18_PIN_DEINIT LPSPI18_DeinitPins 631 #define RTE_SPI18_DMA_TX_CH 2 632 #define RTE_SPI18_DMA_TX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm18Tx 633 #define RTE_SPI18_DMA_TX_DMA_BASE DMA2 634 #define RTE_SPI18_DMA_RX_CH 3 635 #define RTE_SPI18_DMA_RX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm18Rx 636 #define RTE_SPI18_DMA_RX_DMA_BASE DMA2 637 638 #define RTE_SPI19_PIN_INIT LPSPI19_InitPins 639 #define RTE_SPI19_PIN_DEINIT LPSPI19_DeinitPins 640 #define RTE_SPI19_DMA_TX_CH 4 641 #define RTE_SPI19_DMA_TX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm19Tx 642 #define RTE_SPI19_DMA_TX_DMA_BASE DMA2 643 #define RTE_SPI19_DMA_RX_CH 5 644 #define RTE_SPI19_DMA_RX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm19Rx 645 #define RTE_SPI19_DMA_RX_DMA_BASE DMA2 646 647 #define RTE_SPI20_PIN_INIT LPSPI20_InitPins 648 #define RTE_SPI20_PIN_DEINIT LPSPI20_DeinitPins 649 #define RTE_SPI20_DMA_TX_CH 6 650 #define RTE_SPI20_DMA_TX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm20Tx 651 #define RTE_SPI20_DMA_TX_DMA_BASE DMA2 652 #define RTE_SPI20_DMA_RX_CH 7 653 #define RTE_SPI20_DMA_RX_PERI_SEL (uint16_t) kDmaRequestMuxLpFlexcomm20Rx 654 #define RTE_SPI20_DMA_RX_DMA_BASE DMA2 655 656 #endif /* _RTE_DEVICE_H */ 657
