div3 (reference) in projects: hal_nxp-3.5.0

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Searched refs:div3 (Results 1 – 22 of 22) sorted by relevance

/hal_nxp-3.5.0/mcux/mcux-sdk/boards/frdmk32l2a4s/
D	clock_config.c	89 .div3 = kSCG_AsyncClkDivBy2, in CLOCK_CONFIG_FircSafeConfig() 197 .div3 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 3: divided by 1 / 205 .div3 = kSCG_AsyncClkDivBy2, / Slow IRC Clock Divider 3: divided by 2 / 212 .div3 = kSCG_AsyncClkDivBy1, / Fast IRC Clock Divider 3: divided by 1 / 221 ….div3 = kSCG_AsyncClkDisable, / System PLL Clock Divider 3: Clock output is disabled … 328 .div3 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 3: divided by 1 / 336 .div3 = kSCG_AsyncClkDivBy1, / Slow IRC Clock Divider 3: divided by 1 / 343 .div3 = kSCG_AsyncClkDivBy1, / Fast IRC Clock Divider 3: divided by 1 / 352 .div3 = kSCG_AsyncClkDivBy1, / System PLL Clock Divider 3: divided by 1 / 444 ….div3 = kSCG_AsyncClkDisable, / System OSC Clock Divider 3: Clock output is disabled … [all …]
/hal_nxp-3.5.0/mcux/mcux-sdk/boards/frdmk32l2a4s/project_template/
D	clock_config.c	90 .div3 = kSCG_AsyncClkDivBy2, in CLOCK_CONFIG_FircSafeConfig() 213 ….div3 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 3: divided … 220 ….div3 = kSCG_AsyncClkDivBy1, /* Slow IRC Clock Divider 3: divided by… 226 .div3 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 3: divided by 1 / 234 .div3 = kSCG_AsyncClkDivBy1, / System PLL Clock Divider 3: divided by 1 / 324 ….div3 = kSCG_AsyncClkDisable, / System OSC Clock Divider 3: Clock output is disabled … 331 ….div3 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 3: Clock outp… 337 ….div3 = kSCG_AsyncClkDisable, /* Fast IRC Clock Divider 3: Clock outp… 345 ….div3 = kSCG_AsyncClkDisable, /* System PLL Clock Divider 3: Clock output is disabled …
/hal_nxp-3.5.0/mcux/mcux-sdk/boards/frdmk32l3a6/project_template/
D	clock_config.c	153 ….div3 = kSCG_AsyncClkDivBy1, /* Slow IRC Clock Divider 3: divided by… 160 .div3 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 3: divided by 1 / 168 … .div3 = kSCG_AsyncClkDisable, / Low Power FLL Clock Divider 3: Clock output is disabled / 252 ….div3 = kSCG_AsyncClkDivBy1, / Slow IRC Clock Divider 3: divided by… 259 .div3 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 3: divided by 1 / 267 … .div3 = kSCG_AsyncClkDisable, / Low Power FLL Clock Divider 3: Clock output is disabled / 356 ….div3 = kSCG_AsyncClkDivBy1, / Slow IRC Clock Divider 3: divided by… 363 .div3 = kSCG_AsyncClkDisable, /* Fast IRC Clock Divider 3: Clock output is disabled / 371 … .div3 = kSCG_AsyncClkDisable, / Low Power FLL Clock Divider 3: Clock output is disabled */
/hal_nxp-3.5.0/mcux/mcux-sdk/boards/frdmk32l3a6/
D	clock_config.c	151 .div3 = kSCG_AsyncClkDivBy1, /* Slow IRC Clock Divider 3: divided by 1 / 159 .div3 = kSCG_AsyncClkDivBy1, / Fast IRC Clock Divider 3: divided by 1 / 168 ….div3 = kSCG_AsyncClkDisable, / Low Power FLL Clock Divider 3: Clock output is disabl… 251 .div3 = kSCG_AsyncClkDivBy1, /* Slow IRC Clock Divider 3: divided by 1 / 259 .div3 = kSCG_AsyncClkDivBy1, / Fast IRC Clock Divider 3: divided by 1 / 268 ….div3 = kSCG_AsyncClkDisable, / Low Power FLL Clock Divider 3: Clock output is disabl… 359 .div3 = kSCG_AsyncClkDivBy1, /* Slow IRC Clock Divider 3: divided by 1 / 367 … .div3 = kSCG_AsyncClkDisable, / Fast IRC Clock Divider 3: Clock output is disabled / 376 ….div3 = kSCG_AsyncClkDisable, / Low Power FLL Clock Divider 3: Clock output is disabl…
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/K32L2A41A/project_template/
D	clock_config.c	`74 .div3 = kSCG_AsyncClkDivBy2, in CLOCK_CONFIG_FircSafeConfig() 165 ….div3 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 3: Clock output is disabled … 173 … .div3 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 3: Clock output is disabled / 180 … .div3 = kSCG_AsyncClkDisable, / Fast IRC Clock Divider 3: Clock output is disabled / 189 ….div3 = kSCG_AsyncClkDisable, / System PLL Clock Divider 3: Clock output is disabled …`
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/K32L2A31A/project_template/
D	clock_config.c	`74 .div3 = kSCG_AsyncClkDivBy2, in CLOCK_CONFIG_FircSafeConfig() 165 ….div3 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 3: Clock output is disabled … 173 … .div3 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 3: Clock output is disabled / 180 … .div3 = kSCG_AsyncClkDisable, / Fast IRC Clock Divider 3: Clock output is disabled / 189 ….div3 = kSCG_AsyncClkDisable, / System PLL Clock Divider 3: Clock output is disabled …`
/hal_nxp-3.5.0/mcux/mcux-sdk/middleware/issdk/boardkit/frdm-k32w042/
D	clock_config.c	`139 .div3 = kSCG_AsyncClkDisable, /* System OSC Clock Divider 3: Clock output is disabled / 145 ….div3 = kSCG_AsyncClkDivBy1, / Slow IRC Clock Divider 3: divided by… 152 .div3 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 3: divided by 1 / 160 .div3 = kSCG_AsyncClkDisable, / Low Power FLL Clock Divider 3: Clock output is disabled */`
/hal_nxp-3.5.0/mcux/mcux-sdk/boards/evkmcimx7ulp/project_template/
D	clock_config.c	`37 .div3 = kSCG_AsyncClkDisable, 50 .div3 = kSCG_AsyncClkDisable, 63 .div3 = kSCG_AsyncClkDisable, 78 .div3 = kSCG_AsyncClkDisable, 95 .div3 = kSCG_AsyncClkDisable,`
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MCIMX7U3/project_template/
D	clock_config.c	`37 .div3 = kSCG_AsyncClkDisable, 50 .div3 = kSCG_AsyncClkDisable, 63 .div3 = kSCG_AsyncClkDisable, 78 .div3 = kSCG_AsyncClkDisable, 95 .div3 = kSCG_AsyncClkDisable,`
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MCIMX7U5/project_template/
D	clock_config.c	`37 .div3 = kSCG_AsyncClkDisable, 50 .div3 = kSCG_AsyncClkDisable, 63 .div3 = kSCG_AsyncClkDisable, 78 .div3 = kSCG_AsyncClkDisable, 95 .div3 = kSCG_AsyncClkDisable,`
/hal_nxp-3.5.0/mcux/mcux-sdk/boards/evkmcimx7ulp/
D	clock_config.c	`27 .div3 = kSCG_AsyncClkDisable, 40 .div3 = kSCG_AsyncClkDisable, 53 .div3 = kSCG_AsyncClkDisable, 68 .div3 = kSCG_AsyncClkDisable, 85 .div3 = kSCG_AsyncClkDisable,`
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/K32L3A60/project_template/
D	clock_config.c	`136 … .div3 = kSCG_AsyncClkDisable, /* Slow IRC Clock Divider 3: Clock output is disabled / 144 … .div3 = kSCG_AsyncClkDisable, / Fast IRC Clock Divider 3: Clock output is disabled / 153 ….div3 = kSCG_AsyncClkDisable, / Low Power FLL Clock Divider 3: Clock output is disabl…`
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/K32L2A41A/drivers/
D	fsl_clock.h	`463 scg_async_clk_div_t div3; /!< SOSCDIV3 value. / member 494 scg_async_clk_div_t div3; /!< SIRCDIV3 value. / member 579 scg_async_clk_div_t div3; /!< FIRCDIV3 value. / member 623 scg_async_clk_div_t div3; /!< SPLLDIV3 value. / member`
D	fsl_clock.c	`469 …V_SOSCDIV1(config->div1) \| SCG_SOSCDIV_SOSCDIV2(config->div2) \| SCG_SOSCDIV_SOSCDIV3(config->div3); in CLOCK_InitSysOsc() 621 SCG_SIRCDIV_SIRCDIV3(config->div3); in CLOCK_InitSirc() 768 …V_FIRCDIV1(config->div1) \| SCG_FIRCDIV_FIRCDIV2(config->div2) \| SCG_FIRCDIV_FIRCDIV3(config->div3); in CLOCK_InitFirc() 1074 …V_SPLLDIV1(config->div1) \| SCG_SPLLDIV_SPLLDIV2(config->div2) \| SCG_SPLLDIV_SPLLDIV3(config->div3); in CLOCK_InitSysPll()`
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/K32L2A31A/drivers/
D	fsl_clock.h	`463 scg_async_clk_div_t div3; /!< SOSCDIV3 value. / member 494 scg_async_clk_div_t div3; /!< SIRCDIV3 value. / member 579 scg_async_clk_div_t div3; /!< FIRCDIV3 value. / member 623 scg_async_clk_div_t div3; /!< SPLLDIV3 value. / member`
D	fsl_clock.c	`469 …V_SOSCDIV1(config->div1) \| SCG_SOSCDIV_SOSCDIV2(config->div2) \| SCG_SOSCDIV_SOSCDIV3(config->div3); in CLOCK_InitSysOsc() 621 SCG_SIRCDIV_SIRCDIV3(config->div3); in CLOCK_InitSirc() 768 …V_FIRCDIV1(config->div1) \| SCG_FIRCDIV_FIRCDIV2(config->div2) \| SCG_FIRCDIV_FIRCDIV3(config->div3); in CLOCK_InitFirc() 1074 …V_SPLLDIV1(config->div1) \| SCG_SPLLDIV_SPLLDIV2(config->div2) \| SCG_SPLLDIV_SPLLDIV3(config->div3); in CLOCK_InitSysPll()`
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MCIMX7U3/drivers/
D	fsl_clock.h	`631 scg_async_clk_div_t div3; /!< SOSCDIV3 value. / member 661 scg_async_clk_div_t div3; /!< SIRCDIV3 value. / member 746 scg_async_clk_div_t div3; /!< FIRCDIV3 value. / member 789 scg_async_clk_div_t div3; /!< SPLLDIV3 value. / member 853 scg_async_clk_div_t div3; /!< APLLDIV3 value. / member`
D	fsl_clock.c	603 …V_SOSCDIV1(config->div1) \| SCG_SOSCDIV_SOSCDIV2(config->div2) \| SCG_SOSCDIV_SOSCDIV3(config->div3); in CLOCK_InitSysOsc() 754 …V_SIRCDIV1(config->div1) \| SCG_SIRCDIV_SIRCDIV2(config->div2) \| SCG_SIRCDIV_SIRCDIV3(config->div3); in CLOCK_InitSirc() 900 …V_FIRCDIV1(config->div1) \| SCG_FIRCDIV_FIRCDIV2(config->div2) \| SCG_FIRCDIV_FIRCDIV3(config->div3); in CLOCK_InitFirc() 1120 …V_APLLDIV1(config->div1) \| SCG_APLLDIV_APLLDIV2(config->div2) \| SCG_APLLDIV_APLLDIV3(config->div3); in CLOCK_InitAuxPll() 1426 …V_SPLLDIV1(config->div1) \| SCG_SPLLDIV_SPLLDIV2(config->div2) \| SCG_SPLLDIV_SPLLDIV3(config->div3); in CLOCK_InitSysPll()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/MCIMX7U5/drivers/
D	fsl_clock.h	`631 scg_async_clk_div_t div3; /!< SOSCDIV3 value. / member 661 scg_async_clk_div_t div3; /!< SIRCDIV3 value. / member 746 scg_async_clk_div_t div3; /!< FIRCDIV3 value. / member 789 scg_async_clk_div_t div3; /!< SPLLDIV3 value. / member 853 scg_async_clk_div_t div3; /!< APLLDIV3 value. / member`
D	fsl_clock.c	603 …V_SOSCDIV1(config->div1) \| SCG_SOSCDIV_SOSCDIV2(config->div2) \| SCG_SOSCDIV_SOSCDIV3(config->div3); in CLOCK_InitSysOsc() 754 …V_SIRCDIV1(config->div1) \| SCG_SIRCDIV_SIRCDIV2(config->div2) \| SCG_SIRCDIV_SIRCDIV3(config->div3); in CLOCK_InitSirc() 900 …V_FIRCDIV1(config->div1) \| SCG_FIRCDIV_FIRCDIV2(config->div2) \| SCG_FIRCDIV_FIRCDIV3(config->div3); in CLOCK_InitFirc() 1120 …V_APLLDIV1(config->div1) \| SCG_APLLDIV_APLLDIV2(config->div2) \| SCG_APLLDIV_APLLDIV3(config->div3); in CLOCK_InitAuxPll() 1426 …V_SPLLDIV1(config->div1) \| SCG_SPLLDIV_SPLLDIV2(config->div2) \| SCG_SPLLDIV_SPLLDIV3(config->div3); in CLOCK_InitSysPll()
/hal_nxp-3.5.0/mcux/mcux-sdk/devices/K32L3A60/drivers/
D	fsl_clock.c	`400 …V_SIRCDIV1(config->div1) \| SCG_SIRCDIV_SIRCDIV2(config->div2) \| SCG_SIRCDIV_SIRCDIV3(config->div3); in CLOCK_InitSirc() 537 …V_FIRCDIV1(config->div1) \| SCG_FIRCDIV_FIRCDIV2(config->div2) \| SCG_FIRCDIV_FIRCDIV3(config->div3); in CLOCK_InitFirc() 719 SCG_LPFLLDIV_LPFLLDIV3(config->div3); in CLOCK_InitLpFll()`
D	fsl_clock.h	`517 scg_async_clk_div_t div3; /!< SIRCDIV3 value. / member 601 scg_async_clk_div_t div3; /!< FIRCDIV3 value. / member 684 scg_async_clk_div_t div3; /!< LPFLLDIV3 value. / member`

TraceRecorderSource-2.7.6
TraceRecorderSource-3.4.0
Zephyr-Core-2.7.6
Zephyr-Core-3.4.0
Zephyr-Core-3.5.0
Zephyr-Core-3.6.0
Zephyr-Core-3.7.0
acpica-3.5.0
acpica-3.6.0
acpica-3.7.0
babblesim_base-3.4.0
babblesim_base-3.6.0-3.5.0
babblesim_base-3.7.0
babblesim_ext_2G4_channel_NtNcable-3.7.0-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_channel_multiatt-3.4.0
babblesim_ext_2G4_channel_multiatt-3.7.0-3.6.0-3.5.0
babblesim_ext_2G4_device_WLAN_actmod-3.7.0-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_burst_interferer-3.7.0-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_playback-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_device_playback-3.7.0
babblesim_ext_2G4_libPhyComv1-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_libPhyComv1-3.7.0
babblesim_ext_2G4_modem_BLE_simple-3.4.0
babblesim_ext_2G4_modem_BLE_simple-3.6.0-3.5.0
babblesim_ext_2G4_modem_BLE_simple-3.7.0
babblesim_ext_2G4_modem_magic-3.6.0-3.5.0-3.4.0
babblesim_ext_2G4_modem_magic-3.7.0
babblesim_ext_2G4_phy_v1-3.4.0
babblesim_ext_2G4_phy_v1-3.6.0-3.5.0
babblesim_ext_2G4_phy_v1-3.7.0
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