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Searched refs:MCG_SC_FCRDIV_SHIFT (Results 1 – 25 of 44) sorted by relevance

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/hal_nxp-2.7.6/mcux/devices/MKW41Z4/
Dsystem_MKW41Z4.c164 Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); in SystemCoreClockUpdate()
Dfsl_clock.c102 #define MCG_SC_FCRDIV_VAL ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)
/hal_nxp-2.7.6/mcux/devices/MKW21Z4/
Dsystem_MKW21Z4.c163 Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); in SystemCoreClockUpdate()
/hal_nxp-2.7.6/mcux/devices/MKW31Z4/
Dsystem_MKW31Z4.c164 Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); in SystemCoreClockUpdate()
/hal_nxp-2.7.6/mcux/devices/MKL25Z4/
Dsystem_MKL25Z4.c204 Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); in SystemCoreClockUpdate()
Dfsl_clock.c74 #define MCG_SC_FCRDIV_VAL ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)
/hal_nxp-2.7.6/mcux/devices/MKV58F24/
Dsystem_MKV58F24.c182 …k = CPU_INT_FAST_CLK_HZ / (1 << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); /* Fast… in SystemCoreClockUpdate()
Dfsl_clock.c56 #define MCG_SC_FCRDIV_VAL ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)
/hal_nxp-2.7.6/mcux/devices/MKV56F24/
Dsystem_MKV56F24.c182 …k = CPU_INT_FAST_CLK_HZ / (1 << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); /* Fast… in SystemCoreClockUpdate()
Dfsl_clock.c56 #define MCG_SC_FCRDIV_VAL ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)
/hal_nxp-2.7.6/mcux/devices/MK22F51212/
Dsystem_MK22F51212.c208 Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); in SystemCoreClockUpdate()
Dfsl_clock.c56 #define MCG_SC_FCRDIV_VAL ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)
/hal_nxp-2.7.6/mcux/devices/MK64F12/
Dsystem_MK64F12.c212 Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); in SystemCoreClockUpdate()
Dfsl_clock.c56 #define MCG_SC_FCRDIV_VAL ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)
/hal_nxp-2.7.6/mcux/devices/MK80F25615/
Dsystem_MK80F25615.c188 Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); in SystemCoreClockUpdate()
Dfsl_clock.c56 #define MCG_SC_FCRDIV_VAL ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)
/hal_nxp-2.7.6/mcux/devices/MK82F25615/
Dsystem_MK82F25615.c182 Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); in SystemCoreClockUpdate()
/hal_nxp-2.7.6/mcux/devices/MK66F18/
Dsystem_MK66F18.c212 Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); in SystemCoreClockUpdate()
/hal_nxp-2.7.6/mcux/devices/MKW22D5/
Dsystem_MKW22D5.c217 Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); in SystemCoreClockUpdate()
Dfsl_clock.c74 #define MCG_SC_FCRDIV_VAL ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)
/hal_nxp-2.7.6/mcux/devices/MKW24D5/
Dsystem_MKW24D5.c217 Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); in SystemCoreClockUpdate()
Dfsl_clock.c74 #define MCG_SC_FCRDIV_VAL ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)
/hal_nxp-2.7.6/mcux/devices/MKW30Z4/
Dsystem_MKW30Z4.c280 Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); in SystemCoreClockUpdate()
/hal_nxp-2.7.6/mcux/devices/MKW20Z4/
Dsystem_MKW20Z4.c280 Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); in SystemCoreClockUpdate()
/hal_nxp-2.7.6/mcux/devices/MKW40Z4/
Dsystem_MKW40Z4.c280 Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT)); in SystemCoreClockUpdate()

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