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Searched refs:MCG_C2_RANGE_MASK (Results 1 – 25 of 41) sorted by relevance

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/hal_nxp-2.7.6/mcux/devices/MKW41Z4/
Dfsl_clock.c73 #if (defined(MCG_C2_RANGE_MASK) && !(defined(MCG_C2_RANGE0_MASK)))
74 #define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK
101 #define MCG_C2_RANGE_VAL ((MCG->C2 & MCG_C2_RANGE_MASK) >> MCG_C2_RANGE_SHIFT)
Dsystem_MKW41Z4.c111 if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) { in SystemCoreClockUpdate()
/hal_nxp-2.7.6/mcux/devices/MKW21Z4/
Dsystem_MKW21Z4.c110 if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) { in SystemCoreClockUpdate()
/hal_nxp-2.7.6/mcux/devices/MKW31Z4/
Dsystem_MKW31Z4.c111 if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) { in SystemCoreClockUpdate()
/hal_nxp-2.7.6/mcux/devices/MKL25Z4/
Dfsl_clock.c45 #if (defined(MCG_C2_RANGE_MASK) && !(defined(MCG_C2_RANGE0_MASK)))
46 #define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK
73 #define MCG_C2_RANGE_VAL ((MCG->C2 & MCG_C2_RANGE_MASK) >> MCG_C2_RANGE_SHIFT)
/hal_nxp-2.7.6/mcux/devices/MKV58F24/
Dsystem_MKV58F24.c121 if ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x0U) { in SystemCoreClockUpdate()
Dfsl_clock.c27 #if (defined(MCG_C2_RANGE_MASK) && !(defined(MCG_C2_RANGE0_MASK)))
28 #define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK
55 #define MCG_C2_RANGE_VAL ((MCG->C2 & MCG_C2_RANGE_MASK) >> MCG_C2_RANGE_SHIFT)
/hal_nxp-2.7.6/mcux/devices/MKV56F24/
Dsystem_MKV56F24.c121 if ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x0U) { in SystemCoreClockUpdate()
Dfsl_clock.c27 #if (defined(MCG_C2_RANGE_MASK) && !(defined(MCG_C2_RANGE0_MASK)))
28 #define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK
55 #define MCG_C2_RANGE_VAL ((MCG->C2 & MCG_C2_RANGE_MASK) >> MCG_C2_RANGE_SHIFT)
/hal_nxp-2.7.6/mcux/devices/MKW22D5/
Dfsl_clock.c45 #if (defined(MCG_C2_RANGE_MASK) && !(defined(MCG_C2_RANGE0_MASK)))
46 #define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK
73 #define MCG_C2_RANGE_VAL ((MCG->C2 & MCG_C2_RANGE_MASK) >> MCG_C2_RANGE_SHIFT)
/hal_nxp-2.7.6/mcux/devices/MKW24D5/
Dfsl_clock.c45 #if (defined(MCG_C2_RANGE_MASK) && !(defined(MCG_C2_RANGE0_MASK)))
46 #define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK
73 #define MCG_C2_RANGE_VAL ((MCG->C2 & MCG_C2_RANGE_MASK) >> MCG_C2_RANGE_SHIFT)
/hal_nxp-2.7.6/mcux/devices/MK22F51212/
Dsystem_MK22F51212.c147 if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((tmpC7 & MCG_C7_OSCSEL_MASK) != 0x01U)) { in SystemCoreClockUpdate()
Dfsl_clock.c27 #if (defined(MCG_C2_RANGE_MASK) && !(defined(MCG_C2_RANGE0_MASK)))
28 #define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK
55 #define MCG_C2_RANGE_VAL ((MCG->C2 & MCG_C2_RANGE_MASK) >> MCG_C2_RANGE_SHIFT)
DMK22F51212.h8722 #define MCG_C2_RANGE_MASK (0x30U) macro
8729 …x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_RANGE_SHIFT)) & MCG_C2_RANGE_MASK)
15328 #define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK
/hal_nxp-2.7.6/mcux/devices/MK64F12/
Dsystem_MK64F12.c151 if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((tmpC7 & MCG_C7_OSCSEL_MASK) != 0x01U)) { in SystemCoreClockUpdate()
Dfsl_clock.c27 #if (defined(MCG_C2_RANGE_MASK) && !(defined(MCG_C2_RANGE0_MASK)))
28 #define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK
55 #define MCG_C2_RANGE_VAL ((MCG->C2 & MCG_C2_RANGE_MASK) >> MCG_C2_RANGE_SHIFT)
/hal_nxp-2.7.6/mcux/devices/MK80F25615/
Dsystem_MK80F25615.c126 if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((tmpC7 & MCG_C7_OSCSEL_MASK) != 0x01U)) { in SystemCoreClockUpdate()
Dfsl_clock.c27 #if (defined(MCG_C2_RANGE_MASK) && !(defined(MCG_C2_RANGE0_MASK)))
28 #define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK
55 #define MCG_C2_RANGE_VAL ((MCG->C2 & MCG_C2_RANGE_MASK) >> MCG_C2_RANGE_SHIFT)
/hal_nxp-2.7.6/mcux/devices/MK82F25615/
Dsystem_MK82F25615.c120 if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((tmpC7 & MCG_C7_OSCSEL_MASK) != 0x01U)) { in SystemCoreClockUpdate()
Dfsl_clock.c27 #if (defined(MCG_C2_RANGE_MASK) && !(defined(MCG_C2_RANGE0_MASK)))
28 #define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK
55 #define MCG_C2_RANGE_VAL ((MCG->C2 & MCG_C2_RANGE_MASK) >> MCG_C2_RANGE_SHIFT)
/hal_nxp-2.7.6/mcux/devices/MK66F18/
Dsystem_MK66F18.c132 if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((tmpC7 & MCG_C7_OSCSEL_MASK) != 0x01U)) { in SystemCoreClockUpdate()
Dfsl_clock.c27 #if (defined(MCG_C2_RANGE_MASK) && !(defined(MCG_C2_RANGE0_MASK)))
28 #define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK
55 #define MCG_C2_RANGE_VAL ((MCG->C2 & MCG_C2_RANGE_MASK) >> MCG_C2_RANGE_SHIFT)
/hal_nxp-2.7.6/mcux/devices/MKW30Z4/
Dsystem_MKW30Z4.c227 if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) { in SystemCoreClockUpdate()
/hal_nxp-2.7.6/mcux/devices/MKW20Z4/
Dsystem_MKW20Z4.c227 if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) { in SystemCoreClockUpdate()
/hal_nxp-2.7.6/mcux/devices/MKW40Z4/
Dsystem_MKW40Z4.c227 if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) { in SystemCoreClockUpdate()

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