| /hal_microchip-latest/pic32c/pic32cxsg/include/fixups/component/ |
| D | pac_component_fixup_pic32cxsg.h | 59 __I uint32_t FLASH_:1; /*!< bit: 0 FLASH */
60 __I uint32_t FLASH_ALT_:1; /*!< bit: 1 FLASH_ALT */
61 __I uint32_t SEEPROM_:1; /*!< bit: 2 SEEPROM */
62 __I uint32_t RAMCM4S_:1; /*!< bit: 3 RAMCM4S */
63 __I uint32_t RAMPPPDSU_:1; /*!< bit: 4 RAMPPPDSU */
64 __I uint32_t RAMDMAWR_:1; /*!< bit: 5 RAMDMAWR */
65 __I uint32_t RAMDMACICM_:1; /*!< bit: 6 RAMDMACICM */
66 __I uint32_t HPB0_:1; /*!< bit: 7 HPB0 */
67 __I uint32_t HPB1_:1; /*!< bit: 8 HPB1 */
68 __I uint32_t HPB2_:1; /*!< bit: 9 HPB2 */
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| D | usb_component_fixup_pic32cxsg.h | 216 __I uint8_t TRCPT0:1; /*!< bit: 0 Transfer Complete 0 */
217 __I uint8_t TRCPT1:1; /*!< bit: 1 Transfer Complete 1 */
218 __I uint8_t TRFAIL0:1; /*!< bit: 2 Error Flow 0 */
219 __I uint8_t TRFAIL1:1; /*!< bit: 3 Error Flow 1 */
220 __I uint8_t RXSTP:1; /*!< bit: 4 Received Setup */
221 __I uint8_t STALL0:1; /*!< bit: 5 Stall 0 In/out */
222 __I uint8_t STALL1:1; /*!< bit: 6 Stall 1 In/out */
223 __I uint8_t :1; /*!< bit: 7 Reserved */
226 __I uint8_t TRCPT:2; /*!< bit: 0.. 1 Transfer Complete x */
227 __I uint8_t TRFAIL:2; /*!< bit: 2.. 3 Error Flow x */
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| D | oscctrl_component_fixup_pic32cxsg.h | 169 __I uint32_t XOSCRDY0:1; /*!< bit: 0 XOSC 0 Ready */
170 __I uint32_t XOSCRDY1:1; /*!< bit: 1 XOSC 1 Ready */
171 __I uint32_t XOSCFAIL0:1; /*!< bit: 2 XOSC 0 Clock Failure Detector */
172 __I uint32_t XOSCFAIL1:1; /*!< bit: 3 XOSC 1 Clock Failure Detector */
173 __I uint32_t :4; /*!< bit: 4.. 7 Reserved */
174 __I uint32_t DFLLRDY:1; /*!< bit: 8 DFLL Ready */
175 __I uint32_t DFLLOOB:1; /*!< bit: 9 DFLL Out Of Bounds */
176 __I uint32_t DFLLLCKF:1; /*!< bit: 10 DFLL Lock Fine */
177 __I uint32_t DFLLLCKC:1; /*!< bit: 11 DFLL Lock Coarse */
178 __I uint32_t DFLLRCS:1; /*!< bit: 12 DFLL Reference Clock Stopped */
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| D | i2s_component_fixup_pic32cxsg.h | 122 __I uint16_t RXRDY0:1; /*!< bit: 0 Receive Ready 0 */
123 __I uint16_t RXRDY1:1; /*!< bit: 1 Receive Ready 1 */
124 __I uint16_t :2; /*!< bit: 2.. 3 Reserved */
125 __I uint16_t RXOR0:1; /*!< bit: 4 Receive Overrun 0 */
126 __I uint16_t RXOR1:1; /*!< bit: 5 Receive Overrun 1 */
127 __I uint16_t :2; /*!< bit: 6.. 7 Reserved */
128 __I uint16_t TXRDY0:1; /*!< bit: 8 Transmit Ready 0 */
129 __I uint16_t TXRDY1:1; /*!< bit: 9 Transmit Ready 1 */
130 __I uint16_t :2; /*!< bit: 10..11 Reserved */
131 __I uint16_t TXUR0:1; /*!< bit: 12 Transmit Underrun 0 */
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| D | rtc_component_fixup_pic32cxsg.h | 386 __I uint16_t PER0:1; /*!< bit: 0 Periodic Interval 0 */
387 __I uint16_t PER1:1; /*!< bit: 1 Periodic Interval 1 */
388 __I uint16_t PER2:1; /*!< bit: 2 Periodic Interval 2 */
389 __I uint16_t PER3:1; /*!< bit: 3 Periodic Interval 3 */
390 __I uint16_t PER4:1; /*!< bit: 4 Periodic Interval 4 */
391 __I uint16_t PER5:1; /*!< bit: 5 Periodic Interval 5 */
392 __I uint16_t PER6:1; /*!< bit: 6 Periodic Interval 6 */
393 __I uint16_t PER7:1; /*!< bit: 7 Periodic Interval 7 */
394 __I uint16_t CMP0:1; /*!< bit: 8 Compare 0 */
395 __I uint16_t CMP1:1; /*!< bit: 9 Compare 1 */
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| D | gmac_component_fixup_pic32cxsg.h | 1296 …__I GMAC_NSR_Type NSR; /**< \brief Offset: 0x008 (R/ 32) Network Status Regi…
1306 …__I GMAC_IMR_Type IMR; /**< \brief Offset: 0x030 (R/ 32) Interrupt Mask Regi…
1308 …__I GMAC_RPQ_Type RPQ; /**< \brief Offset: 0x038 (R/ 32) Received Pause Quan…
1328 …__I GMAC_EFTSH_Type EFTSH; /**< \brief Offset: 0x0E8 (R/ 32) PTP Event Frame Tra…
1329 …__I GMAC_EFRSH_Type EFRSH; /**< \brief Offset: 0x0EC (R/ 32) PTP Event Frame Rec…
1330 …__I GMAC_PEFTSH_Type PEFTSH; /**< \brief Offset: 0x0F0 (R/ 32) PTP Peer Event Fram…
1331 …__I GMAC_PEFRSH_Type PEFRSH; /**< \brief Offset: 0x0F4 (R/ 32) PTP Peer Event Fram…
1333 …__I GMAC_OTLO_Type OTLO; /**< \brief Offset: 0x100 (R/ 32) Octets Transmitted …
1334 …__I GMAC_OTHI_Type OTHI; /**< \brief Offset: 0x104 (R/ 32) Octets Transmitted …
1335 …__I GMAC_FT_Type FT; /**< \brief Offset: 0x108 (R/ 32) Frames Transmitted …
[all …]
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| D | nvmctrl_component_fixup_pic32cxsg.h | 100 __I uint16_t DONE:1; /*!< bit: 0 Command Done */
101 __I uint16_t ADDRE:1; /*!< bit: 1 Address Error */
102 __I uint16_t PROGE:1; /*!< bit: 2 Programming Error */
103 __I uint16_t LOCKE:1; /*!< bit: 3 Lock Error */
104 __I uint16_t ECCSE:1; /*!< bit: 4 ECC Single Error */
105 __I uint16_t ECCDE:1; /*!< bit: 5 ECC Dual Error */
106 __I uint16_t NVME:1; /*!< bit: 6 NVM Error */
107 __I uint16_t SUSP:1; /*!< bit: 7 Suspended Write Or Erase Operation */
108 __I uint16_t SEESFULL:1; /*!< bit: 8 Active SEES Full */
109 __I uint16_t SEESOVF:1; /*!< bit: 9 Active SEES Overflow */
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| D | dsu_component_fixup_pic32cxsg.h | 314 __I DSU_STATUSB_Type STATUSB; /**< \brief Offset: 0x0002 (R/ 8) Status B */
320 …__I DSU_DID_Type DID; /**< \brief Offset: 0x0018 (R/ 32) Device Identificat…
325 …__I DSU_ENTRY0_Type ENTRY0; /**< \brief Offset: 0x1000 (R/ 32) CoreSight ROM Tabl…
326 …__I DSU_ENTRY1_Type ENTRY1; /**< \brief Offset: 0x1004 (R/ 32) CoreSight ROM Tabl…
327 …__I DSU_END_Type END; /**< \brief Offset: 0x1008 (R/ 32) CoreSight ROM Tabl…
329 …__I DSU_MEMTYPE_Type MEMTYPE; /**< \brief Offset: 0x1FCC (R/ 32) CoreSight ROM Tabl…
330 …__I DSU_PID4_Type PID4; /**< \brief Offset: 0x1FD0 (R/ 32) Peripheral Identif…
331 …__I DSU_PID5_Type PID5; /**< \brief Offset: 0x1FD4 (R/ 32) Peripheral Identif…
332 …__I DSU_PID6_Type PID6; /**< \brief Offset: 0x1FD8 (R/ 32) Peripheral Identif…
333 …__I DSU_PID7_Type PID7; /**< \brief Offset: 0x1FDC (R/ 32) Peripheral Identif…
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| D | dac_component_fixup_pic32cxsg.h | 107 __I uint8_t UNDERRUN0:1; /*!< bit: 0 Result 0 Underrun */
108 __I uint8_t UNDERRUN1:1; /*!< bit: 1 Result 1 Underrun */
109 __I uint8_t EMPTY0:1; /*!< bit: 2 Data Buffer 0 Empty */
110 __I uint8_t EMPTY1:1; /*!< bit: 3 Data Buffer 1 Empty */
111 __I uint8_t :1; /*!< bit: 4 Deprecated */
112 __I uint8_t :1; /*!< bit: 5 Deprecated */
113 __I uint8_t :1; /*!< bit: 6 Deprecated */
114 __I uint8_t :1; /*!< bit: 7 Deprecated */
117 __I uint8_t UNDERRUN:2; /*!< bit: 0.. 1 Result x Underrun */
118 __I uint8_t EMPTY:2; /*!< bit: 2.. 3 Data Buffer x Empty */
[all …]
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| D | supc_component_fixup_pic32cxsg.h | 48 __I uint32_t BOD33RDY:1; /*!< bit: 0 BOD33 Ready */
49 __I uint32_t BOD33DET:1; /*!< bit: 1 BOD33 Detection */
50 __I uint32_t B33SRDY:1; /*!< bit: 2 BOD33 Synchronization Ready */
51 __I uint32_t :5; /*!< bit: 3.. 7 Reserved */
52 __I uint32_t VREGRDY:1; /*!< bit: 8 Voltage Regulator Ready */
53 __I uint32_t :1; /*!< bit: 9 Reserved */
54 __I uint32_t VCORERDY:1; /*!< bit: 10 VDDCORE Ready */
55 __I uint32_t :21; /*!< bit: 11..31 Reserved */
184 …__I SUPC_STATUS_Type STATUS; /**< \brief Offset: 0x0C (R/ 32) Power and Clocks Sta…
191 …__I SUPC_BKIN_Type BKIN; /**< \brief Offset: 0x28 (R/ 32) Backup Input Control…
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| D | qspi_component_fixup_pic32cxsg.h | 119 __I uint32_t RXC:1; /*!< bit: 0 Receive Data Register Full */
120 __I uint32_t DRE:1; /*!< bit: 1 Transmit Data Register Empty */
121 __I uint32_t TXC:1; /*!< bit: 2 Transmission Complete */
122 __I uint32_t ERROR:1; /*!< bit: 3 Overrun Error */
123 __I uint32_t :4; /*!< bit: 4.. 7 Reserved */
124 __I uint32_t CSRISE:1; /*!< bit: 8 Chip Select Rise */
125 __I uint32_t :1; /*!< bit: 9 Reserved */
126 __I uint32_t INSTREND:1; /*!< bit: 10 Instruction End */
127 __I uint32_t :21; /*!< bit: 11..31 Reserved */
220 __I QSPI_RXDATA_Type RXDATA; /**< \brief Offset: 0x0C (R/ 32) Receive Data */
[all …]
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| D | ac_component_fixup_pic32cxsg.h | 112 __I uint8_t COMP0:1; /*!< bit: 0 Comparator 0 */
113 __I uint8_t COMP1:1; /*!< bit: 1 Comparator 1 */
114 __I uint8_t :2; /*!< bit: 2.. 3 Reserved */
115 __I uint8_t WIN0:1; /*!< bit: 4 Window 0 */
116 __I uint8_t :3; /*!< bit: 5.. 7 Reserved */
119 __I uint8_t COMP:2; /*!< bit: 0.. 1 Comparator x */
120 __I uint8_t :2; /*!< bit: 2.. 3 Reserved */
121 __I uint8_t WIN:1; /*!< bit: 4 Window x */
122 __I uint8_t :3; /*!< bit: 5.. 7 Reserved */
265 __I AC_STATUSA_Type STATUSA; /**< \brief Offset: 0x07 (R/ 8) Status A */
[all …]
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| D | tcc_component_fixup_pic32cxsg.h | 332 __I uint32_t OVF:1; /*!< bit: 0 Overflow */
333 __I uint32_t TRG:1; /*!< bit: 1 Retrigger */
334 __I uint32_t CNT:1; /*!< bit: 2 Counter */
335 __I uint32_t ERR:1; /*!< bit: 3 Error */
336 __I uint32_t :6; /*!< bit: 4.. 9 Reserved */
337 __I uint32_t UFS:1; /*!< bit: 10 Non-Recoverable Update Fault */
338 __I uint32_t DFS:1; /*!< bit: 11 Non-Recoverable Debug Fault */
339 __I uint32_t FAULTA:1; /*!< bit: 12 Recoverable Fault A */
340 __I uint32_t FAULTB:1; /*!< bit: 13 Recoverable Fault B */
341 __I uint32_t FAULT0:1; /*!< bit: 14 Non-Recoverable Fault 0 */
[all …]
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| D | pdec_component_fixup_pic32cxsg.h | 144 __I uint8_t OVF:1; /*!< bit: 0 Overflow/Underflow */
145 __I uint8_t ERR:1; /*!< bit: 1 Error */
146 __I uint8_t DIR:1; /*!< bit: 2 Direction Change */
147 __I uint8_t VLC:1; /*!< bit: 3 Velocity */
148 __I uint8_t MC0:1; /*!< bit: 4 Channel 0 Compare Match */
149 __I uint8_t MC1:1; /*!< bit: 5 Channel 1 Compare Match */
150 __I uint8_t :2; /*!< bit: 6.. 7 Reserved */
153 __I uint8_t :4; /*!< bit: 0.. 3 Reserved */
154 __I uint8_t MC:2; /*!< bit: 4.. 5 Channel x Compare Match */
155 __I uint8_t :2; /*!< bit: 6.. 7 Reserved */
[all …]
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| D | ramecc_component_fixup_pic32cxsg.h | 38 __I uint8_t SINGLEE:1; /*!< bit: 0 Single Bit ECC Error Interrupt */
39 __I uint8_t DUALE:1; /*!< bit: 1 Dual Bit ECC Error Interrupt */
40 __I uint8_t :6; /*!< bit: 2.. 7 Reserved */
86 __I RAMECC_STATUS_Type STATUS; /**< \brief Offset: 0x3 (R/ 8) Status */
87 __I RAMECC_ERRADDR_Type ERRADDR; /**< \brief Offset: 0x4 (R/ 32) Error Address */
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| /hal_microchip-latest/mpfs/mpfs_hal/common/nwc/ |
| D | mss_ddr_sgmii_phy_defs.h | 29 #ifndef __I
30 #define __I const volatile macro
234 __I uint32_t reserved_01 :6;
236 __I uint32_t reserved_02 :7;
237 __I uint32_t BLOCKID_DDR_PHY :16;
261 __I uint32_t Reserved :3;
274 __I uint32_t reserved :3;
280 __I uint32_t reserved2 :3;
297 __I uint32_t reserved_01 :6;
299 __I uint32_t reserved_02 :7;
[all …]
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| D | mss_ddr_sgmii_regs.h | 49 __I uint32_t reserved :31;
58 __I uint32_t reserved :8;
67 __I uint32_t reserved :14;
76 __I uint32_t reserved :29;
85 __I uint32_t reserved :28;
102 __I uint32_t reserved :28;
135 __I uint32_t reserved :20;
168 __I uint32_t reserved :22;
177 __I uint32_t reserved :22;
186 __I uint32_t reserved :31;
[all …]
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| D | mss_cfm.h | 85 __I uint32_t count0; /* Count x value */
86 __I uint32_t count1;
87 __I uint32_t count2;
88 __I uint32_t count3;
89 __I uint32_t count4;
90 __I uint32_t count5;
91 __I uint32_t count6;
92 __I uint32_t count7;
94 __I uint32_t reserved[4]; /*Reserved registers, padding structure */
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| D | mss_scb_nwc_regs.h | 28 #ifndef __I
29 #define __I const volatile macro
86 __I uint32_t IOC_REG1; /*!< Offset: 0x08 */
87 __I uint32_t IOC_REG2; /*!< Offset: 0x0c */
88 __I uint32_t IOC_REG3; /*!< Offset: 0x10 */
89 __I uint32_t IOC_REG4; /*!< Offset: 0x14 */
90 __I uint32_t IOC_REG5; /*!< Offset: 0x18 */
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| /hal_microchip-latest/mpfs/mpfs_hal/common/ |
| D | mss_sysreg.h | 35 #ifndef __I
37 #define __I volatile /*!< Defines 'read only' permis macro
40 #define __I volatile const /*!< Defines 'read only' permis
3635 __I uint32_t MSS_BUILD;
3638 __I uint32_t RESERVEDREG32B_1;
3639 __I uint32_t RESERVEDREG32B_2;
3640 __I uint32_t RESERVEDREG32B_3;
3641 __I uint32_t RESERVEDREG32B_4;
3642 __I uint32_t RESERVEDREG32B_5;
3676 __I uint32_t RESERVEDREG32B_6;
[all …]
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| /hal_microchip-latest/mec/ |
| D | MCHP_MEC1701.h | 305 …__I uint32_t VCC_PWRGD_STATUS: 1; /*!< [2..2] Indicates the status of VCC_PWRGD. 0 = P…
307 …__I uint32_t RESET_HOST_STATUS: 1; /*!< [3..3] Indicates the status of RESET_VCC. 0 = r…
321 …__I uint32_t _32K_ACTIVE: 1; /*!< [10..10] 32K_ACTIVE (32K_ACTIVE) …
322 …__I uint32_t PCICLK_ACTIVE: 1; /*!< [11..11] PCICLK_ACTIVE (PCICLK_ACTIVE) …
323 …__I uint32_t ESPI_CLK_ACTIVE: 1; /*!< [12..12] ESPI_CLK_ACTIVE …
349 __I uint32_t RESERVED[5];
476 __I uint32_t RESERVED1[3];
603 __I uint32_t RESERVED2[3];
756 __I uint8_t RESERVED[3];
757 …__I uint32_t DATA_PACKET; /*!< (@ 0x40002404) Debug register that has the …
[all …]
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| /hal_microchip-latest/pic32c/pic32cxsg/include/pic32cxsg60/component/ |
| D | dsu.h | 396 __I uint8_t DSU_STATUSB; /**< Offset: 0x02 (R/ 8) Status B */
397 __I uint8_t Reserved1[0x01];
402 …__I uint32_t DSU_DID; /**< Offset: 0x18 (R/ 32) Device Identi…
404 __I uint8_t Reserved2[0xD0];
406 __I uint8_t Reserved3[0xF08];
407 …__I uint32_t DSU_ENTRY0; /**< Offset: 0x1000 (R/ 32) CoreSight R…
408 …__I uint32_t DSU_ENTRY1; /**< Offset: 0x1004 (R/ 32) CoreSight R…
409 …__I uint32_t DSU_END; /**< Offset: 0x1008 (R/ 32) CoreSight R…
410 __I uint8_t Reserved4[0xFC0];
411 …__I uint32_t DSU_MEMTYPE; /**< Offset: 0x1FCC (R/ 32) CoreSight R…
[all …]
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| /hal_microchip-latest/pic32c/pic32cxsg/include/pic32cxsg41/component/ |
| D | dsu.h | 396 __I uint8_t DSU_STATUSB; /* Offset: 0x02 (R/ 8) Status B */
397 __I uint8_t Reserved1[0x01];
402 …__I uint32_t DSU_DID; /* Offset: 0x18 (R/ 32) Device Identifi…
404 __I uint8_t Reserved2[0xD0];
406 __I uint8_t Reserved3[0xF08];
407 …__I uint32_t DSU_ENTRY0; /* Offset: 0x1000 (R/ 32) CoreSight ROM…
408 …__I uint32_t DSU_ENTRY1; /* Offset: 0x1004 (R/ 32) CoreSight ROM…
409 …__I uint32_t DSU_END; /* Offset: 0x1008 (R/ 32) CoreSight ROM…
410 __I uint8_t Reserved4[0xFC0];
411 …__I uint32_t DSU_MEMTYPE; /* Offset: 0x1FCC (R/ 32) CoreSight ROM…
[all …]
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| D | gmac.h | 1615 …__I uint32_t GMAC_NSR; /* Offset: 0x08 (R/ 32) Network Status …
1625 …__I uint32_t GMAC_IMR; /* Offset: 0x30 (R/ 32) Interrupt Mask …
1627 …__I uint32_t GMAC_RPQ; /* Offset: 0x38 (R/ 32) Received Pause …
1632 __I uint8_t Reserved1[0x34];
1643 __I uint8_t Reserved2[0x0C];
1647 …__I uint32_t GMAC_EFTSH; /* Offset: 0xE8 (R/ 32) PTP Event Frame…
1648 …__I uint32_t GMAC_EFRSH; /* Offset: 0xEC (R/ 32) PTP Event Frame…
1649 …__I uint32_t GMAC_PEFTSH; /* Offset: 0xF0 (R/ 32) PTP Peer Event …
1650 …__I uint32_t GMAC_PEFRSH; /* Offset: 0xF4 (R/ 32) PTP Peer Event …
1651 __I uint8_t Reserved3[0x08];
[all …]
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| /hal_microchip-latest/pic32c/pic32cxsg/include/pic32cxsg61/component/ |
| D | dsu.h | 396 __I uint8_t DSU_STATUSB; /**< Offset: 0x02 (R/ 8) Status B */
397 __I uint8_t Reserved1[0x01];
402 …__I uint32_t DSU_DID; /**< Offset: 0x18 (R/ 32) Device Identi…
404 __I uint8_t Reserved2[0xD0];
406 __I uint8_t Reserved3[0xF08];
407 …__I uint32_t DSU_ENTRY0; /**< Offset: 0x1000 (R/ 32) CoreSight R…
408 …__I uint32_t DSU_ENTRY1; /**< Offset: 0x1004 (R/ 32) CoreSight R…
409 …__I uint32_t DSU_END; /**< Offset: 0x1008 (R/ 32) CoreSight R…
410 __I uint8_t Reserved4[0xFC0];
411 …__I uint32_t DSU_MEMTYPE; /**< Offset: 0x1FCC (R/ 32) CoreSight R…
[all …]
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