1 /* 2 * Component description for DSU 3 * 4 * Copyright (c) 2024 Microchip Technology Inc. and its subsidiaries. 5 * 6 * Licensed under the Apache License, Version 2.0 (the "License"); 7 * you may not use this file except in compliance with the License. 8 * You may obtain a copy of the License at 9 * 10 * http://www.apache.org/licenses/LICENSE-2.0 11 * 12 * Unless required by applicable law or agreed to in writing, software 13 * distributed under the License is distributed on an "AS IS" BASIS, 14 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 * See the License for the specific language governing permissions and 16 * limitations under the License. 17 * 18 */ 19 20 /* file generated from device description file (ATDF) version 2023-03-17T09:48:34Z */ 21 #ifndef _PIC32CXSG41_DSU_COMPONENT_H_ 22 #define _PIC32CXSG41_DSU_COMPONENT_H_ 23 24 /* ************************************************************************** */ 25 /* SOFTWARE API DEFINITION FOR DSU */ 26 /* ************************************************************************** */ 27 28 /* -------- DSU_CTRL : (DSU Offset: 0x00) ( /W 8) Control -------- */ 29 #define DSU_CTRL_RESETVALUE _UINT8_(0x00) /* (DSU_CTRL) Control Reset Value */ 30 31 #define DSU_CTRL_SWRST_Pos _UINT8_(0) /* (DSU_CTRL) Software Reset Position */ 32 #define DSU_CTRL_SWRST_Msk (_UINT8_(0x1) << DSU_CTRL_SWRST_Pos) /* (DSU_CTRL) Software Reset Mask */ 33 #define DSU_CTRL_SWRST(value) (DSU_CTRL_SWRST_Msk & (_UINT8_(value) << DSU_CTRL_SWRST_Pos)) /* Assignment of value for SWRST in the DSU_CTRL register */ 34 #define DSU_CTRL_CRC_Pos _UINT8_(2) /* (DSU_CTRL) 32-bit Cyclic Redundancy Code Position */ 35 #define DSU_CTRL_CRC_Msk (_UINT8_(0x1) << DSU_CTRL_CRC_Pos) /* (DSU_CTRL) 32-bit Cyclic Redundancy Code Mask */ 36 #define DSU_CTRL_CRC(value) (DSU_CTRL_CRC_Msk & (_UINT8_(value) << DSU_CTRL_CRC_Pos)) /* Assignment of value for CRC in the DSU_CTRL register */ 37 #define DSU_CTRL_MBIST_Pos _UINT8_(3) /* (DSU_CTRL) Memory built-in self-test Position */ 38 #define DSU_CTRL_MBIST_Msk (_UINT8_(0x1) << DSU_CTRL_MBIST_Pos) /* (DSU_CTRL) Memory built-in self-test Mask */ 39 #define DSU_CTRL_MBIST(value) (DSU_CTRL_MBIST_Msk & (_UINT8_(value) << DSU_CTRL_MBIST_Pos)) /* Assignment of value for MBIST in the DSU_CTRL register */ 40 #define DSU_CTRL_CE_Pos _UINT8_(4) /* (DSU_CTRL) Chip-Erase Position */ 41 #define DSU_CTRL_CE_Msk (_UINT8_(0x1) << DSU_CTRL_CE_Pos) /* (DSU_CTRL) Chip-Erase Mask */ 42 #define DSU_CTRL_CE(value) (DSU_CTRL_CE_Msk & (_UINT8_(value) << DSU_CTRL_CE_Pos)) /* Assignment of value for CE in the DSU_CTRL register */ 43 #define DSU_CTRL_Msk _UINT8_(0x1D) /* (DSU_CTRL) Register Mask */ 44 45 46 /* -------- DSU_STATUSA : (DSU Offset: 0x01) (R/W 8) Status A -------- */ 47 #define DSU_STATUSA_RESETVALUE _UINT8_(0x00) /* (DSU_STATUSA) Status A Reset Value */ 48 49 #define DSU_STATUSA_DONE_Pos _UINT8_(0) /* (DSU_STATUSA) Done Position */ 50 #define DSU_STATUSA_DONE_Msk (_UINT8_(0x1) << DSU_STATUSA_DONE_Pos) /* (DSU_STATUSA) Done Mask */ 51 #define DSU_STATUSA_DONE(value) (DSU_STATUSA_DONE_Msk & (_UINT8_(value) << DSU_STATUSA_DONE_Pos)) /* Assignment of value for DONE in the DSU_STATUSA register */ 52 #define DSU_STATUSA_CRSTEXT_Pos _UINT8_(1) /* (DSU_STATUSA) CPU Reset Phase Extension Position */ 53 #define DSU_STATUSA_CRSTEXT_Msk (_UINT8_(0x1) << DSU_STATUSA_CRSTEXT_Pos) /* (DSU_STATUSA) CPU Reset Phase Extension Mask */ 54 #define DSU_STATUSA_CRSTEXT(value) (DSU_STATUSA_CRSTEXT_Msk & (_UINT8_(value) << DSU_STATUSA_CRSTEXT_Pos)) /* Assignment of value for CRSTEXT in the DSU_STATUSA register */ 55 #define DSU_STATUSA_BERR_Pos _UINT8_(2) /* (DSU_STATUSA) Bus Error Position */ 56 #define DSU_STATUSA_BERR_Msk (_UINT8_(0x1) << DSU_STATUSA_BERR_Pos) /* (DSU_STATUSA) Bus Error Mask */ 57 #define DSU_STATUSA_BERR(value) (DSU_STATUSA_BERR_Msk & (_UINT8_(value) << DSU_STATUSA_BERR_Pos)) /* Assignment of value for BERR in the DSU_STATUSA register */ 58 #define DSU_STATUSA_FAIL_Pos _UINT8_(3) /* (DSU_STATUSA) Failure Position */ 59 #define DSU_STATUSA_FAIL_Msk (_UINT8_(0x1) << DSU_STATUSA_FAIL_Pos) /* (DSU_STATUSA) Failure Mask */ 60 #define DSU_STATUSA_FAIL(value) (DSU_STATUSA_FAIL_Msk & (_UINT8_(value) << DSU_STATUSA_FAIL_Pos)) /* Assignment of value for FAIL in the DSU_STATUSA register */ 61 #define DSU_STATUSA_PERR_Pos _UINT8_(4) /* (DSU_STATUSA) Protection Error Position */ 62 #define DSU_STATUSA_PERR_Msk (_UINT8_(0x1) << DSU_STATUSA_PERR_Pos) /* (DSU_STATUSA) Protection Error Mask */ 63 #define DSU_STATUSA_PERR(value) (DSU_STATUSA_PERR_Msk & (_UINT8_(value) << DSU_STATUSA_PERR_Pos)) /* Assignment of value for PERR in the DSU_STATUSA register */ 64 #define DSU_STATUSA_Msk _UINT8_(0x1F) /* (DSU_STATUSA) Register Mask */ 65 66 67 /* -------- DSU_STATUSB : (DSU Offset: 0x02) ( R/ 8) Status B -------- */ 68 #define DSU_STATUSB_RESETVALUE _UINT8_(0x00) /* (DSU_STATUSB) Status B Reset Value */ 69 70 #define DSU_STATUSB_PROT_Pos _UINT8_(0) /* (DSU_STATUSB) Protected Position */ 71 #define DSU_STATUSB_PROT_Msk (_UINT8_(0x1) << DSU_STATUSB_PROT_Pos) /* (DSU_STATUSB) Protected Mask */ 72 #define DSU_STATUSB_PROT(value) (DSU_STATUSB_PROT_Msk & (_UINT8_(value) << DSU_STATUSB_PROT_Pos)) /* Assignment of value for PROT in the DSU_STATUSB register */ 73 #define DSU_STATUSB_DBGPRES_Pos _UINT8_(1) /* (DSU_STATUSB) Debugger Present Position */ 74 #define DSU_STATUSB_DBGPRES_Msk (_UINT8_(0x1) << DSU_STATUSB_DBGPRES_Pos) /* (DSU_STATUSB) Debugger Present Mask */ 75 #define DSU_STATUSB_DBGPRES(value) (DSU_STATUSB_DBGPRES_Msk & (_UINT8_(value) << DSU_STATUSB_DBGPRES_Pos)) /* Assignment of value for DBGPRES in the DSU_STATUSB register */ 76 #define DSU_STATUSB_DCCD0_Pos _UINT8_(2) /* (DSU_STATUSB) Debug Communication Channel 0 Dirty Position */ 77 #define DSU_STATUSB_DCCD0_Msk (_UINT8_(0x1) << DSU_STATUSB_DCCD0_Pos) /* (DSU_STATUSB) Debug Communication Channel 0 Dirty Mask */ 78 #define DSU_STATUSB_DCCD0(value) (DSU_STATUSB_DCCD0_Msk & (_UINT8_(value) << DSU_STATUSB_DCCD0_Pos)) /* Assignment of value for DCCD0 in the DSU_STATUSB register */ 79 #define DSU_STATUSB_DCCD1_Pos _UINT8_(3) /* (DSU_STATUSB) Debug Communication Channel 1 Dirty Position */ 80 #define DSU_STATUSB_DCCD1_Msk (_UINT8_(0x1) << DSU_STATUSB_DCCD1_Pos) /* (DSU_STATUSB) Debug Communication Channel 1 Dirty Mask */ 81 #define DSU_STATUSB_DCCD1(value) (DSU_STATUSB_DCCD1_Msk & (_UINT8_(value) << DSU_STATUSB_DCCD1_Pos)) /* Assignment of value for DCCD1 in the DSU_STATUSB register */ 82 #define DSU_STATUSB_HPE_Pos _UINT8_(4) /* (DSU_STATUSB) Hot-Plugging Enable Position */ 83 #define DSU_STATUSB_HPE_Msk (_UINT8_(0x1) << DSU_STATUSB_HPE_Pos) /* (DSU_STATUSB) Hot-Plugging Enable Mask */ 84 #define DSU_STATUSB_HPE(value) (DSU_STATUSB_HPE_Msk & (_UINT8_(value) << DSU_STATUSB_HPE_Pos)) /* Assignment of value for HPE in the DSU_STATUSB register */ 85 #define DSU_STATUSB_CELCK_Pos _UINT8_(5) /* (DSU_STATUSB) Chip Erase Locked Position */ 86 #define DSU_STATUSB_CELCK_Msk (_UINT8_(0x1) << DSU_STATUSB_CELCK_Pos) /* (DSU_STATUSB) Chip Erase Locked Mask */ 87 #define DSU_STATUSB_CELCK(value) (DSU_STATUSB_CELCK_Msk & (_UINT8_(value) << DSU_STATUSB_CELCK_Pos)) /* Assignment of value for CELCK in the DSU_STATUSB register */ 88 #define DSU_STATUSB_CEHL_Pos _UINT8_(6) /* (DSU_STATUSB) Chip Erase Hard Locked Position */ 89 #define DSU_STATUSB_CEHL_Msk (_UINT8_(0x1) << DSU_STATUSB_CEHL_Pos) /* (DSU_STATUSB) Chip Erase Hard Locked Mask */ 90 #define DSU_STATUSB_CEHL(value) (DSU_STATUSB_CEHL_Msk & (_UINT8_(value) << DSU_STATUSB_CEHL_Pos)) /* Assignment of value for CEHL in the DSU_STATUSB register */ 91 #define DSU_STATUSB_Msk _UINT8_(0x7F) /* (DSU_STATUSB) Register Mask */ 92 93 #define DSU_STATUSB_DCCD_Pos _UINT8_(2) /* (DSU_STATUSB Position) Debug Communication Channel x Dirty */ 94 #define DSU_STATUSB_DCCD_Msk (_UINT8_(0x3) << DSU_STATUSB_DCCD_Pos) /* (DSU_STATUSB Mask) DCCD */ 95 #define DSU_STATUSB_DCCD(value) (DSU_STATUSB_DCCD_Msk & (_UINT8_(value) << DSU_STATUSB_DCCD_Pos)) 96 97 /* -------- DSU_ADDR : (DSU Offset: 0x04) (R/W 32) Address -------- */ 98 #define DSU_ADDR_RESETVALUE _UINT32_(0x00) /* (DSU_ADDR) Address Reset Value */ 99 100 #define DSU_ADDR_AMOD_Pos _UINT32_(0) /* (DSU_ADDR) Access Mode Position */ 101 #define DSU_ADDR_AMOD_Msk (_UINT32_(0x3) << DSU_ADDR_AMOD_Pos) /* (DSU_ADDR) Access Mode Mask */ 102 #define DSU_ADDR_AMOD(value) (DSU_ADDR_AMOD_Msk & (_UINT32_(value) << DSU_ADDR_AMOD_Pos)) /* Assignment of value for AMOD in the DSU_ADDR register */ 103 #define DSU_ADDR_ADDR_Pos _UINT32_(2) /* (DSU_ADDR) Address Position */ 104 #define DSU_ADDR_ADDR_Msk (_UINT32_(0x3FFFFFFF) << DSU_ADDR_ADDR_Pos) /* (DSU_ADDR) Address Mask */ 105 #define DSU_ADDR_ADDR(value) (DSU_ADDR_ADDR_Msk & (_UINT32_(value) << DSU_ADDR_ADDR_Pos)) /* Assignment of value for ADDR in the DSU_ADDR register */ 106 #define DSU_ADDR_Msk _UINT32_(0xFFFFFFFF) /* (DSU_ADDR) Register Mask */ 107 108 109 /* -------- DSU_LENGTH : (DSU Offset: 0x08) (R/W 32) Length -------- */ 110 #define DSU_LENGTH_RESETVALUE _UINT32_(0x00) /* (DSU_LENGTH) Length Reset Value */ 111 112 #define DSU_LENGTH_LENGTH_Pos _UINT32_(2) /* (DSU_LENGTH) Length Position */ 113 #define DSU_LENGTH_LENGTH_Msk (_UINT32_(0x3FFFFFFF) << DSU_LENGTH_LENGTH_Pos) /* (DSU_LENGTH) Length Mask */ 114 #define DSU_LENGTH_LENGTH(value) (DSU_LENGTH_LENGTH_Msk & (_UINT32_(value) << DSU_LENGTH_LENGTH_Pos)) /* Assignment of value for LENGTH in the DSU_LENGTH register */ 115 #define DSU_LENGTH_Msk _UINT32_(0xFFFFFFFC) /* (DSU_LENGTH) Register Mask */ 116 117 118 /* -------- DSU_DATA : (DSU Offset: 0x0C) (R/W 32) Data -------- */ 119 #define DSU_DATA_RESETVALUE _UINT32_(0x00) /* (DSU_DATA) Data Reset Value */ 120 121 #define DSU_DATA_DATA_Pos _UINT32_(0) /* (DSU_DATA) Data Position */ 122 #define DSU_DATA_DATA_Msk (_UINT32_(0xFFFFFFFF) << DSU_DATA_DATA_Pos) /* (DSU_DATA) Data Mask */ 123 #define DSU_DATA_DATA(value) (DSU_DATA_DATA_Msk & (_UINT32_(value) << DSU_DATA_DATA_Pos)) /* Assignment of value for DATA in the DSU_DATA register */ 124 #define DSU_DATA_Msk _UINT32_(0xFFFFFFFF) /* (DSU_DATA) Register Mask */ 125 126 127 /* -------- DSU_DCC : (DSU Offset: 0x10) (R/W 32) Debug Communication Channel n -------- */ 128 #define DSU_DCC_RESETVALUE _UINT32_(0x00) /* (DSU_DCC) Debug Communication Channel n Reset Value */ 129 130 #define DSU_DCC_DATA_Pos _UINT32_(0) /* (DSU_DCC) Data Position */ 131 #define DSU_DCC_DATA_Msk (_UINT32_(0xFFFFFFFF) << DSU_DCC_DATA_Pos) /* (DSU_DCC) Data Mask */ 132 #define DSU_DCC_DATA(value) (DSU_DCC_DATA_Msk & (_UINT32_(value) << DSU_DCC_DATA_Pos)) /* Assignment of value for DATA in the DSU_DCC register */ 133 #define DSU_DCC_Msk _UINT32_(0xFFFFFFFF) /* (DSU_DCC) Register Mask */ 134 135 136 /* -------- DSU_DID : (DSU Offset: 0x18) ( R/ 32) Device Identification -------- */ 137 #define DSU_DID_RESETVALUE _UINT32_(0x61870500) /* (DSU_DID) Device Identification Reset Value */ 138 139 #define DSU_DID_DEVSEL_Pos _UINT32_(0) /* (DSU_DID) Device Select Position */ 140 #define DSU_DID_DEVSEL_Msk (_UINT32_(0xFF) << DSU_DID_DEVSEL_Pos) /* (DSU_DID) Device Select Mask */ 141 #define DSU_DID_DEVSEL(value) (DSU_DID_DEVSEL_Msk & (_UINT32_(value) << DSU_DID_DEVSEL_Pos)) /* Assignment of value for DEVSEL in the DSU_DID register */ 142 #define DSU_DID_DEVSEL_1MB_256KB_128PIN_Val _UINT32_(0x0) /* (DSU_DID) 1 MB Flash / 256 KB SRAM / 128-pin */ 143 #define DSU_DID_DEVSEL_1MB_256KB_100PIN_Val _UINT32_(0x1) /* (DSU_DID) 1 MB Flash / 256 KB SRAM / 100-pin */ 144 #define DSU_DID_DEVSEL_1MB_256KB_128PIN (DSU_DID_DEVSEL_1MB_256KB_128PIN_Val << DSU_DID_DEVSEL_Pos) /* (DSU_DID) 1 MB Flash / 256 KB SRAM / 128-pin Position */ 145 #define DSU_DID_DEVSEL_1MB_256KB_100PIN (DSU_DID_DEVSEL_1MB_256KB_100PIN_Val << DSU_DID_DEVSEL_Pos) /* (DSU_DID) 1 MB Flash / 256 KB SRAM / 100-pin Position */ 146 #define DSU_DID_REVISION_Pos _UINT32_(8) /* (DSU_DID) Revision Number Position */ 147 #define DSU_DID_REVISION_Msk (_UINT32_(0xF) << DSU_DID_REVISION_Pos) /* (DSU_DID) Revision Number Mask */ 148 #define DSU_DID_REVISION(value) (DSU_DID_REVISION_Msk & (_UINT32_(value) << DSU_DID_REVISION_Pos)) /* Assignment of value for REVISION in the DSU_DID register */ 149 #define DSU_DID_DIE_Pos _UINT32_(12) /* (DSU_DID) Die Number Position */ 150 #define DSU_DID_DIE_Msk (_UINT32_(0xF) << DSU_DID_DIE_Pos) /* (DSU_DID) Die Number Mask */ 151 #define DSU_DID_DIE(value) (DSU_DID_DIE_Msk & (_UINT32_(value) << DSU_DID_DIE_Pos)) /* Assignment of value for DIE in the DSU_DID register */ 152 #define DSU_DID_SERIES_Pos _UINT32_(16) /* (DSU_DID) Series Position */ 153 #define DSU_DID_SERIES_Msk (_UINT32_(0x3F) << DSU_DID_SERIES_Pos) /* (DSU_DID) Series Mask */ 154 #define DSU_DID_SERIES(value) (DSU_DID_SERIES_Msk & (_UINT32_(value) << DSU_DID_SERIES_Pos)) /* Assignment of value for SERIES in the DSU_DID register */ 155 #define DSU_DID_SERIES_PIC32CX_SG60_Val _UINT32_(0x0) /* (DSU_DID) PIC32CX SG Without Immutable Boot, With HSM */ 156 #define DSU_DID_SERIES_PIC32CX_SG61_Val _UINT32_(0x2) /* (DSU_DID) PIC32CX SG With Immutable Boot and HSM */ 157 #define DSU_DID_SERIES_PIC32CX_SG41_Val _UINT32_(0x7) /* (DSU_DID) PIC32CX SG With Immutable Boot, No HSM */ 158 #define DSU_DID_SERIES_PIC32CX_SG60 (DSU_DID_SERIES_PIC32CX_SG60_Val << DSU_DID_SERIES_Pos) /* (DSU_DID) PIC32CX SG Without Immutable Boot, With HSM Position */ 159 #define DSU_DID_SERIES_PIC32CX_SG61 (DSU_DID_SERIES_PIC32CX_SG61_Val << DSU_DID_SERIES_Pos) /* (DSU_DID) PIC32CX SG With Immutable Boot and HSM Position */ 160 #define DSU_DID_SERIES_PIC32CX_SG41 (DSU_DID_SERIES_PIC32CX_SG41_Val << DSU_DID_SERIES_Pos) /* (DSU_DID) PIC32CX SG With Immutable Boot, No HSM Position */ 161 #define DSU_DID_FAMILY_Pos _UINT32_(23) /* (DSU_DID) Family Position */ 162 #define DSU_DID_FAMILY_Msk (_UINT32_(0x1F) << DSU_DID_FAMILY_Pos) /* (DSU_DID) Family Mask */ 163 #define DSU_DID_FAMILY(value) (DSU_DID_FAMILY_Msk & (_UINT32_(value) << DSU_DID_FAMILY_Pos)) /* Assignment of value for FAMILY in the DSU_DID register */ 164 #define DSU_DID_FAMILY_1_Val _UINT32_(0x3) /* (DSU_DID) PIC32CX Advanced Feature Set Microcontrollers */ 165 #define DSU_DID_FAMILY_1 (DSU_DID_FAMILY_1_Val << DSU_DID_FAMILY_Pos) /* (DSU_DID) PIC32CX Advanced Feature Set Microcontrollers Position */ 166 #define DSU_DID_PROCESSOR_Pos _UINT32_(28) /* (DSU_DID) Processor Position */ 167 #define DSU_DID_PROCESSOR_Msk (_UINT32_(0xF) << DSU_DID_PROCESSOR_Pos) /* (DSU_DID) Processor Mask */ 168 #define DSU_DID_PROCESSOR(value) (DSU_DID_PROCESSOR_Msk & (_UINT32_(value) << DSU_DID_PROCESSOR_Pos)) /* Assignment of value for PROCESSOR in the DSU_DID register */ 169 #define DSU_DID_PROCESSOR_CM4F_Val _UINT32_(0x6) /* (DSU_DID) Cortex-M4 with FPU */ 170 #define DSU_DID_PROCESSOR_CM4F (DSU_DID_PROCESSOR_CM4F_Val << DSU_DID_PROCESSOR_Pos) /* (DSU_DID) Cortex-M4 with FPU Position */ 171 #define DSU_DID_Msk _UINT32_(0xFFBFFFFF) /* (DSU_DID) Register Mask */ 172 173 174 /* -------- DSU_CFG : (DSU Offset: 0x1C) (R/W 32) Configuration -------- */ 175 #define DSU_CFG_RESETVALUE _UINT32_(0x02) /* (DSU_CFG) Configuration Reset Value */ 176 177 #define DSU_CFG_LQOS_Pos _UINT32_(0) /* (DSU_CFG) Latency Quality Of Service Position */ 178 #define DSU_CFG_LQOS_Msk (_UINT32_(0x3) << DSU_CFG_LQOS_Pos) /* (DSU_CFG) Latency Quality Of Service Mask */ 179 #define DSU_CFG_LQOS(value) (DSU_CFG_LQOS_Msk & (_UINT32_(value) << DSU_CFG_LQOS_Pos)) /* Assignment of value for LQOS in the DSU_CFG register */ 180 #define DSU_CFG_DCCDMALEVEL_Pos _UINT32_(2) /* (DSU_CFG) DMA Trigger Level Position */ 181 #define DSU_CFG_DCCDMALEVEL_Msk (_UINT32_(0x3) << DSU_CFG_DCCDMALEVEL_Pos) /* (DSU_CFG) DMA Trigger Level Mask */ 182 #define DSU_CFG_DCCDMALEVEL(value) (DSU_CFG_DCCDMALEVEL_Msk & (_UINT32_(value) << DSU_CFG_DCCDMALEVEL_Pos)) /* Assignment of value for DCCDMALEVEL in the DSU_CFG register */ 183 #define DSU_CFG_DCCDMALEVEL_EMPTY_Val _UINT32_(0x0) /* (DSU_CFG) Trigger rises when DCC is empty */ 184 #define DSU_CFG_DCCDMALEVEL_FULL_Val _UINT32_(0x1) /* (DSU_CFG) Trigger rises when DCC is full */ 185 #define DSU_CFG_DCCDMALEVEL_EMPTY (DSU_CFG_DCCDMALEVEL_EMPTY_Val << DSU_CFG_DCCDMALEVEL_Pos) /* (DSU_CFG) Trigger rises when DCC is empty Position */ 186 #define DSU_CFG_DCCDMALEVEL_FULL (DSU_CFG_DCCDMALEVEL_FULL_Val << DSU_CFG_DCCDMALEVEL_Pos) /* (DSU_CFG) Trigger rises when DCC is full Position */ 187 #define DSU_CFG_ETBRAMEN_Pos _UINT32_(4) /* (DSU_CFG) Trace Control Position */ 188 #define DSU_CFG_ETBRAMEN_Msk (_UINT32_(0x1) << DSU_CFG_ETBRAMEN_Pos) /* (DSU_CFG) Trace Control Mask */ 189 #define DSU_CFG_ETBRAMEN(value) (DSU_CFG_ETBRAMEN_Msk & (_UINT32_(value) << DSU_CFG_ETBRAMEN_Pos)) /* Assignment of value for ETBRAMEN in the DSU_CFG register */ 190 #define DSU_CFG_Msk _UINT32_(0x0000001F) /* (DSU_CFG) Register Mask */ 191 192 193 /* -------- DSU_DCFG : (DSU Offset: 0xF0) (R/W 32) Device Configuration -------- */ 194 #define DSU_DCFG_RESETVALUE _UINT32_(0x00) /* (DSU_DCFG) Device Configuration Reset Value */ 195 196 #define DSU_DCFG_DCFG_Pos _UINT32_(0) /* (DSU_DCFG) Device Configuration Position */ 197 #define DSU_DCFG_DCFG_Msk (_UINT32_(0xFFFFFFFF) << DSU_DCFG_DCFG_Pos) /* (DSU_DCFG) Device Configuration Mask */ 198 #define DSU_DCFG_DCFG(value) (DSU_DCFG_DCFG_Msk & (_UINT32_(value) << DSU_DCFG_DCFG_Pos)) /* Assignment of value for DCFG in the DSU_DCFG register */ 199 #define DSU_DCFG_Msk _UINT32_(0xFFFFFFFF) /* (DSU_DCFG) Register Mask */ 200 201 202 /* -------- DSU_ENTRY0 : (DSU Offset: 0x1000) ( R/ 32) CoreSight ROM Table Entry 0 -------- */ 203 #define DSU_ENTRY0_RESETVALUE _UINT32_(0x9F0FC002) /* (DSU_ENTRY0) CoreSight ROM Table Entry 0 Reset Value */ 204 205 #define DSU_ENTRY0_EPRES_Pos _UINT32_(0) /* (DSU_ENTRY0) Entry Present Position */ 206 #define DSU_ENTRY0_EPRES_Msk (_UINT32_(0x1) << DSU_ENTRY0_EPRES_Pos) /* (DSU_ENTRY0) Entry Present Mask */ 207 #define DSU_ENTRY0_EPRES(value) (DSU_ENTRY0_EPRES_Msk & (_UINT32_(value) << DSU_ENTRY0_EPRES_Pos)) /* Assignment of value for EPRES in the DSU_ENTRY0 register */ 208 #define DSU_ENTRY0_FMT_Pos _UINT32_(1) /* (DSU_ENTRY0) Format Position */ 209 #define DSU_ENTRY0_FMT_Msk (_UINT32_(0x1) << DSU_ENTRY0_FMT_Pos) /* (DSU_ENTRY0) Format Mask */ 210 #define DSU_ENTRY0_FMT(value) (DSU_ENTRY0_FMT_Msk & (_UINT32_(value) << DSU_ENTRY0_FMT_Pos)) /* Assignment of value for FMT in the DSU_ENTRY0 register */ 211 #define DSU_ENTRY0_ADDOFF_Pos _UINT32_(12) /* (DSU_ENTRY0) Address Offset Position */ 212 #define DSU_ENTRY0_ADDOFF_Msk (_UINT32_(0xFFFFF) << DSU_ENTRY0_ADDOFF_Pos) /* (DSU_ENTRY0) Address Offset Mask */ 213 #define DSU_ENTRY0_ADDOFF(value) (DSU_ENTRY0_ADDOFF_Msk & (_UINT32_(value) << DSU_ENTRY0_ADDOFF_Pos)) /* Assignment of value for ADDOFF in the DSU_ENTRY0 register */ 214 #define DSU_ENTRY0_Msk _UINT32_(0xFFFFF003) /* (DSU_ENTRY0) Register Mask */ 215 216 217 /* -------- DSU_ENTRY1 : (DSU Offset: 0x1004) ( R/ 32) CoreSight ROM Table Entry 1 -------- */ 218 #define DSU_ENTRY1_RESETVALUE _UINT32_(0x00) /* (DSU_ENTRY1) CoreSight ROM Table Entry 1 Reset Value */ 219 220 #define DSU_ENTRY1_Msk _UINT32_(0x00000000) /* (DSU_ENTRY1) Register Mask */ 221 222 223 /* -------- DSU_END : (DSU Offset: 0x1008) ( R/ 32) CoreSight ROM Table End -------- */ 224 #define DSU_END_RESETVALUE _UINT32_(0x00) /* (DSU_END) CoreSight ROM Table End Reset Value */ 225 226 #define DSU_END_END_Pos _UINT32_(0) /* (DSU_END) End Marker Position */ 227 #define DSU_END_END_Msk (_UINT32_(0xFFFFFFFF) << DSU_END_END_Pos) /* (DSU_END) End Marker Mask */ 228 #define DSU_END_END(value) (DSU_END_END_Msk & (_UINT32_(value) << DSU_END_END_Pos)) /* Assignment of value for END in the DSU_END register */ 229 #define DSU_END_Msk _UINT32_(0xFFFFFFFF) /* (DSU_END) Register Mask */ 230 231 232 /* -------- DSU_MEMTYPE : (DSU Offset: 0x1FCC) ( R/ 32) CoreSight ROM Table Memory Type -------- */ 233 #define DSU_MEMTYPE_RESETVALUE _UINT32_(0x00) /* (DSU_MEMTYPE) CoreSight ROM Table Memory Type Reset Value */ 234 235 #define DSU_MEMTYPE_SMEMP_Pos _UINT32_(0) /* (DSU_MEMTYPE) System Memory Present Position */ 236 #define DSU_MEMTYPE_SMEMP_Msk (_UINT32_(0x1) << DSU_MEMTYPE_SMEMP_Pos) /* (DSU_MEMTYPE) System Memory Present Mask */ 237 #define DSU_MEMTYPE_SMEMP(value) (DSU_MEMTYPE_SMEMP_Msk & (_UINT32_(value) << DSU_MEMTYPE_SMEMP_Pos)) /* Assignment of value for SMEMP in the DSU_MEMTYPE register */ 238 #define DSU_MEMTYPE_Msk _UINT32_(0x00000001) /* (DSU_MEMTYPE) Register Mask */ 239 240 241 /* -------- DSU_PID4 : (DSU Offset: 0x1FD0) ( R/ 32) Peripheral Identification 4 -------- */ 242 #define DSU_PID4_RESETVALUE _UINT32_(0x00) /* (DSU_PID4) Peripheral Identification 4 Reset Value */ 243 244 #define DSU_PID4_JEPCC_Pos _UINT32_(0) /* (DSU_PID4) JEP-106 Continuation Code Position */ 245 #define DSU_PID4_JEPCC_Msk (_UINT32_(0xF) << DSU_PID4_JEPCC_Pos) /* (DSU_PID4) JEP-106 Continuation Code Mask */ 246 #define DSU_PID4_JEPCC(value) (DSU_PID4_JEPCC_Msk & (_UINT32_(value) << DSU_PID4_JEPCC_Pos)) /* Assignment of value for JEPCC in the DSU_PID4 register */ 247 #define DSU_PID4_FKBC_Pos _UINT32_(4) /* (DSU_PID4) 4KB count Position */ 248 #define DSU_PID4_FKBC_Msk (_UINT32_(0xF) << DSU_PID4_FKBC_Pos) /* (DSU_PID4) 4KB count Mask */ 249 #define DSU_PID4_FKBC(value) (DSU_PID4_FKBC_Msk & (_UINT32_(value) << DSU_PID4_FKBC_Pos)) /* Assignment of value for FKBC in the DSU_PID4 register */ 250 #define DSU_PID4_Msk _UINT32_(0x000000FF) /* (DSU_PID4) Register Mask */ 251 252 253 /* -------- DSU_PID5 : (DSU Offset: 0x1FD4) ( R/ 32) Peripheral Identification 5 -------- */ 254 #define DSU_PID5_RESETVALUE _UINT32_(0x00) /* (DSU_PID5) Peripheral Identification 5 Reset Value */ 255 256 #define DSU_PID5_Msk _UINT32_(0x00000000) /* (DSU_PID5) Register Mask */ 257 258 259 /* -------- DSU_PID6 : (DSU Offset: 0x1FD8) ( R/ 32) Peripheral Identification 6 -------- */ 260 #define DSU_PID6_RESETVALUE _UINT32_(0x00) /* (DSU_PID6) Peripheral Identification 6 Reset Value */ 261 262 #define DSU_PID6_Msk _UINT32_(0x00000000) /* (DSU_PID6) Register Mask */ 263 264 265 /* -------- DSU_PID7 : (DSU Offset: 0x1FDC) ( R/ 32) Peripheral Identification 7 -------- */ 266 #define DSU_PID7_RESETVALUE _UINT32_(0x00) /* (DSU_PID7) Peripheral Identification 7 Reset Value */ 267 268 #define DSU_PID7_Msk _UINT32_(0x00000000) /* (DSU_PID7) Register Mask */ 269 270 271 /* -------- DSU_PID0 : (DSU Offset: 0x1FE0) ( R/ 32) Peripheral Identification 0 -------- */ 272 #define DSU_PID0_RESETVALUE _UINT32_(0xD0) /* (DSU_PID0) Peripheral Identification 0 Reset Value */ 273 274 #define DSU_PID0_PARTNBL_Pos _UINT32_(0) /* (DSU_PID0) Part Number Low Position */ 275 #define DSU_PID0_PARTNBL_Msk (_UINT32_(0xFF) << DSU_PID0_PARTNBL_Pos) /* (DSU_PID0) Part Number Low Mask */ 276 #define DSU_PID0_PARTNBL(value) (DSU_PID0_PARTNBL_Msk & (_UINT32_(value) << DSU_PID0_PARTNBL_Pos)) /* Assignment of value for PARTNBL in the DSU_PID0 register */ 277 #define DSU_PID0_Msk _UINT32_(0x000000FF) /* (DSU_PID0) Register Mask */ 278 279 280 /* -------- DSU_PID1 : (DSU Offset: 0x1FE4) ( R/ 32) Peripheral Identification 1 -------- */ 281 #define DSU_PID1_RESETVALUE _UINT32_(0xFC) /* (DSU_PID1) Peripheral Identification 1 Reset Value */ 282 283 #define DSU_PID1_PARTNBH_Pos _UINT32_(0) /* (DSU_PID1) Part Number High Position */ 284 #define DSU_PID1_PARTNBH_Msk (_UINT32_(0xF) << DSU_PID1_PARTNBH_Pos) /* (DSU_PID1) Part Number High Mask */ 285 #define DSU_PID1_PARTNBH(value) (DSU_PID1_PARTNBH_Msk & (_UINT32_(value) << DSU_PID1_PARTNBH_Pos)) /* Assignment of value for PARTNBH in the DSU_PID1 register */ 286 #define DSU_PID1_JEPIDCL_Pos _UINT32_(4) /* (DSU_PID1) Low part of the JEP-106 Identity Code Position */ 287 #define DSU_PID1_JEPIDCL_Msk (_UINT32_(0xF) << DSU_PID1_JEPIDCL_Pos) /* (DSU_PID1) Low part of the JEP-106 Identity Code Mask */ 288 #define DSU_PID1_JEPIDCL(value) (DSU_PID1_JEPIDCL_Msk & (_UINT32_(value) << DSU_PID1_JEPIDCL_Pos)) /* Assignment of value for JEPIDCL in the DSU_PID1 register */ 289 #define DSU_PID1_Msk _UINT32_(0x000000FF) /* (DSU_PID1) Register Mask */ 290 291 292 /* -------- DSU_PID2 : (DSU Offset: 0x1FE8) ( R/ 32) Peripheral Identification 2 -------- */ 293 #define DSU_PID2_RESETVALUE _UINT32_(0x09) /* (DSU_PID2) Peripheral Identification 2 Reset Value */ 294 295 #define DSU_PID2_JEPIDCH_Pos _UINT32_(0) /* (DSU_PID2) JEP-106 Identity Code High Position */ 296 #define DSU_PID2_JEPIDCH_Msk (_UINT32_(0x7) << DSU_PID2_JEPIDCH_Pos) /* (DSU_PID2) JEP-106 Identity Code High Mask */ 297 #define DSU_PID2_JEPIDCH(value) (DSU_PID2_JEPIDCH_Msk & (_UINT32_(value) << DSU_PID2_JEPIDCH_Pos)) /* Assignment of value for JEPIDCH in the DSU_PID2 register */ 298 #define DSU_PID2_JEPU_Pos _UINT32_(3) /* (DSU_PID2) JEP-106 Identity Code is used Position */ 299 #define DSU_PID2_JEPU_Msk (_UINT32_(0x1) << DSU_PID2_JEPU_Pos) /* (DSU_PID2) JEP-106 Identity Code is used Mask */ 300 #define DSU_PID2_JEPU(value) (DSU_PID2_JEPU_Msk & (_UINT32_(value) << DSU_PID2_JEPU_Pos)) /* Assignment of value for JEPU in the DSU_PID2 register */ 301 #define DSU_PID2_REVISION_Pos _UINT32_(4) /* (DSU_PID2) Revision Number Position */ 302 #define DSU_PID2_REVISION_Msk (_UINT32_(0xF) << DSU_PID2_REVISION_Pos) /* (DSU_PID2) Revision Number Mask */ 303 #define DSU_PID2_REVISION(value) (DSU_PID2_REVISION_Msk & (_UINT32_(value) << DSU_PID2_REVISION_Pos)) /* Assignment of value for REVISION in the DSU_PID2 register */ 304 #define DSU_PID2_Msk _UINT32_(0x000000FF) /* (DSU_PID2) Register Mask */ 305 306 307 /* -------- DSU_PID3 : (DSU Offset: 0x1FEC) ( R/ 32) Peripheral Identification 3 -------- */ 308 #define DSU_PID3_RESETVALUE _UINT32_(0x00) /* (DSU_PID3) Peripheral Identification 3 Reset Value */ 309 310 #define DSU_PID3_CUSMOD_Pos _UINT32_(0) /* (DSU_PID3) ARM CUSMOD Position */ 311 #define DSU_PID3_CUSMOD_Msk (_UINT32_(0xF) << DSU_PID3_CUSMOD_Pos) /* (DSU_PID3) ARM CUSMOD Mask */ 312 #define DSU_PID3_CUSMOD(value) (DSU_PID3_CUSMOD_Msk & (_UINT32_(value) << DSU_PID3_CUSMOD_Pos)) /* Assignment of value for CUSMOD in the DSU_PID3 register */ 313 #define DSU_PID3_REVAND_Pos _UINT32_(4) /* (DSU_PID3) Revision Number Position */ 314 #define DSU_PID3_REVAND_Msk (_UINT32_(0xF) << DSU_PID3_REVAND_Pos) /* (DSU_PID3) Revision Number Mask */ 315 #define DSU_PID3_REVAND(value) (DSU_PID3_REVAND_Msk & (_UINT32_(value) << DSU_PID3_REVAND_Pos)) /* Assignment of value for REVAND in the DSU_PID3 register */ 316 #define DSU_PID3_Msk _UINT32_(0x000000FF) /* (DSU_PID3) Register Mask */ 317 318 319 /* -------- DSU_CID0 : (DSU Offset: 0x1FF0) ( R/ 32) Component Identification 0 -------- */ 320 #define DSU_CID0_RESETVALUE _UINT32_(0x0D) /* (DSU_CID0) Component Identification 0 Reset Value */ 321 322 #define DSU_CID0_PREAMBLEB0_Pos _UINT32_(0) /* (DSU_CID0) Preamble Byte 0 Position */ 323 #define DSU_CID0_PREAMBLEB0_Msk (_UINT32_(0xFF) << DSU_CID0_PREAMBLEB0_Pos) /* (DSU_CID0) Preamble Byte 0 Mask */ 324 #define DSU_CID0_PREAMBLEB0(value) (DSU_CID0_PREAMBLEB0_Msk & (_UINT32_(value) << DSU_CID0_PREAMBLEB0_Pos)) /* Assignment of value for PREAMBLEB0 in the DSU_CID0 register */ 325 #define DSU_CID0_Msk _UINT32_(0x000000FF) /* (DSU_CID0) Register Mask */ 326 327 328 /* -------- DSU_CID1 : (DSU Offset: 0x1FF4) ( R/ 32) Component Identification 1 -------- */ 329 #define DSU_CID1_RESETVALUE _UINT32_(0x10) /* (DSU_CID1) Component Identification 1 Reset Value */ 330 331 #define DSU_CID1_PREAMBLE_Pos _UINT32_(0) /* (DSU_CID1) Preamble Position */ 332 #define DSU_CID1_PREAMBLE_Msk (_UINT32_(0xF) << DSU_CID1_PREAMBLE_Pos) /* (DSU_CID1) Preamble Mask */ 333 #define DSU_CID1_PREAMBLE(value) (DSU_CID1_PREAMBLE_Msk & (_UINT32_(value) << DSU_CID1_PREAMBLE_Pos)) /* Assignment of value for PREAMBLE in the DSU_CID1 register */ 334 #define DSU_CID1_CCLASS_Pos _UINT32_(4) /* (DSU_CID1) Component Class Position */ 335 #define DSU_CID1_CCLASS_Msk (_UINT32_(0xF) << DSU_CID1_CCLASS_Pos) /* (DSU_CID1) Component Class Mask */ 336 #define DSU_CID1_CCLASS(value) (DSU_CID1_CCLASS_Msk & (_UINT32_(value) << DSU_CID1_CCLASS_Pos)) /* Assignment of value for CCLASS in the DSU_CID1 register */ 337 #define DSU_CID1_Msk _UINT32_(0x000000FF) /* (DSU_CID1) Register Mask */ 338 339 340 /* -------- DSU_CID2 : (DSU Offset: 0x1FF8) ( R/ 32) Component Identification 2 -------- */ 341 #define DSU_CID2_RESETVALUE _UINT32_(0x05) /* (DSU_CID2) Component Identification 2 Reset Value */ 342 343 #define DSU_CID2_PREAMBLEB2_Pos _UINT32_(0) /* (DSU_CID2) Preamble Byte 2 Position */ 344 #define DSU_CID2_PREAMBLEB2_Msk (_UINT32_(0xFF) << DSU_CID2_PREAMBLEB2_Pos) /* (DSU_CID2) Preamble Byte 2 Mask */ 345 #define DSU_CID2_PREAMBLEB2(value) (DSU_CID2_PREAMBLEB2_Msk & (_UINT32_(value) << DSU_CID2_PREAMBLEB2_Pos)) /* Assignment of value for PREAMBLEB2 in the DSU_CID2 register */ 346 #define DSU_CID2_Msk _UINT32_(0x000000FF) /* (DSU_CID2) Register Mask */ 347 348 349 /* -------- DSU_CID3 : (DSU Offset: 0x1FFC) ( R/ 32) Component Identification 3 -------- */ 350 #define DSU_CID3_RESETVALUE _UINT32_(0xB1) /* (DSU_CID3) Component Identification 3 Reset Value */ 351 352 #define DSU_CID3_PREAMBLEB3_Pos _UINT32_(0) /* (DSU_CID3) Preamble Byte 3 Position */ 353 #define DSU_CID3_PREAMBLEB3_Msk (_UINT32_(0xFF) << DSU_CID3_PREAMBLEB3_Pos) /* (DSU_CID3) Preamble Byte 3 Mask */ 354 #define DSU_CID3_PREAMBLEB3(value) (DSU_CID3_PREAMBLEB3_Msk & (_UINT32_(value) << DSU_CID3_PREAMBLEB3_Pos)) /* Assignment of value for PREAMBLEB3 in the DSU_CID3 register */ 355 #define DSU_CID3_Msk _UINT32_(0x000000FF) /* (DSU_CID3) Register Mask */ 356 357 358 /* DSU register offsets definitions */ 359 #define DSU_CTRL_REG_OFST _UINT32_(0x00) /* (DSU_CTRL) Control Offset */ 360 #define DSU_STATUSA_REG_OFST _UINT32_(0x01) /* (DSU_STATUSA) Status A Offset */ 361 #define DSU_STATUSB_REG_OFST _UINT32_(0x02) /* (DSU_STATUSB) Status B Offset */ 362 #define DSU_ADDR_REG_OFST _UINT32_(0x04) /* (DSU_ADDR) Address Offset */ 363 #define DSU_LENGTH_REG_OFST _UINT32_(0x08) /* (DSU_LENGTH) Length Offset */ 364 #define DSU_DATA_REG_OFST _UINT32_(0x0C) /* (DSU_DATA) Data Offset */ 365 #define DSU_DCC_REG_OFST _UINT32_(0x10) /* (DSU_DCC) Debug Communication Channel n Offset */ 366 #define DSU_DCC0_REG_OFST _UINT32_(0x10) /* (DSU_DCC0) Debug Communication Channel n Offset */ 367 #define DSU_DCC1_REG_OFST _UINT32_(0x14) /* (DSU_DCC1) Debug Communication Channel n Offset */ 368 #define DSU_DID_REG_OFST _UINT32_(0x18) /* (DSU_DID) Device Identification Offset */ 369 #define DSU_CFG_REG_OFST _UINT32_(0x1C) /* (DSU_CFG) Configuration Offset */ 370 #define DSU_DCFG_REG_OFST _UINT32_(0xF0) /* (DSU_DCFG) Device Configuration Offset */ 371 #define DSU_DCFG0_REG_OFST _UINT32_(0xF0) /* (DSU_DCFG0) Device Configuration Offset */ 372 #define DSU_DCFG1_REG_OFST _UINT32_(0xF4) /* (DSU_DCFG1) Device Configuration Offset */ 373 #define DSU_ENTRY0_REG_OFST _UINT32_(0x1000) /* (DSU_ENTRY0) CoreSight ROM Table Entry 0 Offset */ 374 #define DSU_ENTRY1_REG_OFST _UINT32_(0x1004) /* (DSU_ENTRY1) CoreSight ROM Table Entry 1 Offset */ 375 #define DSU_END_REG_OFST _UINT32_(0x1008) /* (DSU_END) CoreSight ROM Table End Offset */ 376 #define DSU_MEMTYPE_REG_OFST _UINT32_(0x1FCC) /* (DSU_MEMTYPE) CoreSight ROM Table Memory Type Offset */ 377 #define DSU_PID4_REG_OFST _UINT32_(0x1FD0) /* (DSU_PID4) Peripheral Identification 4 Offset */ 378 #define DSU_PID5_REG_OFST _UINT32_(0x1FD4) /* (DSU_PID5) Peripheral Identification 5 Offset */ 379 #define DSU_PID6_REG_OFST _UINT32_(0x1FD8) /* (DSU_PID6) Peripheral Identification 6 Offset */ 380 #define DSU_PID7_REG_OFST _UINT32_(0x1FDC) /* (DSU_PID7) Peripheral Identification 7 Offset */ 381 #define DSU_PID0_REG_OFST _UINT32_(0x1FE0) /* (DSU_PID0) Peripheral Identification 0 Offset */ 382 #define DSU_PID1_REG_OFST _UINT32_(0x1FE4) /* (DSU_PID1) Peripheral Identification 1 Offset */ 383 #define DSU_PID2_REG_OFST _UINT32_(0x1FE8) /* (DSU_PID2) Peripheral Identification 2 Offset */ 384 #define DSU_PID3_REG_OFST _UINT32_(0x1FEC) /* (DSU_PID3) Peripheral Identification 3 Offset */ 385 #define DSU_CID0_REG_OFST _UINT32_(0x1FF0) /* (DSU_CID0) Component Identification 0 Offset */ 386 #define DSU_CID1_REG_OFST _UINT32_(0x1FF4) /* (DSU_CID1) Component Identification 1 Offset */ 387 #define DSU_CID2_REG_OFST _UINT32_(0x1FF8) /* (DSU_CID2) Component Identification 2 Offset */ 388 #define DSU_CID3_REG_OFST _UINT32_(0x1FFC) /* (DSU_CID3) Component Identification 3 Offset */ 389 390 #if !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) 391 /* DSU register API structure */ 392 typedef struct 393 { /* Device Service Unit */ 394 __O uint8_t DSU_CTRL; /* Offset: 0x00 ( /W 8) Control */ 395 __IO uint8_t DSU_STATUSA; /* Offset: 0x01 (R/W 8) Status A */ 396 __I uint8_t DSU_STATUSB; /* Offset: 0x02 (R/ 8) Status B */ 397 __I uint8_t Reserved1[0x01]; 398 __IO uint32_t DSU_ADDR; /* Offset: 0x04 (R/W 32) Address */ 399 __IO uint32_t DSU_LENGTH; /* Offset: 0x08 (R/W 32) Length */ 400 __IO uint32_t DSU_DATA; /* Offset: 0x0C (R/W 32) Data */ 401 __IO uint32_t DSU_DCC[2]; /* Offset: 0x10 (R/W 32) Debug Communication Channel n */ 402 __I uint32_t DSU_DID; /* Offset: 0x18 (R/ 32) Device Identification */ 403 __IO uint32_t DSU_CFG; /* Offset: 0x1C (R/W 32) Configuration */ 404 __I uint8_t Reserved2[0xD0]; 405 __IO uint32_t DSU_DCFG[2]; /* Offset: 0xF0 (R/W 32) Device Configuration */ 406 __I uint8_t Reserved3[0xF08]; 407 __I uint32_t DSU_ENTRY0; /* Offset: 0x1000 (R/ 32) CoreSight ROM Table Entry 0 */ 408 __I uint32_t DSU_ENTRY1; /* Offset: 0x1004 (R/ 32) CoreSight ROM Table Entry 1 */ 409 __I uint32_t DSU_END; /* Offset: 0x1008 (R/ 32) CoreSight ROM Table End */ 410 __I uint8_t Reserved4[0xFC0]; 411 __I uint32_t DSU_MEMTYPE; /* Offset: 0x1FCC (R/ 32) CoreSight ROM Table Memory Type */ 412 __I uint32_t DSU_PID4; /* Offset: 0x1FD0 (R/ 32) Peripheral Identification 4 */ 413 __I uint32_t DSU_PID5; /* Offset: 0x1FD4 (R/ 32) Peripheral Identification 5 */ 414 __I uint32_t DSU_PID6; /* Offset: 0x1FD8 (R/ 32) Peripheral Identification 6 */ 415 __I uint32_t DSU_PID7; /* Offset: 0x1FDC (R/ 32) Peripheral Identification 7 */ 416 __I uint32_t DSU_PID0; /* Offset: 0x1FE0 (R/ 32) Peripheral Identification 0 */ 417 __I uint32_t DSU_PID1; /* Offset: 0x1FE4 (R/ 32) Peripheral Identification 1 */ 418 __I uint32_t DSU_PID2; /* Offset: 0x1FE8 (R/ 32) Peripheral Identification 2 */ 419 __I uint32_t DSU_PID3; /* Offset: 0x1FEC (R/ 32) Peripheral Identification 3 */ 420 __I uint32_t DSU_CID0; /* Offset: 0x1FF0 (R/ 32) Component Identification 0 */ 421 __I uint32_t DSU_CID1; /* Offset: 0x1FF4 (R/ 32) Component Identification 1 */ 422 __I uint32_t DSU_CID2; /* Offset: 0x1FF8 (R/ 32) Component Identification 2 */ 423 __I uint32_t DSU_CID3; /* Offset: 0x1FFC (R/ 32) Component Identification 3 */ 424 } dsu_registers_t; 425 426 427 #endif /* !(defined(__ASSEMBLER__) || defined(__IAR_SYSTEMS_ASM__)) */ 428 #endif /* _PIC32CXSG41_DSU_COMPONENT_H_ */ 429
