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Searched refs:SCB5_CHIP_TOP_SPI_SEL_NR (Results 1 – 11 of 11) sorted by relevance

/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/
Dpsoc6_01_config.h2770 #define SCB5_CHIP_TOP_SPI_SEL_NR 3u macro
Dpsoc6_03_config.h2872 #define SCB5_CHIP_TOP_SPI_SEL_NR 4u macro
Dpsoc6_04_config.h2941 #define SCB5_CHIP_TOP_SPI_SEL_NR 4u macro
Dpsoc6_02_config.h3347 #define SCB5_CHIP_TOP_SPI_SEL_NR 4u macro
Dfx3g2_config.h3616 #define SCB5_CHIP_TOP_SPI_SEL_NR 1u macro
Dtviibe1m_config.h3576 #define SCB5_CHIP_TOP_SPI_SEL_NR 4u macro
Dtviibe2m_config.h3746 #define SCB5_CHIP_TOP_SPI_SEL_NR 4u macro
Dtviibe4m_config.h3751 #define SCB5_CHIP_TOP_SPI_SEL_NR 4u macro
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/
Dxmc7100_config.h4150 #define SCB5_CHIP_TOP_SPI_SEL_NR 4u macro
Dtviic2d6m_config.h4675 #define SCB5_CHIP_TOP_SPI_SEL_NR 2u macro
Dxmc7200_config.h4810 #define SCB5_CHIP_TOP_SPI_SEL_NR 4u macro