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Searched refs:PCLK_TCPWM0_CLOCKS3 (Results 1 – 10 of 10) sorted by relevance

/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1A/include/
Dpsoc6_01_config.h55 PCLK_TCPWM0_CLOCKS3 = 0x0016u, /* tcpwm[0].clocks[3] */ enumerator
Dpsoc6_03_config.h45 PCLK_TCPWM0_CLOCKS3 = 0x000Cu, /* tcpwm[0].clocks[3] */ enumerator
Dpsoc6_04_config.h43 PCLK_TCPWM0_CLOCKS3 = 0x000Au, /* tcpwm[0].clocks[3] */ enumerator
Dpsoc6_02_config.h51 PCLK_TCPWM0_CLOCKS3 = 0x0012u, /* tcpwm[0].clocks[3] */ enumerator
Dfx3g2_config.h43 PCLK_TCPWM0_CLOCKS3 = 0x000Au, /* tcpwm[0].clocks[3] */ enumerator
Dtviibe1m_config.h67 PCLK_TCPWM0_CLOCKS3 = 0x0022u, /* tcpwm[0].clocks[3] */ enumerator
Dtviibe2m_config.h77 PCLK_TCPWM0_CLOCKS3 = 0x002Cu, /* tcpwm[0].clocks[3] */ enumerator
Dtviibe4m_config.h77 PCLK_TCPWM0_CLOCKS3 = 0x002Cu, /* tcpwm[0].clocks[3] */ enumerator
/hal_infineon-latest/mtb-pdl-cat1/devices/COMPONENT_CAT1C/include/
Dxmc7100_config.h80 PCLK_TCPWM0_CLOCKS3 = 0x0129u, /* tcpwm[0].clocks[3] */ enumerator
Dtviic2d6m_config.h38 PCLK_TCPWM0_CLOCKS3 = 0x0005u, /* tcpwm[0].clocks[3] */ enumerator