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/hal_gigadevice-latest/gd32f4xx/standard_peripheral/source/
Dgd32f4xx_enet.c880 uint32_t offset = 0U, size = 0U; in enet_frame_receive() local
909 for(offset = 0U; offset < size; offset++) { in enet_frame_receive()
910 … (*(buffer + offset)) = (*(__IO uint8_t *)(uint32_t)((dma_current_rxdesc->buffer1_addr) + offset)); in enet_frame_receive()
957 uint32_t offset = 0U; in enet_frame_transmit() local
973 for(offset = 0U; offset < length; offset++) { in enet_frame_transmit()
974 … (*(__IO uint8_t *)(uint32_t)((dma_current_txdesc->buffer1_addr) + offset)) = (*(buffer + offset)); in enet_frame_transmit()
1397 uint32_t offset = 0U, max = 0U, limit = 0U; in enet_registers_get() local
1399 offset = (uint32_t)type; in enet_registers_get()
1408 for(; offset < max; offset++) { in enet_registers_get()
1410 *preg = REG32((ENET) + enet_reg_tab[offset]); in enet_registers_get()
[all …]
Dgd32f4xx_misc.c119 void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset) in nvic_vector_table_set() argument
121 SCB->VTOR = nvic_vict_tab | (offset & NVIC_VECTTAB_OFFSET_MASK); in nvic_vector_table_set()
/hal_gigadevice-latest/gd32e50x/standard_peripheral/source/
Dgd32e50x_enet.c878 uint32_t offset = 0U, size = 0U; in enet_frame_receive() local
906 for(offset = 0U; offset<size; offset++){ in enet_frame_receive()
907 …(*(buffer + offset)) = (*(__IO uint8_t *) (uint32_t)((dma_current_rxdesc->buffer1_addr) + offset)); in enet_frame_receive()
954 uint32_t offset = 0U; in enet_frame_transmit() local
970 for(offset = 0U; offset < length; offset++){ in enet_frame_transmit()
971 …(*(__IO uint8_t *) (uint32_t)((dma_current_txdesc->buffer1_addr) + offset)) = (*(buffer + offset)); in enet_frame_transmit()
1405 uint32_t offset = 0U, max = 0U, limit = 0U; in enet_registers_get() local
1407 offset = (uint32_t)type; in enet_registers_get()
1416 for(; offset < max; offset++){ in enet_registers_get()
1418 *preg = REG32((ENET) + enet_reg_tab[offset]); in enet_registers_get()
[all …]
Dgd32e50x_misc.c131 void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset) in nvic_vector_table_set() argument
133 SCB->VTOR = nvic_vict_tab | (offset & NVIC_VECTTAB_OFFSET_MASK); in nvic_vector_table_set()
/hal_gigadevice-latest/gd32vf103/riscv/drivers/
Dn200_timer.h14 #define TIMER_REG(offset) _REG32(TIMER_CTRL_ADDR, offset) argument
/hal_gigadevice-latest/gd32l23x/standard_peripheral/source/
Dgd32l23x_misc.c83 void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset) in nvic_vector_table_set() argument
85 SCB->VTOR = nvic_vict_tab | (offset & NVIC_VECTTAB_OFFSET_MASK); in nvic_vector_table_set()
/hal_gigadevice-latest/gd32vf103/standard_peripheral/include/
Dgd32vf103_fmc.h114 #define FMC_REG_VAL(offset) (REG32(FMC + ((uint32_t)(offset) >> 6))) argument
117 #define FMC_REG_VALS(offset) (REG32(FMC + ((uint32_t)(offset) >> 12))) argument
Dgd32vf103_i2c.h134 #define I2C_REG_VAL(i2cx, offset) (REG32((i2cx) + (((uint32_t)(offset) & 0xFFFFU) >> 6))) argument
138 #define I2C_REG_VAL2(i2cx, offset) (REG32((i2cx) + ((uint32_t)(offset) >> 22))) argument
Dgd32vf103_usart.h125 #define USART_REG_VAL(usartx, offset) (REG32((usartx) + (((uint32_t)(offset) & (0x0000FFFFU)… argument
129 #define USART_REG_VAL2(usartx, offset) (REG32((usartx) + ((uint32_t)(offset) >> 22))) argument
/hal_gigadevice-latest/gd32f3x0/standard_peripheral/source/
Dgd32f3x0_misc.c132 void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset) in nvic_vector_table_set() argument
134 SCB->VTOR = nvic_vict_tab | (offset & NVIC_VECTTAB_OFFSET_MASK); in nvic_vector_table_set()
/hal_gigadevice-latest/gd32e10x/standard_peripheral/source/
Dgd32e10x_misc.c131 void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset) in nvic_vector_table_set() argument
133 SCB->VTOR = nvic_vict_tab | (offset & NVIC_VECTTAB_OFFSET_MASK); in nvic_vector_table_set()
/hal_gigadevice-latest/gd32f403/standard_peripheral/source/
Dgd32f403_misc.c119 void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset) in nvic_vector_table_set() argument
121 SCB->VTOR = nvic_vict_tab | (offset & NVIC_VECTTAB_OFFSET_MASK); in nvic_vector_table_set()
/hal_gigadevice-latest/gd32a50x/standard_peripheral/source/
Dgd32a50x_misc.c128 void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset) in nvic_vector_table_set() argument
130 SCB->VTOR = nvic_vict_tab | (offset & NVIC_VECTTAB_OFFSET_MASK); in nvic_vector_table_set()
/hal_gigadevice-latest/gd32f403/standard_peripheral/include/
Dgd32f403_fmc.h140 #define FMC_REG_VAL(offset) (REG32(FMC + ((uint32_t)(offset) >> 6))) argument
143 #define FMC_REG_VALS(offset) (REG32(FMC + ((uint32_t)(offset) >> 12))) argument
Dgd32f403_i2c.h137 #define I2C_REG_VAL(i2cx, offset) (REG32((i2cx) + (((uint32_t)(offset) & 0xFFFFU) >> 6))) argument
141 #define I2C_REG_VAL2(i2cx, offset) (REG32((i2cx) + ((uint32_t)(offset) >> 22))) argument
Dgd32f403_usart.h147 #define USART_REG_VAL(usartx, offset) (REG32((usartx) + (((uint32_t)(offset) & 0xFFFFU) >> 6)… argument
151 #define USART_REG_VAL2(usartx, offset) (REG32((usartx) + ((uint32_t)(offset) >> 22))) argument
/hal_gigadevice-latest/gd32f3x0/standard_peripheral/include/
Dgd32f3x0_i2c.h136 #define I2C_REG_VAL(i2cx, offset) (REG32((i2cx) + (((uint32_t)(offset) & 0x0000FFFFU) >> 6))) argument
140 #define I2C_REG_VAL2(i2cx, offset) (REG32((i2cx) + ((uint32_t)(offset) >> 22))) argument
/hal_gigadevice-latest/gd32l23x/standard_peripheral/include/
Dgd32l23x_dma.h177 #define DMAMUX_REG_VAL(offset) (REG32(DMAMUX + (((uint32_t)(offset) & 0x0000FFFFU) >> 6)… argument
181 #define DMAMUX_REG_VAL2(offset) (REG32(DMAMUX + ((uint32_t)(offset) >> 22))) argument
183 #define DMAMUX_REG_VAL3(offset) (REG32(DMAMUX + (((uint32_t)(offset) & 0x0000FFFFU) >> 6… argument
Dgd32l23x_lpuart.h151 #define LPUART_REG_VAL(lpuart, offset) (REG32((lpuart) + (((uint32_t)(offset) & 0x0000FFFFU) >… argument
155 #define LPUART_REG_VAL2(lpuart, offset) (REG32((lpuart) + ((uint32_t)(offset) >> 22))) argument
Dgd32l23x_i2c.h166 #define I2C_REG_VAL(i2cx, offset) (REG32((i2cx) + (((uint32_t)(offset) & 0x0000FFFFU) >> 6))) argument
170 #define I2C_REG_VAL2(i2cx, offset) (REG32((i2cx) + ((uint32_t)(offset) >> 22))) argument
Dgd32l23x_misc.h71 void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset);
/hal_gigadevice-latest/gd32e10x/standard_peripheral/include/
Dgd32e10x_i2c.h153 #define I2C_REG_VAL(i2cx, offset) (REG32((i2cx) + (((uint32_t)(offset) & 0x0000FFFFU) >> 6))) argument
157 #define I2C_REG_VAL2(i2cx, offset) (REG32((i2cx) + ((uint32_t)(offset) >> 22))) argument
/hal_gigadevice-latest/gd32f4xx/standard_peripheral/include/
Dgd32f4xx_i2c.h155 #define I2C_REG_VAL(i2cx, offset) (REG32((i2cx) + (((uint32_t)(offset) & 0x0000FFFFU) >> 6))) argument
159 #define I2C_REG_VAL2(i2cx, offset) (REG32((i2cx) + ((uint32_t)(offset) >> 22))) argument
/hal_gigadevice-latest/gd32a50x/standard_peripheral/include/
Dgd32a50x_i2c.h164 #define I2C_REG_VAL(i2cx, offset) (REG32((i2cx) + (((uint32_t)(offset) & 0x0000FFFFU) >> 6))) argument
168 #define I2C_REG_VAL2(i2cx, offset) (REG32((i2cx) + ((uint32_t)(offset) >> 22))) argument
Dgd32a50x_dma.h200 #define DMAMUX_REG_VAL(offset) (REG32(DMAMUX + (((uint32_t)(offset)… argument
201 #define DMAMUX_REG_VAL2(offset) (REG32(DMAMUX + ((uint32_t)(offset) … argument
202 #define DMAMUX_REG_VAL3(offset) (REG32(DMAMUX + (((uint32_t)(offset)… argument

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