1 /*!
2 \file gd32f3x0_misc.c
3 \brief MISC driver
4
5 \version 2017-06-06, V1.0.0, firmware for GD32F3x0
6 \version 2019-06-01, V2.0.0, firmware for GD32F3x0
7 \version 2020-09-30, V2.1.0, firmware for GD32F3x0
8 */
9
10 /*
11 Copyright (c) 2020, GigaDevice Semiconductor Inc.
12
13 Redistribution and use in source and binary forms, with or without modification,
14 are permitted provided that the following conditions are met:
15
16 1. Redistributions of source code must retain the above copyright notice, this
17 list of conditions and the following disclaimer.
18 2. Redistributions in binary form must reproduce the above copyright notice,
19 this list of conditions and the following disclaimer in the documentation
20 and/or other materials provided with the distribution.
21 3. Neither the name of the copyright holder nor the names of its contributors
22 may be used to endorse or promote products derived from this software without
23 specific prior written permission.
24
25 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
26 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
27 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
28 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
29 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
30 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
31 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
32 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
34 OF SUCH DAMAGE.
35 */
36
37 #include "gd32f3x0_misc.h"
38
39 /*!
40 \brief set the priority group
41 \param[in] nvic_prigroup: the NVIC priority group
42 only one parameter can be selected which is shown as below:
43 \arg NVIC_PRIGROUP_PRE0_SUB4:0 bits for pre-emption priority 4 bits for subpriority
44 \arg NVIC_PRIGROUP_PRE1_SUB3:1 bits for pre-emption priority 3 bits for subpriority
45 \arg NVIC_PRIGROUP_PRE2_SUB2:2 bits for pre-emption priority 2 bits for subpriority
46 \arg NVIC_PRIGROUP_PRE3_SUB1:3 bits for pre-emption priority 1 bits for subpriority
47 \arg NVIC_PRIGROUP_PRE4_SUB0:4 bits for pre-emption priority 0 bits for subpriority
48 \param[out] none
49 \retval none
50 */
nvic_priority_group_set(uint32_t nvic_prigroup)51 void nvic_priority_group_set(uint32_t nvic_prigroup)
52 {
53 /* set the priority group value */
54 SCB->AIRCR = NVIC_AIRCR_VECTKEY_MASK | nvic_prigroup;
55 }
56
57 /*!
58 \brief enable NVIC request
59 \param[in] nvic_irq: the NVIC interrupt request, detailed in IRQn_Type
60 \param[in] nvic_irq_pre_priority: the pre-emption priority needed to set
61 \param[in] nvic_irq_sub_priority: the subpriority needed to set
62 \param[out] none
63 \retval none
64 */
nvic_irq_enable(uint8_t nvic_irq,uint8_t nvic_irq_pre_priority,uint8_t nvic_irq_sub_priority)65 void nvic_irq_enable(uint8_t nvic_irq,
66 uint8_t nvic_irq_pre_priority,
67 uint8_t nvic_irq_sub_priority)
68 {
69 uint32_t temp_priority = 0x00U, temp_pre = 0x00U, temp_sub = 0x00U;
70
71 /* use the priority group value to get the temp_pre and the temp_sub */
72 switch ((SCB->AIRCR) & (uint32_t)0x700U) {
73 case NVIC_PRIGROUP_PRE0_SUB4:
74 temp_pre = 0U;
75 temp_sub = 0x4U;
76 break;
77 case NVIC_PRIGROUP_PRE1_SUB3:
78 temp_pre = 1U;
79 temp_sub = 0x3U;
80 break;
81 case NVIC_PRIGROUP_PRE2_SUB2:
82 temp_pre = 2U;
83 temp_sub = 0x2U;
84 break;
85 case NVIC_PRIGROUP_PRE3_SUB1:
86 temp_pre = 3U;
87 temp_sub = 0x1U;
88 break;
89 case NVIC_PRIGROUP_PRE4_SUB0:
90 temp_pre = 4U;
91 temp_sub = 0x0U;
92 break;
93 default:
94 nvic_priority_group_set(NVIC_PRIGROUP_PRE2_SUB2);
95 temp_pre = 2U;
96 temp_sub = 0x2U;
97 break;
98 }
99
100 /* get the temp_priority to fill the NVIC->IP register */
101 temp_priority = (uint32_t)nvic_irq_pre_priority << (0x4U - temp_pre);
102 temp_priority |= nvic_irq_sub_priority &(0x0FU >> (0x4U - temp_sub));
103 temp_priority = temp_priority << 0x04U;
104 NVIC->IP[nvic_irq] = (uint8_t)temp_priority;
105
106 /* enable the selected IRQ */
107 NVIC->ISER[nvic_irq >> 0x05U] = (uint32_t)0x01U << (nvic_irq & (uint8_t)0x1FU);
108 }
109
110 /*!
111 \brief disable NVIC request
112 \param[in] nvic_irq: the NVIC interrupt request, detailed in IRQn_Type
113 \param[out] none
114 \retval none
115 */
nvic_irq_disable(uint8_t nvic_irq)116 void nvic_irq_disable(uint8_t nvic_irq)
117 {
118 /* disable the selected IRQ.*/
119 NVIC->ICER[nvic_irq >> 0x05U] = (uint32_t)0x01U << (nvic_irq & (uint8_t)0x1FU);
120 }
121
122 /*!
123 \brief set the NVIC vector table base address
124 \param[in] nvic_vict_tab: the RAM or FLASH base address
125 only one parameter can be selected which is shown as below:
126 \arg NVIC_VECTTAB_RAM: RAM base address
127 \are NVIC_VECTTAB_FLASH: Flash base address
128 \param[in] offset: Vector Table offset
129 \param[out] none
130 \retval none
131 */
nvic_vector_table_set(uint32_t nvic_vict_tab,uint32_t offset)132 void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset)
133 {
134 SCB->VTOR = nvic_vict_tab | (offset & NVIC_VECTTAB_OFFSET_MASK);
135 }
136
137 /*!
138 \brief set the state of the low power mode
139 \param[in] lowpower_mode: the low power mode state
140 only one parameter can be selected which is shown as below:
141 \arg SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system always enter low power
142 mode by exiting from ISR
143 \arg SCB_LPM_DEEPSLEEP: if chose this para, the system will enter the DEEPSLEEP mode
144 \arg SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the lowpower mode can be woke up
145 by all the enable and disable interrupts
146 \param[out] none
147 \retval none
148 */
system_lowpower_set(uint8_t lowpower_mode)149 void system_lowpower_set(uint8_t lowpower_mode)
150 {
151 SCB->SCR |= (uint32_t)lowpower_mode;
152 }
153
154 /*!
155 \brief reset the state of the low power mode
156 \param[in] lowpower_mode: the low power mode state
157 only one parameter can be selected which is shown as below:
158 \arg SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system will exit low power
159 mode by exiting from ISR
160 \arg SCB_LPM_DEEPSLEEP: if chose this para, the system will enter the SLEEP mode
161 \arg SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the lowpower mode only can be
162 woke up by the enable interrupts
163 \param[out] none
164 \retval none
165 */
system_lowpower_reset(uint8_t lowpower_mode)166 void system_lowpower_reset(uint8_t lowpower_mode)
167 {
168 SCB->SCR &= (~(uint32_t)lowpower_mode);
169 }
170
171 /*!
172 \brief set the systick clock source
173 \param[in] systick_clksource: the systick clock source needed to choose
174 only one parameter can be selected which is shown as below:
175 \arg SYSTICK_CLKSOURCE_HCLK: systick clock source is from HCLK
176 \arg SYSTICK_CLKSOURCE_HCLK_DIV8: systick clock source is from HCLK/8
177 \param[out] none
178 \retval none
179 */
180
systick_clksource_set(uint32_t systick_clksource)181 void systick_clksource_set(uint32_t systick_clksource)
182 {
183 if(SYSTICK_CLKSOURCE_HCLK == systick_clksource ){
184 /* set the systick clock source from HCLK */
185 SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
186 }else{
187 /* set the systick clock source from HCLK/8 */
188 SysTick->CTRL &= SYSTICK_CLKSOURCE_HCLK_DIV8;
189 }
190 }
191
