1 /*! 2 \file gd32vf103_i2c.h 3 \brief definitions for the I2C 4 5 \version 2019-06-05, V1.0.0, firmware for GD32VF103 6 \version 2020-08-04, V1.1.0, firmware for GD32VF103 7 */ 8 9 /* 10 Copyright (c) 2020, GigaDevice Semiconductor Inc. 11 12 Redistribution and use in source and binary forms, with or without modification, 13 are permitted provided that the following conditions are met: 14 15 1. Redistributions of source code must retain the above copyright notice, this 16 list of conditions and the following disclaimer. 17 2. Redistributions in binary form must reproduce the above copyright notice, 18 this list of conditions and the following disclaimer in the documentation 19 and/or other materials provided with the distribution. 20 3. Neither the name of the copyright holder nor the names of its contributors 21 may be used to endorse or promote products derived from this software without 22 specific prior written permission. 23 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 26 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 28 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 29 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 30 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 31 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 32 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 33 OF SUCH DAMAGE. 34 */ 35 36 #ifndef GD32VF103_I2C_H 37 #define GD32VF103_I2C_H 38 39 #include "gd32vf103.h" 40 41 /* I2Cx(x=0,1) definitions */ 42 #define I2C0 I2C_BASE /*!< I2C0 base address */ 43 #define I2C1 (I2C_BASE + 0x00000400U) /*!< I2C1 base address */ 44 45 /* registers definitions */ 46 #define I2C_CTL0(i2cx) REG32((i2cx) + 0x00U) /*!< I2C control register 0 */ 47 #define I2C_CTL1(i2cx) REG32((i2cx) + 0x04U) /*!< I2C control register 1 */ 48 #define I2C_SADDR0(i2cx) REG32((i2cx) + 0x08U) /*!< I2C slave address register 0*/ 49 #define I2C_SADDR1(i2cx) REG32((i2cx) + 0x0CU) /*!< I2C slave address register */ 50 #define I2C_DATA(i2cx) REG32((i2cx) + 0x10U) /*!< I2C transfer buffer register */ 51 #define I2C_STAT0(i2cx) REG32((i2cx) + 0x14U) /*!< I2C transfer status register 0 */ 52 #define I2C_STAT1(i2cx) REG32((i2cx) + 0x18U) /*!< I2C transfer status register */ 53 #define I2C_CKCFG(i2cx) REG32((i2cx) + 0x1CU) /*!< I2C clock configure register */ 54 #define I2C_RT(i2cx) REG32((i2cx) + 0x20U) /*!< I2C rise time register */ 55 #define I2C_FMPCFG(i2cx) REG32((i2cx) + 0x90U) /*!< I2C fast-mode-plus configure register */ 56 /* bits definitions */ 57 /* I2Cx_CTL0 */ 58 #define I2C_CTL0_I2CEN BIT(0) /*!< peripheral enable */ 59 #define I2C_CTL0_SMBEN BIT(1) /*!< SMBus mode */ 60 #define I2C_CTL0_SMBSEL BIT(3) /*!< SMBus type */ 61 #define I2C_CTL0_ARPEN BIT(4) /*!< ARP enable */ 62 #define I2C_CTL0_PECEN BIT(5) /*!< PEC enable */ 63 #define I2C_CTL0_GCEN BIT(6) /*!< general call enable */ 64 #define I2C_CTL0_SS BIT(7) /*!< clock stretching disable (slave mode) */ 65 #define I2C_CTL0_START BIT(8) /*!< start generation */ 66 #define I2C_CTL0_STOP BIT(9) /*!< stop generation */ 67 #define I2C_CTL0_ACKEN BIT(10) /*!< acknowledge enable */ 68 #define I2C_CTL0_POAP BIT(11) /*!< acknowledge/PEC position (for data reception) */ 69 #define I2C_CTL0_PECTRANS BIT(12) /*!< packet error checking */ 70 #define I2C_CTL0_SALT BIT(13) /*!< SMBus alert */ 71 #define I2C_CTL0_SRESET BIT(15) /*!< software reset */ 72 73 /* I2Cx_CTL1 */ 74 #define I2C_CTL1_I2CCLK BITS(0,5) /*!< I2CCLK[5:0] bits (peripheral clock frequency) */ 75 #define I2C_CTL1_ERRIE BIT(8) /*!< error interrupt enable */ 76 #define I2C_CTL1_EVIE BIT(9) /*!< event interrupt enable */ 77 #define I2C_CTL1_BUFIE BIT(10) /*!< buffer interrupt enable */ 78 #define I2C_CTL1_DMAON BIT(11) /*!< DMA requests enable */ 79 #define I2C_CTL1_DMALST BIT(12) /*!< DMA last transfer */ 80 81 /* I2Cx_SADDR0 */ 82 #define I2C_SADDR0_ADDRESS0 BIT(0) /*!< bit 0 of a 10-bit address */ 83 #define I2C_SADDR0_ADDRESS BITS(1,7) /*!< 7-bit address or bits 7:1 of a 10-bit address */ 84 #define I2C_SADDR0_ADDRESS_H BITS(8,9) /*!< highest two bits of a 10-bit address */ 85 #define I2C_SADDR0_ADDFORMAT BIT(15) /*!< address mode for the I2C slave */ 86 87 /* I2Cx_SADDR1 */ 88 #define I2C_SADDR1_DUADEN BIT(0) /*!< aual-address mode switch */ 89 #define I2C_SADDR1_ADDRESS2 BITS(1,7) /*!< second I2C address for the slave in dual-address mode */ 90 91 /* I2Cx_DATA */ 92 #define I2C_DATA_TRB BITS(0,7) /*!< 8-bit data register */ 93 94 /* I2Cx_STAT0 */ 95 #define I2C_STAT0_SBSEND BIT(0) /*!< start bit (master mode) */ 96 #define I2C_STAT0_ADDSEND BIT(1) /*!< address sent (master mode)/matched (slave mode) */ 97 #define I2C_STAT0_BTC BIT(2) /*!< byte transfer finished */ 98 #define I2C_STAT0_ADD10SEND BIT(3) /*!< 10-bit header sent (master mode) */ 99 #define I2C_STAT0_STPDET BIT(4) /*!< stop detection (slave mode) */ 100 #define I2C_STAT0_RBNE BIT(6) /*!< data register not empty (receivers) */ 101 #define I2C_STAT0_TBE BIT(7) /*!< data register empty (transmitters) */ 102 #define I2C_STAT0_BERR BIT(8) /*!< bus error */ 103 #define I2C_STAT0_LOSTARB BIT(9) /*!< arbitration lost (master mode) */ 104 #define I2C_STAT0_AERR BIT(10) /*!< acknowledge failure */ 105 #define I2C_STAT0_OUERR BIT(11) /*!< overrun/underrun */ 106 #define I2C_STAT0_PECERR BIT(12) /*!< PEC error in reception */ 107 #define I2C_STAT0_SMBTO BIT(14) /*!< timeout signal in SMBus mode */ 108 #define I2C_STAT0_SMBALT BIT(15) /*!< SMBus alert status */ 109 110 /* I2Cx_STAT1 */ 111 #define I2C_STAT1_MASTER BIT(0) /*!< master/slave */ 112 #define I2C_STAT1_I2CBSY BIT(1) /*!< bus busy */ 113 #define I2C_STAT1_TR BIT(2) /*!< transmitter/receiver */ 114 #define I2C_STAT1_RXGC BIT(4) /*!< general call address (slave mode) */ 115 #define I2C_STAT1_DEFSMB BIT(5) /*!< SMBus device default address (slave mode) */ 116 #define I2C_STAT1_HSTSMB BIT(6) /*!< SMBus host header (slave mode) */ 117 #define I2C_STAT1_DUMODF BIT(7) /*!< dual flag (slave mode) */ 118 #define I2C_STAT1_PECV BITS(8,15) /*!< packet error checking value */ 119 120 /* I2Cx_CKCFG */ 121 #define I2C_CKCFG_CLKC BITS(0,11) /*!< clock control register in fast/standard mode (master mode) */ 122 #define I2C_CKCFG_DTCY BIT(14) /*!< fast mode duty cycle */ 123 #define I2C_CKCFG_FAST BIT(15) /*!< I2C speed selection in master mode */ 124 125 /* I2Cx_RT */ 126 #define I2C_RT_RISETIME BITS(0,5) /*!< maximum rise time in fast/standard mode (Master mode) */ 127 128 /* I2Cx_FMPCFG */ 129 #define I2C_FMPCFG_FMPEN BIT(0) /*!< fast mode plus enable bit */ 130 131 /* constants definitions */ 132 /* define the I2C bit position and its register index offset */ 133 #define I2C_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) 134 #define I2C_REG_VAL(i2cx, offset) (REG32((i2cx) + (((uint32_t)(offset) & 0xFFFFU) >> 6))) 135 #define I2C_BIT_POS(val) ((uint32_t)(val) & 0x1FU) 136 #define I2C_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16)\ 137 | (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))) 138 #define I2C_REG_VAL2(i2cx, offset) (REG32((i2cx) + ((uint32_t)(offset) >> 22))) 139 #define I2C_BIT_POS2(val) (((uint32_t)(val) & 0x1F0000U) >> 16) 140 141 /* register offset */ 142 #define I2C_CTL1_REG_OFFSET 0x04U /*!< CTL1 register offset */ 143 #define I2C_STAT0_REG_OFFSET 0x14U /*!< STAT0 register offset */ 144 #define I2C_STAT1_REG_OFFSET 0x18U /*!< STAT1 register offset */ 145 146 /* I2C flags */ 147 typedef enum { 148 /* flags in STAT0 register */ 149 I2C_FLAG_SBSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 0U), /*!< start condition sent out in master mode */ 150 I2C_FLAG_ADDSEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 1U), /*!< address is sent in master mode or received and matches in slave mode */ 151 I2C_FLAG_BTC = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes */ 152 I2C_FLAG_ADD10SEND = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 3U), /*!< header of 10-bit address is sent in master mode */ 153 I2C_FLAG_STPDET = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 4U), /*!< stop condition detected in slave mode */ 154 I2C_FLAG_RBNE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 6U), /*!< I2C_DATA is not Empty during receiving */ 155 I2C_FLAG_TBE = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting */ 156 I2C_FLAG_BERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 8U), /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus */ 157 I2C_FLAG_LOSTARB = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 9U), /*!< arbitration lost in master mode */ 158 I2C_FLAG_AERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 10U), /*!< acknowledge error */ 159 I2C_FLAG_OUERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 11U), /*!< over-run or under-run situation occurs in slave mode */ 160 I2C_FLAG_PECERR = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 12U), /*!< PEC error when receiving data */ 161 I2C_FLAG_SMBTO = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 14U), /*!< timeout signal in SMBus mode */ 162 I2C_FLAG_SMBALT = I2C_REGIDX_BIT(I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus alert status */ 163 /* flags in STAT1 register */ 164 I2C_FLAG_MASTER = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 0U), /*!< a flag indicating whether I2C block is in master or slave mode */ 165 I2C_FLAG_I2CBSY = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 1U), /*!< busy flag */ 166 I2C_FLAG_TR = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 2U), /*!< whether the I2C is a transmitter or a receiver */ 167 I2C_FLAG_RXGC = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 4U), /*!< general call address (00h) received */ 168 I2C_FLAG_DEFSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 5U), /*!< default address of SMBus device */ 169 I2C_FLAG_HSTSMB = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 6U), /*!< SMBus host header detected in slave mode */ 170 I2C_FLAG_DUMODF = I2C_REGIDX_BIT(I2C_STAT1_REG_OFFSET, 7U), /*!< dual flag in slave mode indicating which address is matched in dual-address mode */ 171 } i2c_flag_enum; 172 173 /* I2C interrupt flags */ 174 typedef enum { 175 /* interrupt flags in CTL1 register */ 176 I2C_INT_FLAG_SBSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U,I2C_STAT0_REG_OFFSET, 0U), /*!< start condition sent out in master mode interrupt flag */ 177 I2C_INT_FLAG_ADDSEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U,I2C_STAT0_REG_OFFSET, 1U), /*!< address is sent in master mode or received and matches in slave mode interrupt flag */ 178 I2C_INT_FLAG_BTC = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U,I2C_STAT0_REG_OFFSET, 2U), /*!< byte transmission finishes */ 179 I2C_INT_FLAG_ADD10SEND = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U,I2C_STAT0_REG_OFFSET, 3U), /*!< header of 10-bit address is sent in master mode interrupt flag */ 180 I2C_INT_FLAG_STPDET = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U,I2C_STAT0_REG_OFFSET, 4U), /*!< stop condition detected in slave mode interrupt flag */ 181 I2C_INT_FLAG_RBNE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U,I2C_STAT0_REG_OFFSET, 6U), /*!< I2C_DATA is not Empty during receiving interrupt flag */ 182 I2C_INT_FLAG_TBE = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 9U,I2C_STAT0_REG_OFFSET, 7U), /*!< I2C_DATA is empty during transmitting interrupt flag */ 183 I2C_INT_FLAG_BERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U,I2C_STAT0_REG_OFFSET, 8U), /*!< a bus error occurs indication a unexpected start or stop condition on I2C bus interrupt flag */ 184 I2C_INT_FLAG_LOSTARB = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U,I2C_STAT0_REG_OFFSET, 9U), /*!< arbitration lost in master mode interrupt flag */ 185 I2C_INT_FLAG_AERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U,I2C_STAT0_REG_OFFSET, 10U), /*!< acknowledge error interrupt flag */ 186 I2C_INT_FLAG_OUERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U,I2C_STAT0_REG_OFFSET, 11U), /*!< over-run or under-run situation occurs in slave mode interrupt flag */ 187 I2C_INT_FLAG_PECERR = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U,I2C_STAT0_REG_OFFSET, 12U), /*!< PEC error when receiving data interrupt flag */ 188 I2C_INT_FLAG_SMBTO = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U,I2C_STAT0_REG_OFFSET, 14U), /*!< timeout signal in SMBus mode interrupt flag */ 189 I2C_INT_FLAG_SMBALT = I2C_REGIDX_BIT2(I2C_CTL1_REG_OFFSET, 8U,I2C_STAT0_REG_OFFSET, 15U), /*!< SMBus Alert status interrupt flag */ 190 } i2c_interrupt_flag_enum; 191 192 /* I2C interrupt enable or disable */ 193 typedef enum { 194 /* interrupt in CTL1 register */ 195 I2C_INT_ERR = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 8U), /*!< error interrupt enable */ 196 I2C_INT_EV = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 9U), /*!< event interrupt enable */ 197 I2C_INT_BUF = I2C_REGIDX_BIT(I2C_CTL1_REG_OFFSET, 10U), /*!< buffer interrupt enable */ 198 } i2c_interrupt_enum; 199 200 /* SMBus/I2C mode switch and SMBus type selection */ 201 #define I2C_I2CMODE_ENABLE ((uint32_t)0x00000000U) /*!< I2C mode */ 202 #define I2C_SMBUSMODE_ENABLE I2C_CTL0_SMBEN /*!< SMBus mode */ 203 204 /* SMBus/I2C mode switch and SMBus type selection */ 205 #define I2C_SMBUS_DEVICE ((uint32_t)0x00000000U) /*!< SMBus mode device type */ 206 #define I2C_SMBUS_HOST I2C_CTL0_SMBSEL /*!< SMBus mode host type */ 207 208 /* I2C transfer direction */ 209 #define I2C_RECEIVER ((uint32_t)0x00000001U) /*!< receiver */ 210 #define I2C_TRANSMITTER ((uint32_t)0xFFFFFFFEU) /*!< transmitter */ 211 212 /* whether or not to send an ACK */ 213 #define I2C_ACK_DISABLE ((uint32_t)0x00000000U) /*!< ACK will be not sent */ 214 #define I2C_ACK_ENABLE ((uint32_t)0x00000001U) /*!< ACK will be sent */ 215 216 /* I2C POAP position*/ 217 #define I2C_ACKPOS_NEXT ((uint32_t)0x00000000U) /*!< ACKEN bit decides whether or not to send ACK for the next byte */ 218 #define I2C_ACKPOS_CURRENT ((uint32_t)0x00000001U) /*!< ACKEN bit decides whether or not to send ACK or not for the current byte */ 219 220 /* I2C dual-address mode switch */ 221 #define I2C_DUADEN_DISABLE ((uint32_t)0x00000000U) /*!< dual-address mode disabled */ 222 #define I2C_DUADEN_ENABLE ((uint32_t)0x00000001U) /*!< dual-address mode enabled */ 223 224 /* whether or not to stretch SCL low */ 225 #define I2C_SCLSTRETCH_ENABLE ((uint32_t)0x00000000U) /*!< SCL stretching is enabled */ 226 #define I2C_SCLSTRETCH_DISABLE I2C_CTL0_SS /*!< SCL stretching is disabled */ 227 228 /* whether or not to response to a general call */ 229 #define I2C_GCEN_ENABLE I2C_CTL0_GCEN /*!< slave will response to a general call */ 230 #define I2C_GCEN_DISABLE ((uint32_t)0x00000000U) /*!< slave will not response to a general call */ 231 232 /* software reset I2C */ 233 #define I2C_SRESET_SET I2C_CTL0_SRESET /*!< I2C is under reset */ 234 #define I2C_SRESET_RESET ((uint32_t)0x00000000U) /*!< I2C is not under reset */ 235 236 /* I2C DMA mode configure */ 237 /* DMA mode switch */ 238 #define I2C_DMA_ON I2C_CTL1_DMAON /*!< DMA mode enabled */ 239 #define I2C_DMA_OFF ((uint32_t)0x00000000U) /*!< DMA mode disabled */ 240 241 /* flag indicating DMA last transfer */ 242 #define I2C_DMALST_ON I2C_CTL1_DMALST /*!< next DMA EOT is the last transfer */ 243 #define I2C_DMALST_OFF ((uint32_t)0x00000000U) /*!< next DMA EOT is not the last transfer */ 244 245 /* I2C PEC configure */ 246 /* PEC enable */ 247 #define I2C_PEC_ENABLE I2C_CTL0_PECEN /*!< PEC calculation on */ 248 #define I2C_PEC_DISABLE ((uint32_t)0x00000000U) /*!< PEC calculation off */ 249 250 /* PEC transfer */ 251 #define I2C_PECTRANS_ENABLE I2C_CTL0_PECTRANS /*!< transfer PEC */ 252 #define I2C_PECTRANS_DISABLE ((uint32_t)0x00000000U) /*!< not transfer PEC value */ 253 254 /* I2C SMBus configure */ 255 /* issue or not alert through SMBA pin */ 256 #define I2C_SALTSEND_ENABLE I2C_CTL0_SALT /*!< issue alert through SMBA pin */ 257 #define I2C_SALTSEND_DISABLE ((uint32_t)0x00000000U) /*!< not issue alert through SMBA */ 258 259 /* ARP protocol in SMBus switch */ 260 #define I2C_ARP_ENABLE I2C_CTL0_ARPEN /*!< ARP enable */ 261 #define I2C_ARP_DISABLE ((uint32_t)0x00000000U) /*!< ARP disable */ 262 263 /* transmit I2C data */ 264 #define DATA_TRANS(regval) (BITS(0,7) & ((uint32_t)(regval) << 0)) 265 266 /* receive I2C data */ 267 #define DATA_RECV(regval) GET_BITS((uint32_t)(regval), 0, 7) 268 269 /* I2C duty cycle in fast mode */ 270 #define I2C_DTCY_2 ((uint32_t)0x00000000U) /*!< I2C fast mode Tlow/Thigh = 2 */ 271 #define I2C_DTCY_16_9 I2C_CKCFG_DTCY /*!< I2C fast mode Tlow/Thigh = 16/9 */ 272 273 /* address mode for the I2C slave */ 274 #define I2C_ADDFORMAT_7BITS ((uint32_t)0x00000000U) /*!< address:7 bits */ 275 #define I2C_ADDFORMAT_10BITS I2C_SADDR0_ADDFORMAT /*!< address:10 bits */ 276 277 /* I2C clock frequency, MHz */ 278 #define I2CCLK_MAX ((uint32_t)0x00000036U) /*!< i2cclk maximum value */ 279 #define I2CCLK_MIN ((uint32_t)0x00000002U) /*!< i2cclk minimum value for standard mode */ 280 #define I2CCLK_FM_MIN ((uint32_t)0x00000008U) /*!< i2cclk minimum value for fast mode */ 281 #define I2CCLK_FM_PLUS_MIN ((uint32_t)0x00000018U) /*!< i2cclk minimum value for fast mode plus */ 282 283 /* function declarations */ 284 /* reset I2C */ 285 void i2c_deinit(uint32_t i2c_periph); 286 /* configure I2C clock */ 287 void i2c_clock_config(uint32_t i2c_periph, uint32_t clkspeed, uint32_t dutycyc); 288 /* configure I2C address */ 289 void i2c_mode_addr_config(uint32_t i2c_periph, uint32_t mode,uint32_t addformat, uint32_t addr); 290 /* SMBus type selection */ 291 void i2c_smbus_type_config(uint32_t i2c_periph, uint32_t type); 292 /* whether or not to send an ACK */ 293 void i2c_ack_config(uint32_t i2c_periph, uint32_t ack); 294 /* configure I2C POAP position */ 295 void i2c_ackpos_config(uint32_t i2c_periph, uint32_t pos); 296 /* master sends slave address */ 297 void i2c_master_addressing(uint32_t i2c_periph, uint32_t addr,uint32_t trandirection); 298 /* enable dual-address mode */ 299 void i2c_dualaddr_enable(uint32_t i2c_periph, uint32_t dualaddr); 300 /* disable dual-address mode */ 301 void i2c_dualaddr_disable(uint32_t i2c_periph); 302 /* enable I2C */ 303 void i2c_enable(uint32_t i2c_periph); 304 /* disable I2C */ 305 void i2c_disable(uint32_t i2c_periph); 306 307 /* generate a START condition on I2C bus */ 308 void i2c_start_on_bus(uint32_t i2c_periph); 309 /* generate a STOP condition on I2C bus */ 310 void i2c_stop_on_bus(uint32_t i2c_periph); 311 /* I2C transmit data function */ 312 void i2c_data_transmit(uint32_t i2c_periph, uint8_t data); 313 /* I2C receive data function */ 314 uint8_t i2c_data_receive(uint32_t i2c_periph); 315 /* enable I2C DMA mode */ 316 void i2c_dma_enable(uint32_t i2c_periph, uint32_t dmastate); 317 /* configure whether next DMA EOT is DMA last transfer or not */ 318 void i2c_dma_last_transfer_config(uint32_t i2c_periph, uint32_t dmalast); 319 /* whether to stretch SCL low when data is not ready in slave mode */ 320 void i2c_stretch_scl_low_config(uint32_t i2c_periph, uint32_t stretchpara); 321 /* whether or not to response to a general call */ 322 void i2c_slave_response_to_gcall_config(uint32_t i2c_periph, uint32_t gcallpara); 323 /* software reset I2C */ 324 void i2c_software_reset_config(uint32_t i2c_periph, uint32_t sreset); 325 326 /* I2C PEC calculation on or off */ 327 void i2c_pec_enable(uint32_t i2c_periph, uint32_t pecstate); 328 /* I2C whether to transfer PEC value */ 329 void i2c_pec_transfer_enable(uint32_t i2c_periph, uint32_t pecpara); 330 /* packet error checking value */ 331 uint8_t i2c_pec_value_get(uint32_t i2c_periph); 332 /* I2C issue alert through SMBA pin */ 333 void i2c_smbus_issue_alert(uint32_t i2c_periph, uint32_t smbuspara); 334 /* I2C ARP protocol in SMBus switch */ 335 void i2c_smbus_arp_enable(uint32_t i2c_periph, uint32_t arpstate); 336 337 /* check I2C flag is set or not */ 338 FlagStatus i2c_flag_get(uint32_t i2c_periph, i2c_flag_enum flag); 339 /* clear I2C flag */ 340 void i2c_flag_clear(uint32_t i2c_periph, i2c_flag_enum flag); 341 /* enable I2C interrupt */ 342 void i2c_interrupt_enable(uint32_t i2c_periph, i2c_interrupt_enum interrupt); 343 /* disable I2C interrupt */ 344 void i2c_interrupt_disable(uint32_t i2c_periph, i2c_interrupt_enum interrupt); 345 /* check I2C interrupt flag */ 346 FlagStatus i2c_interrupt_flag_get(uint32_t i2c_periph,i2c_interrupt_flag_enum int_flag); 347 /* clear I2C interrupt flag */ 348 void i2c_interrupt_flag_clear(uint32_t i2c_periph,i2c_interrupt_flag_enum int_flag); 349 350 #endif /* GD32VF103_I2C_H */ 351
