1 /*!
2 \file gd32a50x_misc.c
3 \brief MISC driver
4
5 \version 2022-01-30, V1.0.0, firmware for GD32A50x
6 */
7
8 /*
9 Copyright (c) 2022, GigaDevice Semiconductor Inc.
10
11 Redistribution and use in source and binary forms, with or without modification,
12 are permitted provided that the following conditions are met:
13
14 1. Redistributions of source code must retain the above copyright notice, this
15 list of conditions and the following disclaimer.
16 2. Redistributions in binary form must reproduce the above copyright notice,
17 this list of conditions and the following disclaimer in the documentation
18 and/or other materials provided with the distribution.
19 3. Neither the name of the copyright holder nor the names of its contributors
20 may be used to endorse or promote products derived from this software without
21 specific prior written permission.
22
23 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
27 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
29 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
32 OF SUCH DAMAGE.
33 */
34
35 #include "gd32a50x_misc.h"
36
37 /*!
38 \brief set the priority group
39 \param[in] nvic_prigroup: the NVIC priority group
40 \arg NVIC_PRIGROUP_PRE0_SUB4:0 bits for pre-emption priority 4 bits for subpriority
41 \arg NVIC_PRIGROUP_PRE1_SUB3:1 bits for pre-emption priority 3 bits for subpriority
42 \arg NVIC_PRIGROUP_PRE2_SUB2:2 bits for pre-emption priority 2 bits for subpriority
43 \arg NVIC_PRIGROUP_PRE3_SUB1:3 bits for pre-emption priority 1 bits for subpriority
44 \arg NVIC_PRIGROUP_PRE4_SUB0:4 bits for pre-emption priority 0 bits for subpriority
45 \param[out] none
46 \retval none
47 */
nvic_priority_group_set(uint32_t nvic_prigroup)48 void nvic_priority_group_set(uint32_t nvic_prigroup)
49 {
50 /* set the priority group value */
51 SCB->AIRCR = NVIC_AIRCR_VECTKEY_MASK | nvic_prigroup;
52 }
53
54 /*!
55 \brief enable NVIC request
56 \param[in] nvic_irq: the NVIC interrupt request, detailed in IRQn_Type
57 \param[in] nvic_irq_pre_priority: the pre-emption priority needed to set
58 \param[in] nvic_irq_sub_priority: the subpriority needed to set
59 \param[out] none
60 \retval none
61 */
nvic_irq_enable(uint8_t nvic_irq,uint8_t nvic_irq_pre_priority,uint8_t nvic_irq_sub_priority)62 void nvic_irq_enable(uint8_t nvic_irq, uint8_t nvic_irq_pre_priority,
63 uint8_t nvic_irq_sub_priority)
64 {
65 uint32_t temp_priority = 0x00U, temp_pre = 0x00U, temp_sub = 0x00U;
66 /* use the priority group value to get the temp_pre and the temp_sub */
67 if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE0_SUB4){
68 temp_pre=0U;
69 temp_sub=0x4U;
70 }else if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE1_SUB3){
71 temp_pre=1U;
72 temp_sub=0x3U;
73 }else if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE2_SUB2){
74 temp_pre=2U;
75 temp_sub=0x2U;
76 }else if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE3_SUB1){
77 temp_pre=3U;
78 temp_sub=0x1U;
79 }else if(((SCB->AIRCR) & (uint32_t)0x700U)==NVIC_PRIGROUP_PRE4_SUB0){
80 temp_pre=4U;
81 temp_sub=0x0U;
82 }else{
83 nvic_priority_group_set(NVIC_PRIGROUP_PRE2_SUB2);
84 temp_pre=2U;
85 temp_sub=0x2U;
86 }
87 /* get the temp_priority to fill the NVIC->IP register */
88 temp_priority = (uint32_t)nvic_irq_pre_priority << (0x4U - temp_pre);
89 temp_priority |= (uint32_t)nvic_irq_sub_priority &((uint32_t)0x0FU >> (0x4U - temp_sub));
90 temp_priority = temp_priority << 0x04U;
91 NVIC->IPR[nvic_irq] = (uint8_t)temp_priority;
92 /* enable the selected IRQ */
93 NVIC->ISER[nvic_irq >> 0x05U] = (uint32_t)0x01U << (nvic_irq & (uint8_t)0x1FU);
94 }
95
96 /*!
97 \brief disable NVIC request
98 \param[in] nvic_irq: the NVIC interrupt request, detailed in IRQn_Type
99 \param[out] none
100 \retval none
101 */
nvic_irq_disable(IRQn_Type nvic_irq)102 void nvic_irq_disable(IRQn_Type nvic_irq)
103 {
104 /* disable the selected IRQ.*/
105 NVIC_DisableIRQ(nvic_irq);
106 }
107
108 /*!
109 \brief initiates a system reset request to reset the MCU
110 \param[in] none
111 \param[out] none
112 \retval none
113 */
nvic_system_reset(void)114 void nvic_system_reset(void)
115 {
116 NVIC_SystemReset();
117 }
118
119 /*!
120 \brief set the NVIC vector table base address
121 \param[in] nvic_vict_tab: the RAM or FLASH base address
122 \arg NVIC_VECTTAB_RAM: RAM base address
123 \are NVIC_VECTTAB_FLASH: Flash base address
124 \param[in] offset: Vector Table offset
125 \param[out] none
126 \retval none
127 */
nvic_vector_table_set(uint32_t nvic_vict_tab,uint32_t offset)128 void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset)
129 {
130 SCB->VTOR = nvic_vict_tab | (offset & NVIC_VECTTAB_OFFSET_MASK);
131 __DSB();
132 }
133
134 /*!
135 \brief set the state of the low power mode
136 \param[in] lowpower_mode: the low power mode state
137 \arg SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system always enter low power
138 mode by exiting from ISR
139 \arg SCB_LPM_DEEPSLEEP: if chose this para, the system will enter the DEEPSLEEP mode
140 \arg SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the lowpower mode can be woke up
141 by all the enable and disable interrupts
142 \param[out] none
143 \retval none
144 */
system_lowpower_set(uint8_t lowpower_mode)145 void system_lowpower_set(uint8_t lowpower_mode)
146 {
147 SCB->SCR |= (uint32_t)lowpower_mode;
148 }
149
150 /*!
151 \brief reset the state of the low power mode
152 \param[in] lowpower_mode: the low power mode state
153 \arg SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system will exit low power
154 mode by exiting from ISR
155 \arg SCB_LPM_DEEPSLEEP: if chose this para, the system will enter the SLEEP mode
156 \arg SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the lowpower mode only can be
157 woke up by the enable interrupts
158 \param[out] none
159 \retval none
160 */
system_lowpower_reset(uint8_t lowpower_mode)161 void system_lowpower_reset(uint8_t lowpower_mode)
162 {
163 SCB->SCR &= (~(uint32_t)lowpower_mode);
164 }
165
166 /*!
167 \brief set the systick clock source
168 \param[in] systick_clksource: the systick clock source needed to choose
169 \arg SYSTICK_CLKSOURCE_HCLK: systick clock source is from HCLK
170 \arg SYSTICK_CLKSOURCE_HCLK_DIV8: systick clock source is from HCLK/8
171 \param[out] none
172 \retval none
173 */
systick_clksource_set(uint32_t systick_clksource)174 void systick_clksource_set(uint32_t systick_clksource)
175 {
176 if(SYSTICK_CLKSOURCE_HCLK == systick_clksource ){
177 /* set the systick clock source from HCLK */
178 SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
179 }else{
180 /* set the systick clock source from HCLK/8 */
181 SysTick->CTRL &= SYSTICK_CLKSOURCE_HCLK_DIV8;
182 }
183 }
184
