1 /*!
2 \file gd32f4xx_misc.c
3 \brief MISC driver
4 \version 2016-08-15, V1.0.0, firmware for GD32F4xx
5 \version 2018-12-12, V2.0.0, firmware for GD32F4xx
6 \version 2020-09-30, V2.1.0, firmware for GD32F4xx
7 \version 2022-03-09, V3.0.0, firmware for GD32F4xx
8 */
9
10 /*
11 Copyright (c) 2022, GigaDevice Semiconductor Inc.
12
13 Redistribution and use in source and binary forms, with or without modification,
14 are permitted provided that the following conditions are met:
15
16 1. Redistributions of source code must retain the above copyright notice, this
17 list of conditions and the following disclaimer.
18 2. Redistributions in binary form must reproduce the above copyright notice,
19 this list of conditions and the following disclaimer in the documentation
20 and/or other materials provided with the distribution.
21 3. Neither the name of the copyright holder nor the names of its contributors
22 may be used to endorse or promote products derived from this software without
23 specific prior written permission.
24
25 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
26 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
27 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
28 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
29 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
30 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
31 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
32 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
34 OF SUCH DAMAGE.
35 */
36
37 #include "gd32f4xx_misc.h"
38
39 /*!
40 \brief set the priority group
41 \param[in] nvic_prigroup: the NVIC priority group
42 \arg NVIC_PRIGROUP_PRE0_SUB4:0 bits for pre-emption priority 4 bits for subpriority
43 \arg NVIC_PRIGROUP_PRE1_SUB3:1 bits for pre-emption priority 3 bits for subpriority
44 \arg NVIC_PRIGROUP_PRE2_SUB2:2 bits for pre-emption priority 2 bits for subpriority
45 \arg NVIC_PRIGROUP_PRE3_SUB1:3 bits for pre-emption priority 1 bits for subpriority
46 \arg NVIC_PRIGROUP_PRE4_SUB0:4 bits for pre-emption priority 0 bits for subpriority
47 \param[out] none
48 \retval none
49 */
nvic_priority_group_set(uint32_t nvic_prigroup)50 void nvic_priority_group_set(uint32_t nvic_prigroup)
51 {
52 /* set the priority group value */
53 SCB->AIRCR = NVIC_AIRCR_VECTKEY_MASK | nvic_prigroup;
54 }
55
56 /*!
57 \brief enable NVIC request
58 \param[in] nvic_irq: the NVIC interrupt request, detailed in IRQn_Type
59 \param[in] nvic_irq_pre_priority: the pre-emption priority needed to set
60 \param[in] nvic_irq_sub_priority: the subpriority needed to set
61 \param[out] none
62 \retval none
63 */
nvic_irq_enable(uint8_t nvic_irq,uint8_t nvic_irq_pre_priority,uint8_t nvic_irq_sub_priority)64 void nvic_irq_enable(uint8_t nvic_irq, uint8_t nvic_irq_pre_priority,
65 uint8_t nvic_irq_sub_priority)
66 {
67 uint32_t temp_priority = 0x00U, temp_pre = 0x00U, temp_sub = 0x00U;
68 /* use the priority group value to get the temp_pre and the temp_sub */
69 if(((SCB->AIRCR) & (uint32_t)0x700U) == NVIC_PRIGROUP_PRE0_SUB4) {
70 temp_pre = 0U;
71 temp_sub = 0x4U;
72 } else if(((SCB->AIRCR) & (uint32_t)0x700U) == NVIC_PRIGROUP_PRE1_SUB3) {
73 temp_pre = 1U;
74 temp_sub = 0x3U;
75 } else if(((SCB->AIRCR) & (uint32_t)0x700U) == NVIC_PRIGROUP_PRE2_SUB2) {
76 temp_pre = 2U;
77 temp_sub = 0x2U;
78 } else if(((SCB->AIRCR) & (uint32_t)0x700U) == NVIC_PRIGROUP_PRE3_SUB1) {
79 temp_pre = 3U;
80 temp_sub = 0x1U;
81 } else if(((SCB->AIRCR) & (uint32_t)0x700U) == NVIC_PRIGROUP_PRE4_SUB0) {
82 temp_pre = 4U;
83 temp_sub = 0x0U;
84 } else {
85 nvic_priority_group_set(NVIC_PRIGROUP_PRE2_SUB2);
86 temp_pre = 2U;
87 temp_sub = 0x2U;
88 }
89 /* get the temp_priority to fill the NVIC->IP register */
90 temp_priority = (uint32_t)nvic_irq_pre_priority << (0x4U - temp_pre);
91 temp_priority |= nvic_irq_sub_priority & (0x0FU >> (0x4U - temp_sub));
92 temp_priority = temp_priority << 0x04U;
93 NVIC->IP[nvic_irq] = (uint8_t)temp_priority;
94 /* enable the selected IRQ */
95 NVIC->ISER[nvic_irq >> 0x05U] = (uint32_t)0x01U << (nvic_irq & (uint8_t)0x1FU);
96 }
97
98 /*!
99 \brief disable NVIC request
100 \param[in] nvic_irq: the NVIC interrupt request, detailed in IRQn_Type
101 \param[out] none
102 \retval none
103 */
nvic_irq_disable(uint8_t nvic_irq)104 void nvic_irq_disable(uint8_t nvic_irq)
105 {
106 /* disable the selected IRQ.*/
107 NVIC->ICER[nvic_irq >> 0x05] = (uint32_t)0x01 << (nvic_irq & (uint8_t)0x1F);
108 }
109
110 /*!
111 \brief set the NVIC vector table base address
112 \param[in] nvic_vict_tab: the RAM or FLASH base address
113 \arg NVIC_VECTTAB_RAM: RAM base address
114 \are NVIC_VECTTAB_FLASH: Flash base address
115 \param[in] offset: Vector Table offset
116 \param[out] none
117 \retval none
118 */
nvic_vector_table_set(uint32_t nvic_vict_tab,uint32_t offset)119 void nvic_vector_table_set(uint32_t nvic_vict_tab, uint32_t offset)
120 {
121 SCB->VTOR = nvic_vict_tab | (offset & NVIC_VECTTAB_OFFSET_MASK);
122 __DSB();
123 }
124
125 /*!
126 \brief set the state of the low power mode
127 \param[in] lowpower_mode: the low power mode state
128 \arg SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system always enter low power
129 mode by exiting from ISR
130 \arg SCB_LPM_DEEPSLEEP: if chose this para, the system will enter the DEEPSLEEP mode
131 \arg SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the lowpower mode can be woke up
132 by all the enable and disable interrupts
133 \param[out] none
134 \retval none
135 */
system_lowpower_set(uint8_t lowpower_mode)136 void system_lowpower_set(uint8_t lowpower_mode)
137 {
138 SCB->SCR |= (uint32_t)lowpower_mode;
139 }
140
141 /*!
142 \brief reset the state of the low power mode
143 \param[in] lowpower_mode: the low power mode state
144 \arg SCB_LPM_SLEEP_EXIT_ISR: if chose this para, the system will exit low power
145 mode by exiting from ISR
146 \arg SCB_LPM_DEEPSLEEP: if chose this para, the system will enter the SLEEP mode
147 \arg SCB_LPM_WAKE_BY_ALL_INT: if chose this para, the lowpower mode only can be
148 woke up by the enable interrupts
149 \param[out] none
150 \retval none
151 */
system_lowpower_reset(uint8_t lowpower_mode)152 void system_lowpower_reset(uint8_t lowpower_mode)
153 {
154 SCB->SCR &= (~(uint32_t)lowpower_mode);
155 }
156
157 /*!
158 \brief set the systick clock source
159 \param[in] systick_clksource: the systick clock source needed to choose
160 \arg SYSTICK_CLKSOURCE_HCLK: systick clock source is from HCLK
161 \arg SYSTICK_CLKSOURCE_HCLK_DIV8: systick clock source is from HCLK/8
162 \param[out] none
163 \retval none
164 */
165
systick_clksource_set(uint32_t systick_clksource)166 void systick_clksource_set(uint32_t systick_clksource)
167 {
168 if(SYSTICK_CLKSOURCE_HCLK == systick_clksource) {
169 /* set the systick clock source from HCLK */
170 SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
171 } else {
172 /* set the systick clock source from HCLK/8 */
173 SysTick->CTRL &= SYSTICK_CLKSOURCE_HCLK_DIV8;
174 }
175 }
176
