1 /*! 2 \file gd32l23x_dma.h 3 \brief definitions for the DMA 4 5 \version 2021-08-04, V1.0.0, firmware for GD32L23x 6 */ 7 8 /* 9 Copyright (c) 2021, GigaDevice Semiconductor Inc. 10 11 Redistribution and use in source and binary forms, with or without modification, 12 are permitted provided that the following conditions are met: 13 14 1. Redistributions of source code must retain the above copyright notice, this 15 list of conditions and the following disclaimer. 16 2. Redistributions in binary form must reproduce the above copyright notice, 17 this list of conditions and the following disclaimer in the documentation 18 and/or other materials provided with the distribution. 19 3. Neither the name of the copyright holder nor the names of its contributors 20 may be used to endorse or promote products derived from this software without 21 specific prior written permission. 22 23 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 24 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 25 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 27 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 29 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 32 OF SUCH DAMAGE. 33 */ 34 35 #ifndef GD32L23X_DMA_H 36 #define GD32L23X_DMA_H 37 38 #include "gd32l23x.h" 39 40 /* DMA definitions */ 41 #define DMA DMA_BASE /*!< DMA base address */ 42 #define DMAMUX DMAMUX_BASE /*!< DMAMUX base address */ 43 44 /* registers definitions */ 45 #define DMA_INTF REG32(DMA + 0x00000000U) /*!< DMA interrupt flag register */ 46 #define DMA_INTC REG32(DMA + 0x00000004U) /*!< DMA interrupt flag clear register */ 47 #define DMA_CH0CTL REG32(DMA + 0x00000008U) /*!< DMA channel 0 control register */ 48 #define DMA_CH0CNT REG32(DMA + 0x0000000CU) /*!< DMA channel 0 counter register */ 49 #define DMA_CH0PADDR REG32(DMA + 0x00000010U) /*!< DMA channel 0 peripheral base address register */ 50 #define DMA_CH0MADDR REG32(DMA + 0x00000014U) /*!< DMA channel 0 memory base address register */ 51 #define DMA_CH1CTL REG32(DMA + 0x0000001CU) /*!< DMA channel 1 control register */ 52 #define DMA_CH1CNT REG32(DMA + 0x00000020U) /*!< DMA channel 1 counter register */ 53 #define DMA_CH1PADDR REG32(DMA + 0x00000024U) /*!< DMA channel 1 peripheral base address register */ 54 #define DMA_CH1MADDR REG32(DMA + 0x00000028U) /*!< DMA channel 1 memory base address register */ 55 #define DMA_CH2CTL REG32(DMA + 0x00000030U) /*!< DMA channel 2 control register */ 56 #define DMA_CH2CNT REG32(DMA + 0x00000034U) /*!< DMA channel 2 counter register */ 57 #define DMA_CH2PADDR REG32(DMA + 0x00000038U) /*!< DMA channel 2 peripheral base address register */ 58 #define DMA_CH2MADDR REG32(DMA + 0x0000003CU) /*!< DMA channel 2 memory base address register */ 59 #define DMA_CH3CTL REG32(DMA + 0x00000044U) /*!< DMA channel 3 control register */ 60 #define DMA_CH3CNT REG32(DMA + 0x00000048U) /*!< DMA channel 3 counter register */ 61 #define DMA_CH3PADDR REG32(DMA + 0x0000004CU) /*!< DMA channel 3 peripheral base address register */ 62 #define DMA_CH3MADDR REG32(DMA + 0x00000050U) /*!< DMA channel 3 memory base address register */ 63 #define DMA_CH4CTL REG32(DMA + 0x00000058U) /*!< DMA channel 4 control register */ 64 #define DMA_CH4CNT REG32(DMA + 0x0000005CU) /*!< DMA channel 4 counter register */ 65 #define DMA_CH4PADDR REG32(DMA + 0x00000060U) /*!< DMA channel 4 peripheral base address register */ 66 #define DMA_CH4MADDR REG32(DMA + 0x00000064U) /*!< DMA channel 4 memory base address register */ 67 #define DMA_CH5CTL REG32(DMA + 0x0000006CU) /*!< DMA channel 5 control register */ 68 #define DMA_CH5CNT REG32(DMA + 0x00000070U) /*!< DMA channel 5 counter register */ 69 #define DMA_CH5PADDR REG32(DMA + 0x00000074U) /*!< DMA channel 5 peripheral base address register */ 70 #define DMA_CH5MADDR REG32(DMA + 0x00000078U) /*!< DMA channel 5 memory base address register */ 71 #define DMA_CH6CTL REG32(DMA + 0x00000080U) /*!< DMA channel 6 control register */ 72 #define DMA_CH6CNT REG32(DMA + 0x00000084U) /*!< DMA channel 6 counter register */ 73 #define DMA_CH6PADDR REG32(DMA + 0x00000088U) /*!< DMA channel 6 peripheral base address register */ 74 #define DMA_CH6MADDR REG32(DMA + 0x0000008CU) /*!< DMA channel 6 memory base address register */ 75 76 #define DMAMUX_RM_CH0CFG REG32(DMAMUX + 0x00000000U) /*!< DMAMUX request multiplexer channel 0 configuration register */ 77 #define DMAMUX_RM_CH1CFG REG32(DMAMUX + 0x00000004U) /*!< DMAMUX request multiplexer channel 1 configuration register */ 78 #define DMAMUX_RM_CH2CFG REG32(DMAMUX + 0x00000008U) /*!< DMAMUX request multiplexer channel 2 configuration register */ 79 #define DMAMUX_RM_CH3CFG REG32(DMAMUX + 0x0000000CU) /*!< DMAMUX request multiplexer channel 3 configuration register */ 80 #define DMAMUX_RM_CH4CFG REG32(DMAMUX + 0x00000010U) /*!< DMAMUX request multiplexer channel 4 configuration register */ 81 #define DMAMUX_RM_CH5CFG REG32(DMAMUX + 0x00000014U) /*!< DMAMUX request multiplexer channel 5 configuration register */ 82 #define DMAMUX_RM_CH6CFG REG32(DMAMUX + 0x00000018U) /*!< DMAMUX request multiplexer channel 6 configuration register */ 83 #define DMAMUX_RM_INTF REG32(DMAMUX + 0x00000080U) /*!< DMAMUX request multiplexer channel interrupt flag register */ 84 #define DMAMUX_RM_INTC REG32(DMAMUX + 0x00000084U) /*!< DMAMUX request multiplexer channel interrupt flag clear register */ 85 #define DMAMUX_RG_CH0CFG REG32(DMAMUX + 0x00000100U) /*!< DMAMUX generator channel 0 configuration register */ 86 #define DMAMUX_RG_CH1CFG REG32(DMAMUX + 0x00000104U) /*!< DMAMUX generator channel 1 configuration register */ 87 #define DMAMUX_RG_CH2CFG REG32(DMAMUX + 0x00000108U) /*!< DMAMUX generator channel 2 configuration register */ 88 #define DMAMUX_RG_CH3CFG REG32(DMAMUX + 0x0000010CU) /*!< DMAMUX generator channel 3 configuration register */ 89 #define DMAMUX_RG_INTF REG32(DMAMUX + 0x00000140U) /*!< DMAMUX generator channel interrupt flag register */ 90 #define DMAMUX_RG_INTC REG32(DMAMUX + 0x00000144U) /*!< DMAMUX rgenerator channel interrupt flag clear register */ 91 92 /* bits definitions */ 93 /* DMA_INTF */ 94 #define DMA_INTF_GIF BIT(0) /*!< global interrupt flag of channel */ 95 #define DMA_INTF_FTFIF BIT(1) /*!< full transfer finish flag of channel */ 96 #define DMA_INTF_HTFIF BIT(2) /*!< half transfer finish flag of channel */ 97 #define DMA_INTF_ERRIF BIT(3) /*!< error flag of channel */ 98 99 /* DMA_INTC */ 100 #define DMA_INTC_GIFC BIT(0) /*!< clear global interrupt flag of channel */ 101 #define DMA_INTC_FTFIFC BIT(1) /*!< clear transfer finish flag of channel */ 102 #define DMA_INTC_HTFIFC BIT(2) /*!< clear half transfer finish flag of channel */ 103 #define DMA_INTC_ERRIFC BIT(3) /*!< clear error flag of channel */ 104 105 /* DMA_CHxCTL, x=0..6 */ 106 #define DMA_CHXCTL_CHEN BIT(0) /*!< channel x enable */ 107 #define DMA_CHXCTL_FTFIE BIT(1) /*!< enable bit for channel x transfer complete interrupt */ 108 #define DMA_CHXCTL_HTFIE BIT(2) /*!< enable bit for channel x transfer half complete interrupt */ 109 #define DMA_CHXCTL_ERRIE BIT(3) /*!< enable bit for channel x error interrupt */ 110 #define DMA_CHXCTL_DIR BIT(4) /*!< direction of the data transfer on the channel */ 111 #define DMA_CHXCTL_CMEN BIT(5) /*!< circulation mode */ 112 #define DMA_CHXCTL_PNAGA BIT(6) /*!< next address generation algorithm of peripheral */ 113 #define DMA_CHXCTL_MNAGA BIT(7) /*!< next address generation algorithm of memory */ 114 #define DMA_CHXCTL_PWIDTH BITS(8,9) /*!< transfer data size of peripheral */ 115 #define DMA_CHXCTL_MWIDTH BITS(10,11) /*!< transfer data size of memory */ 116 #define DMA_CHXCTL_PRIO BITS(12,13) /*!< priority level of channelx */ 117 #define DMA_CHXCTL_M2M BIT(14) /*!< memory to memory mode */ 118 119 /* DMA_CHxCNT, x=0..6 */ 120 #define DMA_CHXCNT_CNT BITS(0,15) /*!< transfer counter */ 121 122 /* DMA_CHxPADDR, x=0..6 */ 123 #define DMA_CHXPADDR_PADDR BITS(0,31) /*!< peripheral base address */ 124 125 /* DMA_CHxMADDR, x=0..6 */ 126 #define DMA_CHXMADDR_MADDR BITS(0,31) /*!< memory base address */ 127 128 /* DMAMUX_RM_CHxCFG, x=0..6 */ 129 #define DMAMUX_RM_CHXCFG_MUXID BITS(0,5) /*!< multiplexer input identification */ 130 #define DMAMUX_RM_CHXCFG_SOIE BIT(8) /*!< synchronization overrun interrupt enable */ 131 #define DMAMUX_RM_CHXCFG_EVGEN BIT(9) /*!< event generation enable */ 132 #define DMAMUX_RM_CHXCFG_SYNCEN BIT(16) /*!< synchronization enable */ 133 #define DMAMUX_RM_CHXCFG_SYNCP BITS(17,18) /*!< synchronization input polarity */ 134 #define DMAMUX_RM_CHXCFG_NBR BITS(19,23) /*!< number of DMA requests to forward */ 135 #define DMAMUX_RM_CHXCFG_SYNCID BITS(24,28) /*!< synchronization input identification */ 136 137 /* DMAMUX_RM_INTF */ 138 #define DMAMUX_RM_INTF_SOIF0 BIT(0) /*!< synchronization overrun event flag of request multiplexer channel 0 */ 139 #define DMAMUX_RM_INTF_SOIF1 BIT(1) /*!< synchronization overrun event flag of request multiplexer channel 1 */ 140 #define DMAMUX_RM_INTF_SOIF2 BIT(2) /*!< synchronization overrun event flag of request multiplexer channel 2 */ 141 #define DMAMUX_RM_INTF_SOIF3 BIT(3) /*!< synchronization overrun event flag of request multiplexer channel 3 */ 142 #define DMAMUX_RM_INTF_SOIF4 BIT(4) /*!< synchronization overrun event flag of request multiplexer channel 4 */ 143 #define DMAMUX_RM_INTF_SOIF5 BIT(5) /*!< synchronization overrun event flag of request multiplexer channel 5 */ 144 #define DMAMUX_RM_INTF_SOIF6 BIT(6) /*!< synchronization overrun event flag of request multiplexer channel 6 */ 145 146 /* DMAMUX_RM_INTC */ 147 #define DMAMUX_RM_INTF_SOIFC0 BIT(0) /*!< clear bit for synchronization overrun event flag of request multiplexer channel 0 */ 148 #define DMAMUX_RM_INTF_SOIFC1 BIT(1) /*!< clear bit for synchronization overrun event flag of request multiplexer channel 1 */ 149 #define DMAMUX_RM_INTF_SOIFC2 BIT(2) /*!< clear bit for synchronization overrun event flag of request multiplexer channel 2 */ 150 #define DMAMUX_RM_INTF_SOIFC3 BIT(3) /*!< clear bit for synchronization overrun event flag of request multiplexer channel 3 */ 151 #define DMAMUX_RM_INTF_SOIFC4 BIT(4) /*!< clear bit for synchronization overrun event flag of request multiplexer channel 4 */ 152 #define DMAMUX_RM_INTF_SOIFC5 BIT(5) /*!< clear bit for synchronization overrun event flag of request multiplexer channel 5 */ 153 #define DMAMUX_RM_INTF_SOIFC6 BIT(6) /*!< clear bit for synchronization overrun event flag of request multiplexer channel 6 */ 154 155 /* DMAMUX_RG_CHxCFG, x=0..3 */ 156 #define DMAMUX_RG_CHXCFG_TID BITS(0,4) /*!< trigger input identification */ 157 #define DMAMUX_RG_CHXCFG_TOIE BIT(8) /*!< trigger overrun interrupt enable */ 158 #define DMAMUX_RG_CHXCFG_RGEN BIT(16) /*!< DMA request generator channel x enable */ 159 #define DMAMUX_RG_CHXCFG_RGTP BITS(17,18) /*!< DMA request generator trigger polarity */ 160 #define DMAMUX_RG_CHXCFG_NBRG BITS(19,23) /*!< number of DMA requests to be generated */ 161 162 /* DMAMUX_RG_INTF */ 163 #define DMAMUX_RG_INTF_TOIF0 BIT(0) /*!< trigger overrun event flag of request generator channel 0 */ 164 #define DMAMUX_RG_INTF_TOIF1 BIT(1) /*!< trigger overrun event flag of request generator channel 1 */ 165 #define DMAMUX_RG_INTF_TOIF2 BIT(2) /*!< trigger overrun event flag of request generator channel 2 */ 166 #define DMAMUX_RG_INTF_TOIF3 BIT(3) /*!< trigger overrun event flag of request generator channel 3 */ 167 168 /* DMAMUX_RG_INTC */ 169 #define DMAMUX_RG_INTF_TOIFC0 BIT(0) /*!< clear bit for trigger overrun event flag of request generator channel 0 */ 170 #define DMAMUX_RG_INTF_TOIFC1 BIT(1) /*!< clear bit for trigger overrun event flag of request generator channel 1 */ 171 #define DMAMUX_RG_INTF_TOIFC2 BIT(2) /*!< clear bit for trigger overrun event flag of request generator channel 2 */ 172 #define DMAMUX_RG_INTF_TOIFC3 BIT(3) /*!< clear bit for trigger overrun event flag of request generator channel 3 */ 173 174 /* constants definitions */ 175 /* define the DMAMUX bit position and its register index offset */ 176 #define DMAMUX_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos)) 177 #define DMAMUX_REG_VAL(offset) (REG32(DMAMUX + (((uint32_t)(offset) & 0x0000FFFFU) >> 6))) 178 #define DMAMUX_BIT_POS(val) ((uint32_t)(val) & 0x1FU) 179 #define DMAMUX_REGIDX_BIT2(regidx, bitpos, regidx2, bitpos2) (((uint32_t)(regidx2) << 22) | (uint32_t)((bitpos2) << 16) \ 180 | (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))) 181 #define DMAMUX_REG_VAL2(offset) (REG32(DMAMUX + ((uint32_t)(offset) >> 22))) 182 #define DMAMUX_BIT_POS2(val) (((uint32_t)(val) & 0x001F0000U) >> 16) 183 #define DMAMUX_REG_VAL3(offset) (REG32(DMAMUX + (((uint32_t)(offset) & 0x0000FFFFU) >> 6) + 0x4U)) 184 185 /* register offset */ 186 #define DMAMUX_RM_CH0CFG_REG_OFFSET 0x00000000U /*!< DMAMUX_RM_CH0CFG register offset */ 187 #define DMAMUX_RM_CH1CFG_REG_OFFSET 0x00000004U /*!< DMAMUX_RM_CH1CFG register offset */ 188 #define DMAMUX_RM_CH2CFG_REG_OFFSET 0x00000008U /*!< DMAMUX_RM_CH2CFG register offset */ 189 #define DMAMUX_RM_CH3CFG_REG_OFFSET 0x0000000CU /*!< DMAMUX_RM_CH3CFG register offset */ 190 #define DMAMUX_RM_CH4CFG_REG_OFFSET 0x00000010U /*!< DMAMUX_RM_CH4CFG register offset */ 191 #define DMAMUX_RM_CH5CFG_REG_OFFSET 0x00000014U /*!< DMAMUX_RM_CH5CFG register offset */ 192 #define DMAMUX_RM_CH6CFG_REG_OFFSET 0x00000018U /*!< DMAMUX_RM_CH6CFG register offset */ 193 #define DMAMUX_RG_CH0CFG_REG_OFFSET 0x00000100U /*!< DMAMUX_RG_CH0CFG register offset */ 194 #define DMAMUX_RG_CH1CFG_REG_OFFSET 0x00000104U /*!< DMAMUX_RG_CH1CFG register offset */ 195 #define DMAMUX_RG_CH2CFG_REG_OFFSET 0x00000108U /*!< DMAMUX_RG_CH2CFG register offset */ 196 #define DMAMUX_RG_CH3CFG_REG_OFFSET 0x0000010CU /*!< DMAMUX_RG_CH3CFG register offset */ 197 #define DMAMUX_RM_INTF_REG_OFFSET 0x00000080U /*!< DMAMUX_RM_INTF register offset */ 198 #define DMAMUX_RG_INTF_REG_OFFSET 0x00000140U /*!< DMAMUX_RG_INTF register offset */ 199 200 /* DMAMUX interrupt enable or disable */ 201 typedef enum { 202 /* interrupts in CHxCFG register */ 203 DMAMUX_INT_MUXCH0_SO = DMAMUX_REGIDX_BIT(DMAMUX_RM_CH0CFG_REG_OFFSET, 8U), /*!< DMAMUX request multiplexer channel 0 synchronization overrun interrupt */ 204 DMAMUX_INT_MUXCH1_SO = DMAMUX_REGIDX_BIT(DMAMUX_RM_CH1CFG_REG_OFFSET, 8U), /*!< DMAMUX request multiplexer channel 1 synchronization overrun interrupt */ 205 DMAMUX_INT_MUXCH2_SO = DMAMUX_REGIDX_BIT(DMAMUX_RM_CH2CFG_REG_OFFSET, 8U), /*!< DMAMUX request multiplexer channel 2 synchronization overrun interrupt */ 206 DMAMUX_INT_MUXCH3_SO = DMAMUX_REGIDX_BIT(DMAMUX_RM_CH3CFG_REG_OFFSET, 8U), /*!< DMAMUX request multiplexer channel 3 synchronization overrun interrupt */ 207 DMAMUX_INT_MUXCH4_SO = DMAMUX_REGIDX_BIT(DMAMUX_RM_CH4CFG_REG_OFFSET, 8U), /*!< DMAMUX request multiplexer channel 4 synchronization overrun interrupt */ 208 DMAMUX_INT_MUXCH5_SO = DMAMUX_REGIDX_BIT(DMAMUX_RM_CH5CFG_REG_OFFSET, 8U), /*!< DMAMUX request multiplexer channel 5 synchronization overrun interrupt */ 209 DMAMUX_INT_MUXCH6_SO = DMAMUX_REGIDX_BIT(DMAMUX_RM_CH6CFG_REG_OFFSET, 8U), /*!< DMAMUX request multiplexer channel 6 synchronization overrun interrupt */ 210 DMAMUX_INT_GENCH0_TO = DMAMUX_REGIDX_BIT(DMAMUX_RG_CH0CFG_REG_OFFSET, 8U), /*!< DMAMUX request generator channel 0 trigger overrun interrupt */ 211 DMAMUX_INT_GENCH1_TO = DMAMUX_REGIDX_BIT(DMAMUX_RG_CH1CFG_REG_OFFSET, 8U), /*!< DMAMUX request generator channel 1 trigger overrun interrupt */ 212 DMAMUX_INT_GENCH2_TO = DMAMUX_REGIDX_BIT(DMAMUX_RG_CH2CFG_REG_OFFSET, 8U), /*!< DMAMUX request generator channel 2 trigger overrun interrupt */ 213 DMAMUX_INT_GENCH3_TO = DMAMUX_REGIDX_BIT(DMAMUX_RG_CH3CFG_REG_OFFSET, 8U), /*!< DMAMUX request generator channel 3 trigger overrun interrupt */ 214 } dmamux_interrupt_enum; 215 216 /* DMAMUX flags */ 217 typedef enum { 218 /* flags in INTF register */ 219 DMAMUX_FLAG_MUXCH0_SO = DMAMUX_REGIDX_BIT(DMAMUX_RM_INTF_REG_OFFSET, 0U), /*!< DMAMUX request multiplexer channel 0 synchronization overrun flag */ 220 DMAMUX_FLAG_MUXCH1_SO = DMAMUX_REGIDX_BIT(DMAMUX_RM_INTF_REG_OFFSET, 1U), /*!< DMAMUX request multiplexer channel 1 synchronization overrun flag */ 221 DMAMUX_FLAG_MUXCH2_SO = DMAMUX_REGIDX_BIT(DMAMUX_RM_INTF_REG_OFFSET, 2U), /*!< DMAMUX request multiplexer channel 2 synchronization overrun flag */ 222 DMAMUX_FLAG_MUXCH3_SO = DMAMUX_REGIDX_BIT(DMAMUX_RM_INTF_REG_OFFSET, 3U), /*!< DMAMUX request multiplexer channel 3 synchronization overrun flag */ 223 DMAMUX_FLAG_MUXCH4_SO = DMAMUX_REGIDX_BIT(DMAMUX_RM_INTF_REG_OFFSET, 4U), /*!< DMAMUX request multiplexer channel 4 synchronization overrun flag */ 224 DMAMUX_FLAG_MUXCH5_SO = DMAMUX_REGIDX_BIT(DMAMUX_RM_INTF_REG_OFFSET, 5U), /*!< DMAMUX request multiplexer channel 5 synchronization overrun flag */ 225 DMAMUX_FLAG_MUXCH6_SO = DMAMUX_REGIDX_BIT(DMAMUX_RM_INTF_REG_OFFSET, 6U), /*!< DMAMUX request multiplexer channel 6 synchronization overrun flag */ 226 DMAMUX_FLAG_GENCH0_TO = DMAMUX_REGIDX_BIT(DMAMUX_RG_INTF_REG_OFFSET, 0U), /*!< DMAMUX request generator channel 0 trigger overrun flag */ 227 DMAMUX_FLAG_GENCH1_TO = DMAMUX_REGIDX_BIT(DMAMUX_RG_INTF_REG_OFFSET, 1U), /*!< DMAMUX request generator channel 1 trigger overrun flag */ 228 DMAMUX_FLAG_GENCH2_TO = DMAMUX_REGIDX_BIT(DMAMUX_RG_INTF_REG_OFFSET, 2U), /*!< DMAMUX request generator channel 2 trigger overrun flag */ 229 DMAMUX_FLAG_GENCH3_TO = DMAMUX_REGIDX_BIT(DMAMUX_RG_INTF_REG_OFFSET, 3U), /*!< DMAMUX request generator channel 3 trigger overrun flag */ 230 } dmamux_flag_enum; 231 232 /* DMAMUX interrupt flags */ 233 typedef enum { 234 /* interrupt flags in INTF register */ 235 DMAMUX_INT_FLAG_MUXCH0_SO = DMAMUX_REGIDX_BIT2(DMAMUX_RM_INTF_REG_OFFSET, 0U, DMAMUX_RM_CH0CFG_REG_OFFSET, 8U), /*!< DMAMUX request multiplexer channel 0 synchronization overrun interrupt flag */ 236 DMAMUX_INT_FLAG_MUXCH1_SO = DMAMUX_REGIDX_BIT2(DMAMUX_RM_INTF_REG_OFFSET, 1U, DMAMUX_RM_CH1CFG_REG_OFFSET, 8U), /*!< DMAMUX request multiplexer channel 1 synchronization overrun interrupt flag */ 237 DMAMUX_INT_FLAG_MUXCH2_SO = DMAMUX_REGIDX_BIT2(DMAMUX_RM_INTF_REG_OFFSET, 2U, DMAMUX_RM_CH2CFG_REG_OFFSET, 8U), /*!< DMAMUX request multiplexer channel 2 synchronization overrun interrupt flag */ 238 DMAMUX_INT_FLAG_MUXCH3_SO = DMAMUX_REGIDX_BIT2(DMAMUX_RM_INTF_REG_OFFSET, 3U, DMAMUX_RM_CH3CFG_REG_OFFSET, 8U), /*!< DMAMUX request multiplexer channel 3 synchronization overrun interrupt flag */ 239 DMAMUX_INT_FLAG_MUXCH4_SO = DMAMUX_REGIDX_BIT2(DMAMUX_RM_INTF_REG_OFFSET, 4U, DMAMUX_RM_CH4CFG_REG_OFFSET, 8U), /*!< DMAMUX request multiplexer channel 4 synchronization overrun interrupt flag */ 240 DMAMUX_INT_FLAG_MUXCH5_SO = DMAMUX_REGIDX_BIT2(DMAMUX_RM_INTF_REG_OFFSET, 5U, DMAMUX_RM_CH5CFG_REG_OFFSET, 8U), /*!< DMAMUX request multiplexer channel 5 synchronization overrun interrupt flag */ 241 DMAMUX_INT_FLAG_MUXCH6_SO = DMAMUX_REGIDX_BIT2(DMAMUX_RM_INTF_REG_OFFSET, 6U, DMAMUX_RM_CH6CFG_REG_OFFSET, 8U), /*!< DMAMUX request multiplexer channel 6 synchronization overrun interrupt flag */ 242 DMAMUX_INT_FLAG_GENCH0_TO = DMAMUX_REGIDX_BIT2(DMAMUX_RG_INTF_REG_OFFSET, 0U, DMAMUX_RG_CH0CFG_REG_OFFSET, 8U), /*!< DMAMUX request generator channel 0 trigger overrun interrupt flag */ 243 DMAMUX_INT_FLAG_GENCH1_TO = DMAMUX_REGIDX_BIT2(DMAMUX_RG_INTF_REG_OFFSET, 1U, DMAMUX_RG_CH1CFG_REG_OFFSET, 8U), /*!< DMAMUX request generator channel 1 trigger overrun interrupt flag */ 244 DMAMUX_INT_FLAG_GENCH2_TO = DMAMUX_REGIDX_BIT2(DMAMUX_RG_INTF_REG_OFFSET, 2U, DMAMUX_RG_CH2CFG_REG_OFFSET, 8U), /*!< DMAMUX request generator channel 2 trigger overrun interrupt flag */ 245 DMAMUX_INT_FLAG_GENCH3_TO = DMAMUX_REGIDX_BIT2(DMAMUX_RG_INTF_REG_OFFSET, 3U, DMAMUX_RG_CH3CFG_REG_OFFSET, 8U), /*!< DMAMUX request generator channel 3 trigger overrun interrupt flag */ 246 } dmamux_interrupt_flag_enum; 247 248 /* DMA channel selection */ 249 typedef enum { 250 DMA_CH0 = 0U, /*!< DMA Channel 0 */ 251 DMA_CH1, /*!< DMA Channel 1 */ 252 DMA_CH2, /*!< DMA Channel 2 */ 253 DMA_CH3, /*!< DMA Channel 3 */ 254 DMA_CH4, /*!< DMA Channel 4 */ 255 DMA_CH5, /*!< DMA Channel 5 */ 256 DMA_CH6, /*!< DMA Channel 6 */ 257 } dma_channel_enum; 258 259 /* DMAMUX request multiplexer channel */ 260 typedef enum { 261 DMAMUX_MUXCH0 = 0U, /*!< DMAMUX request multiplexer Channel0 */ 262 DMAMUX_MUXCH1, /*!< DMAMUX request multiplexer Channel1 */ 263 DMAMUX_MUXCH2, /*!< DMAMUX request multiplexer Channel2 */ 264 DMAMUX_MUXCH3, /*!< DMAMUX request multiplexer Channel3 */ 265 DMAMUX_MUXCH4, /*!< DMAMUX request multiplexer Channel4 */ 266 DMAMUX_MUXCH5, /*!< DMAMUX request multiplexer Channel5 */ 267 DMAMUX_MUXCH6, /*!< DMAMUX request multiplexer Channel6 */ 268 } dmamux_multiplexer_channel_enum; 269 270 /* DMAMUX request generator channel */ 271 typedef enum { 272 DMAMUX_GENCH0 = 0U, /*!< DMAMUX request generator Channel0 */ 273 DMAMUX_GENCH1, /*!< DMAMUX request generator Channel1 */ 274 DMAMUX_GENCH2, /*!< DMAMUX request generator Channel2 */ 275 DMAMUX_GENCH3, /*!< DMAMUX request generator Channel3 */ 276 } dmamux_generator_channel_enum; 277 278 /* DMA initialization structure */ 279 typedef struct { 280 uint32_t periph_addr; /*!< peripheral base address */ 281 uint32_t periph_width; /*!< transfer data size of peripheral */ 282 uint32_t memory_addr; /*!< memory base address */ 283 uint32_t memory_width; /*!< transfer data size of memory */ 284 uint32_t number; /*!< channel transfer number */ 285 uint32_t priority; /*!< channel priority level */ 286 uint8_t periph_inc; /*!< peripheral increasing mode */ 287 uint8_t memory_inc; /*!< memory increasing mode */ 288 uint8_t direction; /*!< channel data transfer direction */ 289 uint32_t request; /*!< channel input identification */ 290 } dma_parameter_struct; 291 292 /* DMAMUX request multiplexer synchronization configuration structure */ 293 typedef struct { 294 uint32_t sync_id; /*!< synchronization input identification */ 295 uint32_t sync_polarity; /*!< synchronization input polarity */ 296 uint32_t request_number; /*!< number of DMA requests to forward */ 297 } dmamux_sync_parameter_struct; 298 299 /* DMAMUX request generator trigger configuration structure */ 300 typedef struct { 301 uint32_t trigger_id; /*!< trigger input identification */ 302 uint32_t trigger_polarity; /*!< DMAMUX request generator trigger polarity */ 303 uint32_t request_number; /*!< number of DMA requests to be generated */ 304 } dmamux_gen_parameter_struct; 305 306 /* DMA reset value */ 307 #define DMA_CHCTL_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCTL register */ 308 #define DMA_CHCNT_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXCNT register */ 309 #define DMA_CHPADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXPADDR register */ 310 #define DMA_CHMADDR_RESET_VALUE ((uint32_t)0x00000000U) /*!< the reset value of DMA channel CHXMADDR register */ 311 #define DMA_CHINTF_RESET_VALUE (DMA_INTF_GIF | DMA_INTF_FTFIF | \ 312 DMA_INTF_HTFIF | DMA_INTF_ERRIF) /*!< clear DMA channel DMA_INTF register */ 313 314 #define DMA_FLAG_ADD(flag,shift) ((flag) << ((uint32_t)(shift) * 4U)) /*!< DMA channel flag shift */ 315 316 /* DMA_CHCTL base address */ 317 #define DMA_CHXCTL_BASE (DMA + 0x00000008U) /*!< the base address of DMA channel CHXCTL register */ 318 #define DMA_CHXCNT_BASE (DMA + 0x0000000CU) /*!< the base address of DMA channel CHXCNT register */ 319 #define DMA_CHXPADDR_BASE (DMA + 0x00000010U) /*!< the base address of DMA channel CHXPADDR register */ 320 #define DMA_CHXMADDR_BASE (DMA + 0x00000014U) /*!< the base address of DMA channel CHXMADDR register */ 321 322 /* DMA channel shift bit */ 323 #define DMA_CHCTL(channel) REG32(DMA_CHXCTL_BASE + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXCTL register */ 324 #define DMA_CHCNT(channel) REG32(DMA_CHXCNT_BASE + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXCNT register */ 325 #define DMA_CHPADDR(channel) REG32(DMA_CHXPADDR_BASE + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXPADDR register */ 326 #define DMA_CHMADDR(channel) REG32(DMA_CHXMADDR_BASE + 0x14U * (uint32_t)(channel)) /*!< the address of DMA channel CHXMADDR register */ 327 328 /* DMAMUX_RM_CHxCFG base address */ 329 #define DMAMUX_RM_CHXCFG_BASE (DMAMUX) /*!< the base address of DMAMUX request multiplexer channel CHxCFG register */ 330 331 /* DMAMUX request multiplexer channel shift bit */ 332 #define DMAMUX_RM_CHXCFG(channel) REG32(DMAMUX_RM_CHXCFG_BASE + 0x04U * (uint32_t)(channel)) /*!< the address of DMAMUX request multiplexer channel CHxCFG register */ 333 334 /* DMAMUX_RG_CHxCFG base address */ 335 #define DMAMUX_RG_CHXCFG_BASE (DMAMUX + 0x00000100U) /*!< the base address of DMAMUX channel request generator CHxCFG register */ 336 337 /* DMAMUX request generator channel shift bit */ 338 #define DMAMUX_RG_CHXCFG(channel) REG32(DMAMUX_RG_CHXCFG_BASE + 0x04U * (uint32_t)(channel)) /*!< the address of DMAMUX channel request generator CHxCFG register */ 339 340 /* DMA interrupt flag bits */ 341 #define DMA_INT_FLAG_G DMA_INTF_GIF /*!< global interrupt flag of DMA channel */ 342 #define DMA_INT_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish interrupt flag of DMA channel */ 343 #define DMA_INT_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish interrupt flag of DMA channel */ 344 #define DMA_INT_FLAG_ERR DMA_INTF_ERRIF /*!< error interrupt flag of DMA channel */ 345 346 /* DMA flag bits */ 347 #define DMA_FLAG_G DMA_INTF_GIF /*!< global interrupt flag of DMA channel */ 348 #define DMA_FLAG_FTF DMA_INTF_FTFIF /*!< full transfer finish flag of DMA channel */ 349 #define DMA_FLAG_HTF DMA_INTF_HTFIF /*!< half transfer finish flag of DMA channel */ 350 #define DMA_FLAG_ERR DMA_INTF_ERRIF /*!< error flag of DMA channel */ 351 352 /* DMA interrupt enable bits */ 353 #define DMA_INT_FTF DMA_CHXCTL_FTFIE /*!< enable bit for DMA channel full transfer finish interrupt */ 354 #define DMA_INT_HTF DMA_CHXCTL_HTFIE /*!< enable bit for DMA channel half transfer finish interrupt */ 355 #define DMA_INT_ERR DMA_CHXCTL_ERRIE /*!< enable bit for DMA channel error interrupt */ 356 357 /* DMA transfer direction */ 358 #define DMA_PERIPHERAL_TO_MEMORY ((uint8_t)0x00U) /*!< read from peripheral and write to memory */ 359 #define DMA_MEMORY_TO_PERIPHERAL ((uint8_t)0x01U) /*!< read from memory and write to peripheral */ 360 361 /* DMA peripheral increasing mode */ 362 #define DMA_PERIPH_INCREASE_DISABLE ((uint8_t)0x00U) /*!< next address of peripheral is fixed address mode */ 363 #define DMA_PERIPH_INCREASE_ENABLE ((uint8_t)0x01U) /*!< next address of peripheral is increasing address mode */ 364 365 /* DMA memory increasing mode */ 366 #define DMA_MEMORY_INCREASE_DISABLE ((uint8_t)0x00U) /*!< next address of memory is fixed address mode */ 367 #define DMA_MEMORY_INCREASE_ENABLE ((uint8_t)0x01U) /*!< next address of memory is increasing address mode */ 368 369 /* DMA transfer data size of peripheral */ 370 #define CHCTL_PWIDTH(regval) (BITS(8,9) & ((regval) << 8)) /*!< transfer data size of peripheral */ 371 #define DMA_PERIPHERAL_WIDTH_8BIT CHCTL_PWIDTH(0U) /*!< transfer data size of peripheral is 8-bit */ 372 #define DMA_PERIPHERAL_WIDTH_16BIT CHCTL_PWIDTH(1U) /*!< transfer data size of peripheral is 16-bit */ 373 #define DMA_PERIPHERAL_WIDTH_32BIT CHCTL_PWIDTH(2U) /*!< transfer data size of peripheral is 32-bit */ 374 375 /* DMA transfer data size of memory */ 376 #define CHCTL_MWIDTH(regval) (BITS(10,11) & ((regval) << 10)) /*!< transfer data size of memory */ 377 #define DMA_MEMORY_WIDTH_8BIT CHCTL_MWIDTH(0U) /*!< transfer data size of memory is 8-bit */ 378 #define DMA_MEMORY_WIDTH_16BIT CHCTL_MWIDTH(1U) /*!< transfer data size of memory is 16-bit */ 379 #define DMA_MEMORY_WIDTH_32BIT CHCTL_MWIDTH(2U) /*!< transfer data size of memory is 32-bit */ 380 381 /* DMA channel priority level */ 382 #define CHCTL_PRIO(regval) (BITS(12,13) & ((regval) << 12)) /*!< DMA channel priority level */ 383 #define DMA_PRIORITY_LOW CHCTL_PRIO(0U) /*!< low priority */ 384 #define DMA_PRIORITY_MEDIUM CHCTL_PRIO(1U) /*!< medium priority */ 385 #define DMA_PRIORITY_HIGH CHCTL_PRIO(2U) /*!< high priority */ 386 #define DMA_PRIORITY_ULTRA_HIGH CHCTL_PRIO(3U) /*!< ultra high priority */ 387 388 /* DMA transfer counter */ 389 #define DMA_CHANNEL_CNT_MASK DMA_CHXCNT_CNT /*!< transfer counter mask */ 390 391 /* DMAMUX request multiplexer channel input identification */ 392 #define RM_CHXCFG_MUXID(regval) (BITS(0,5) & ((regval) << 0)) /*!< multiplexer input identification */ 393 #define DMA_REQUEST_M2M RM_CHXCFG_MUXID(0U) /*!< memory to memory transfer */ 394 #define DMA_REQUEST_GENERATOR0 RM_CHXCFG_MUXID(1U) /*!< DMAMUX request generator 0 */ 395 #define DMA_REQUEST_GENERATOR1 RM_CHXCFG_MUXID(2U) /*!< DMAMUX request generator 1 */ 396 #define DMA_REQUEST_GENERATOR2 RM_CHXCFG_MUXID(3U) /*!< DMAMUX request generator 2 */ 397 #define DMA_REQUEST_GENERATOR3 RM_CHXCFG_MUXID(4U) /*!< DMAMUX request generator 3 */ 398 #define DMA_REQUEST_ADC RM_CHXCFG_MUXID(5U) /*!< DMAMUX ADC request */ 399 #define DMA_REQUEST_DAC RM_CHXCFG_MUXID(6U) /*!< DMAMUX DAC CH0 request */ 400 #define DMA_REQUEST_I2C0_RX RM_CHXCFG_MUXID(10U) /*!< DMAMUX I2C0 RX request */ 401 #define DMA_REQUEST_I2C0_TX RM_CHXCFG_MUXID(11U) /*!< DMAMUX I2C0 TX request */ 402 #define DMA_REQUEST_I2C1_RX RM_CHXCFG_MUXID(12U) /*!< DMAMUX I2C1 RX request */ 403 #define DMA_REQUEST_I2C1_TX RM_CHXCFG_MUXID(13U) /*!< DMAMUX I2C1 TX request */ 404 #define DMA_REQUEST_I2C2_RX RM_CHXCFG_MUXID(14U) /*!< DMAMUX I2C2 RX request */ 405 #define DMA_REQUEST_I2C2_TX RM_CHXCFG_MUXID(15U) /*!< DMAMUX I2C2 TX request */ 406 #define DMA_REQUEST_SPI0_RX RM_CHXCFG_MUXID(16U) /*!< DMAMUX SPI0 RX request */ 407 #define DMA_REQUEST_SPI0_TX RM_CHXCFG_MUXID(17U) /*!< DMAMUX SPI0 TX request */ 408 #define DMA_REQUEST_SPI1_RX RM_CHXCFG_MUXID(18U) /*!< DMAMUX SPI1 RX request */ 409 #define DMA_REQUEST_SPI1_TX RM_CHXCFG_MUXID(19U) /*!< DMAMUX SPI1 TX request */ 410 #define DMA_REQUEST_TIMER1_CH0 RM_CHXCFG_MUXID(25U) /*!< DMAMUX TIMER1 CH0 request */ 411 #define DMA_REQUEST_TIMER1_CH1 RM_CHXCFG_MUXID(26U) /*!< DMAMUX TIMER1 CH1 request */ 412 #define DMA_REQUEST_TIMER1_CH2 RM_CHXCFG_MUXID(27U) /*!< DMAMUX TIMER1 CH2 request */ 413 #define DMA_REQUEST_TIMER1_CH3 RM_CHXCFG_MUXID(28U) /*!< DMAMUX TIMER1 CH3 request */ 414 #define DMA_REQUEST_TIMER1_UP RM_CHXCFG_MUXID(30U) /*!< DMAMUX TIMER1 UP request */ 415 #define DMA_REQUEST_TIMER2_CH0 RM_CHXCFG_MUXID(32U) /*!< DMAMUX TIMER2 CH0 request */ 416 #define DMA_REQUEST_TIMER2_CH1 RM_CHXCFG_MUXID(33U) /*!< DMAMUX TIMER2 CH1 request */ 417 #define DMA_REQUEST_TIMER2_CH2 RM_CHXCFG_MUXID(34U) /*!< DMAMUX TIMER2 CH2 request */ 418 #define DMA_REQUEST_TIMER2_CH3 RM_CHXCFG_MUXID(35U) /*!< DMAMUX TIMER2 CH3 request */ 419 #define DMA_REQUEST_TIMER2_TRIG RM_CHXCFG_MUXID(36U) /*!< DMAMUX TIMER2 TRIG request */ 420 #define DMA_REQUEST_TIMER2_UP RM_CHXCFG_MUXID(37U) /*!< DMAMUX TIMER2 UP request */ 421 #define DMA_REQUEST_TIMER5_UP RM_CHXCFG_MUXID(42U) /*!< DMAMUX TIMER5 UP request */ 422 #define DMA_REQUEST_TIMER6_UP RM_CHXCFG_MUXID(43U) /*!< DMAMUX TIMER6 UP request */ 423 #define DMA_REQUEST_CAU_IN RM_CHXCFG_MUXID(44U) /*!< DMAMUX CAU IN request */ 424 #define DMA_REQUEST_CAU_OUT RM_CHXCFG_MUXID(45U) /*!< DMAMUX CAU OUT request */ 425 #define DMA_REQUEST_USART0_RX RM_CHXCFG_MUXID(50U) /*!< DMAMUX USART0 RX request */ 426 #define DMA_REQUEST_USART0_TX RM_CHXCFG_MUXID(51U) /*!< DMAMUX USART0 TX request */ 427 #define DMA_REQUEST_USART1_RX RM_CHXCFG_MUXID(52U) /*!< DMAMUX USART1 RX request */ 428 #define DMA_REQUEST_USART1_TX RM_CHXCFG_MUXID(53U) /*!< DMAMUX USART1 TX request */ 429 #define DMA_REQUEST_UART3_RX RM_CHXCFG_MUXID(54U) /*!< DMAMUX UART3 RX request */ 430 #define DMA_REQUEST_UART3_TX RM_CHXCFG_MUXID(55U) /*!< DMAMUX UART3 TX request */ 431 #define DMA_REQUEST_UART4_RX RM_CHXCFG_MUXID(56U) /*!< DMAMUX UART4 RX request */ 432 #define DMA_REQUEST_UART4_TX RM_CHXCFG_MUXID(57U) /*!< DMAMUX UART4 TX request */ 433 #define DMA_REQUEST_LPUART_RX RM_CHXCFG_MUXID(58U) /*!< DMAMUX LPUART RX request */ 434 #define DMA_REQUEST_LPUART_TX RM_CHXCFG_MUXID(59U) /*!< DMAMUX LPUART TX request */ 435 436 /* DMAMUX request generator trigger input identification */ 437 #define RG_CHXCFG_TID(regval) (BITS(0,4) & ((regval) << 0)) /*!< trigger input identification */ 438 #define DMAMUX_TRIGGER_EXTI0 RG_CHXCFG_TID(0U) /*!< trigger input is EXTI0 */ 439 #define DMAMUX_TRIGGER_EXTI1 RG_CHXCFG_TID(1U) /*!< trigger input is EXTI1 */ 440 #define DMAMUX_TRIGGER_EXTI2 RG_CHXCFG_TID(2U) /*!< trigger input is EXTI2 */ 441 #define DMAMUX_TRIGGER_EXTI3 RG_CHXCFG_TID(3U) /*!< trigger input is EXTI3 */ 442 #define DMAMUX_TRIGGER_EXTI4 RG_CHXCFG_TID(4U) /*!< trigger input is EXTI4 */ 443 #define DMAMUX_TRIGGER_EXTI5 RG_CHXCFG_TID(5U) /*!< trigger input is EXTI5 */ 444 #define DMAMUX_TRIGGER_EXTI6 RG_CHXCFG_TID(6U) /*!< trigger input is EXTI6 */ 445 #define DMAMUX_TRIGGER_EXTI7 RG_CHXCFG_TID(7U) /*!< trigger input is EXTI7 */ 446 #define DMAMUX_TRIGGER_EXTI8 RG_CHXCFG_TID(8U) /*!< trigger input is EXTI8 */ 447 #define DMAMUX_TRIGGER_EXTI9 RG_CHXCFG_TID(9U) /*!< trigger input is EXTI9 */ 448 #define DMAMUX_TRIGGER_EXTI10 RG_CHXCFG_TID(10U) /*!< trigger input is EXTI10 */ 449 #define DMAMUX_TRIGGER_EXTI11 RG_CHXCFG_TID(11U) /*!< trigger input is EXTI11 */ 450 #define DMAMUX_TRIGGER_EXTI12 RG_CHXCFG_TID(12U) /*!< trigger input is EXTI12 */ 451 #define DMAMUX_TRIGGER_EXTI13 RG_CHXCFG_TID(13U) /*!< trigger input is EXTI13 */ 452 #define DMAMUX_TRIGGER_EXTI14 RG_CHXCFG_TID(14U) /*!< trigger input is EXTI14 */ 453 #define DMAMUX_TRIGGER_EXTI15 RG_CHXCFG_TID(15U) /*!< trigger input is EXTI15 */ 454 #define DMAMUX_TRIGGER_EVT0_OUT RG_CHXCFG_TID(16U) /*!< trigger input is Evt0_out */ 455 #define DMAMUX_TRIGGER_EVT1_OUT RG_CHXCFG_TID(17U) /*!< trigger input is Evt1_out */ 456 #define DMAMUX_TRIGGER_EVT2_OUT RG_CHXCFG_TID(18U) /*!< trigger input is Evt2_out */ 457 #define DMAMUX_TRIGGER_EVT3_OUT RG_CHXCFG_TID(19U) /*!< trigger input is Evt3_out */ 458 #define DMAMUX_TRIGGER_TIMER11_CH0_O RG_CHXCFG_TID(22U) /*!< trigger input is TIMER11_CH0_O */ 459 460 /* DMAMUX request generator trigger polarity */ 461 #define RG_CHXCFG_RGTP(regval) (BITS(17,18) & ((regval) << 17)) /*!< DMA request generator trigger polarity */ 462 #define DMAMUX_GEN_NO_EVENT RG_CHXCFG_RGTP(0U) /*!< no event detection */ 463 #define DMAMUX_GEN_RISING RG_CHXCFG_RGTP(1U) /*!< rising edge */ 464 #define DMAMUX_GEN_FALLING RG_CHXCFG_RGTP(2U) /*!< falling edge */ 465 #define DMAMUX_GEN_RISING_FALLING RG_CHXCFG_RGTP(3U) /*!< rising and falling edges */ 466 467 /* number of DMA requests to be generated */ 468 #define RG_CHXCFG_NBRG(regval) (BITS(19,23) & ((regval) << 19)) /*!< number of DMA requests to be generated */ 469 470 /* DMAMUX request multiplexer channel synchronization input identification */ 471 #define RM_CHXCFG_SYNCID(regval) (BITS(24,28) & ((regval) << 24)) /*!< synchronization input identification */ 472 #define DMAMUX_SYNC_EXTI0 RM_CHXCFG_SYNCID(0U) /*!< synchronization input is EXTI0 */ 473 #define DMAMUX_SYNC_EXTI1 RM_CHXCFG_SYNCID(1U) /*!< synchronization input is EXTI1 */ 474 #define DMAMUX_SYNC_EXTI2 RM_CHXCFG_SYNCID(2U) /*!< synchronization input is EXTI2 */ 475 #define DMAMUX_SYNC_EXTI3 RM_CHXCFG_SYNCID(3U) /*!< synchronization input is EXTI3 */ 476 #define DMAMUX_SYNC_EXTI4 RM_CHXCFG_SYNCID(4U) /*!< synchronization input is EXTI4 */ 477 #define DMAMUX_SYNC_EXTI5 RM_CHXCFG_SYNCID(5U) /*!< synchronization input is EXTI5 */ 478 #define DMAMUX_SYNC_EXTI6 RM_CHXCFG_SYNCID(6U) /*!< synchronization input is EXTI6 */ 479 #define DMAMUX_SYNC_EXTI7 RM_CHXCFG_SYNCID(7U) /*!< synchronization input is EXTI7 */ 480 #define DMAMUX_SYNC_EXTI8 RM_CHXCFG_SYNCID(8U) /*!< synchronization input is EXTI8 */ 481 #define DMAMUX_SYNC_EXTI9 RM_CHXCFG_SYNCID(9U) /*!< synchronization input is EXTI9 */ 482 #define DMAMUX_SYNC_EXTI10 RM_CHXCFG_SYNCID(10U) /*!< synchronization input is EXTI10 */ 483 #define DMAMUX_SYNC_EXTI11 RM_CHXCFG_SYNCID(11U) /*!< synchronization input is EXTI11 */ 484 #define DMAMUX_SYNC_EXTI12 RM_CHXCFG_SYNCID(12U) /*!< synchronization input is EXTI12 */ 485 #define DMAMUX_SYNC_EXTI13 RM_CHXCFG_SYNCID(13U) /*!< synchronization input is EXTI13 */ 486 #define DMAMUX_SYNC_EXTI14 RM_CHXCFG_SYNCID(14U) /*!< synchronization input is EXTI14 */ 487 #define DMAMUX_SYNC_EXTI15 RM_CHXCFG_SYNCID(15U) /*!< synchronization input is EXTI15 */ 488 #define DMAMUX_SYNC_EVT0_OUT RM_CHXCFG_SYNCID(16U) /*!< synchronization input is Evt0_out */ 489 #define DMAMUX_SYNC_EVT1_OUT RM_CHXCFG_SYNCID(17U) /*!< synchronization input is Evt1_out */ 490 #define DMAMUX_SYNC_EVT2_OUT RM_CHXCFG_SYNCID(18U) /*!< synchronization input is Evt2_out */ 491 #define DMAMUX_SYNC_EVT3_OUT RM_CHXCFG_SYNCID(19U) /*!< synchronization input is Evt3_out */ 492 #define DMAMUX_SYNC_TIMER11_CH0_O RM_CHXCFG_SYNCID(22U) /*!< synchronization input is TIMER11_CH0_O */ 493 494 /* DMAMUX request multiplexer synchronization input polarity */ 495 #define RM_CHXCFG_SYNCP(regval) (BITS(17,18) & ((regval) << 17)) /*!< synchronization input polarity */ 496 #define DMAMUX_SYNC_NO_EVENT RM_CHXCFG_SYNCP(0U) /*!< no event detection */ 497 #define DMAMUX_SYNC_RISING RM_CHXCFG_SYNCP(1U) /*!< rising edge */ 498 #define DMAMUX_SYNC_FALLING RM_CHXCFG_SYNCP(2U) /*!< falling edge */ 499 #define DMAMUX_SYNC_RISING_FALLING RM_CHXCFG_SYNCP(3U) /*!< rising and falling edges */ 500 501 /* number of DMA requests to forward */ 502 #define RM_CHXCFG_NBR(regval) (BITS(19,23) & ((regval) << 19)) /*!< number of DMA requests to forward */ 503 504 /* function declarations */ 505 /* DMA functions */ 506 /* DMA initialization functions */ 507 /* deinitialize DMA a channel registers */ 508 void dma_deinit(dma_channel_enum channelx); 509 /* initialize the parameters of DMA structure with the default values */ 510 void dma_struct_para_init(dma_parameter_struct *init_struct); 511 /* initialize DMA channel */ 512 void dma_init(dma_channel_enum channelx, dma_parameter_struct *init_struct); 513 /* enable DMA circulation mode */ 514 void dma_circulation_enable(dma_channel_enum channelx); 515 /* disable DMA circulation mode */ 516 void dma_circulation_disable(dma_channel_enum channelx); 517 /* enable memory to memory mode */ 518 void dma_memory_to_memory_enable(dma_channel_enum channelx); 519 /* disable memory to memory mode */ 520 void dma_memory_to_memory_disable(dma_channel_enum channelx); 521 /* enable DMA channel */ 522 void dma_channel_enable(dma_channel_enum channelx); 523 /* disable DMA channel */ 524 void dma_channel_disable(dma_channel_enum channelx); 525 526 /* DMA configuration functions */ 527 /* set DMA peripheral base address */ 528 void dma_periph_address_config(dma_channel_enum channelx, uint32_t address); 529 /* set DMA memory base address */ 530 void dma_memory_address_config(dma_channel_enum channelx, uint32_t address); 531 /* set the number of remaining data to be transferred by the DMA */ 532 void dma_transfer_number_config(dma_channel_enum channelx, uint32_t number); 533 /* get the number of remaining data to be transferred by the DMA */ 534 uint32_t dma_transfer_number_get(dma_channel_enum channelx); 535 /* configure priority level of DMA channel */ 536 void dma_priority_config(dma_channel_enum channelx, uint32_t priority); 537 /* configure transfer data size of memory */ 538 void dma_memory_width_config(dma_channel_enum channelx, uint32_t mwidth); 539 /* configure transfer data size of peripheral */ 540 void dma_periph_width_config(dma_channel_enum channelx, uint32_t pwidth); 541 /* enable next address increasement algorithm of memory */ 542 void dma_memory_increase_enable(dma_channel_enum channelx); 543 /* disable next address increasement algorithm of memory */ 544 void dma_memory_increase_disable(dma_channel_enum channelx); 545 /* enable next address increasement algorithm of peripheral */ 546 void dma_periph_increase_enable(dma_channel_enum channelx); 547 /* disable next address increasement algorithm of peripheral */ 548 void dma_periph_increase_disable(dma_channel_enum channelx); 549 /* configure the direction of data transfer on the channel */ 550 void dma_transfer_direction_config(dma_channel_enum channelx, uint32_t direction); 551 552 /* DMA interrupt and flag functions */ 553 /* check DMA flag is set or not */ 554 FlagStatus dma_flag_get(dma_channel_enum channelx, uint32_t flag); 555 /* clear a DMA channel flag */ 556 void dma_flag_clear(dma_channel_enum channelx, uint32_t flag); 557 /* check DMA flag and interrupt enable bit is set or not */ 558 FlagStatus dma_interrupt_flag_get(dma_channel_enum channelx, uint32_t int_flag); 559 /* clear a DMA channel interrupt flag */ 560 void dma_interrupt_flag_clear(dma_channel_enum channelx, uint32_t int_flag); 561 /* enable DMA interrupt */ 562 void dma_interrupt_enable(dma_channel_enum channelx, uint32_t source); 563 /* disable DMA interrupt */ 564 void dma_interrupt_disable(dma_channel_enum channelx, uint32_t source); 565 566 /* DMAMUX functions */ 567 /* DMAMUX request multiplexer functions */ 568 /* initialize the parameters of DMAMUX synchronization mode structure with the default values */ 569 void dmamux_sync_struct_para_init(dmamux_sync_parameter_struct *init_struct); 570 /* initialize DMAMUX request multiplexer channel synchronization mode */ 571 void dmamux_synchronization_init(dmamux_multiplexer_channel_enum channelx, dmamux_sync_parameter_struct *init_struct); 572 /* enable synchronization mode */ 573 void dmamux_synchronization_enable(dmamux_multiplexer_channel_enum channelx); 574 /* disable synchronization mode */ 575 void dmamux_synchronization_disable(dmamux_multiplexer_channel_enum channelx); 576 /* enable event generation */ 577 void dmamux_event_generation_enable(dmamux_multiplexer_channel_enum channelx); 578 /* disable event generation */ 579 void dmamux_event_generation_disable(dmamux_multiplexer_channel_enum channelx); 580 581 /* DMAMUX request generator functions */ 582 /* initialize the parameters of DMAMUX request generator structure with the default values */ 583 void dmamux_gen_struct_para_init(dmamux_gen_parameter_struct *init_struct); 584 /* initialize DMAMUX request generator channel */ 585 void dmamux_request_generator_init(dmamux_generator_channel_enum channelx, dmamux_gen_parameter_struct *init_struct); 586 /* enable DMAMUX request generator channel */ 587 void dmamux_request_generator_chennel_enable(dmamux_generator_channel_enum channelx); 588 /* disable DMAMUX request generator channel */ 589 void dmamux_request_generator_chennel_disable(dmamux_generator_channel_enum channelx); 590 591 /* DMAMUX configuration functions */ 592 /* configure synchronization input polarity */ 593 void dmamux_synchronization_polarity_config(dmamux_multiplexer_channel_enum channelx, uint32_t polarity); 594 /* configure number of DMA requests to forward */ 595 void dmamux_request_forward_number_config(dmamux_multiplexer_channel_enum channelx, uint32_t number); 596 /* configure synchronization input identification */ 597 void dmamux_sync_id_config(dmamux_multiplexer_channel_enum channelx, uint32_t id); 598 /* configure multiplexer input identification */ 599 void dmamux_request_id_config(dmamux_multiplexer_channel_enum channelx, uint32_t id); 600 /* configure trigger input polarity */ 601 void dmamux_trigger_polarity_config(dmamux_generator_channel_enum channelx, uint32_t polarity); 602 /* configure number of DMA requests to be generated */ 603 void dmamux_request_generate_number_config(dmamux_generator_channel_enum channelx, uint32_t number); 604 /* configure trigger input identification */ 605 void dmamux_trigger_id_config(dmamux_generator_channel_enum channelx, uint32_t id); 606 607 /* DMAMUX interrupt and flag functions */ 608 /* get DMAMUX flag */ 609 FlagStatus dmamux_flag_get(dmamux_flag_enum flag); 610 /* clear DMAMUX flag */ 611 void dmamux_flag_clear(dmamux_flag_enum flag); 612 /* get DMAMUX interrupt flag */ 613 FlagStatus dmamux_interrupt_flag_get(dmamux_interrupt_flag_enum int_flag); 614 /* clear DMAMUX interrupt flag */ 615 void dmamux_interrupt_flag_clear(dmamux_interrupt_flag_enum int_flag); 616 /* enable DMAMUX interrupt */ 617 void dmamux_interrupt_enable(dmamux_interrupt_enum interrupt); 618 /* disable DMAMUX interrupt */ 619 void dmamux_interrupt_disable(dmamux_interrupt_enum interrupt); 620 621 #endif /* GD32L23X_DMA_H */ 622
