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Searched refs:PMU_CS (Results 1 – 16 of 16) sorted by relevance

/hal_gigadevice-latest/gd32f4xx/cmsis/gd/gd32f4xx/source/
Dsystem_gd32f4xx.c336 while(0U == (PMU_CS & PMU_CS_HDRF)){ in system_clock_120m_irc16m()
341 while(0U == (PMU_CS & PMU_CS_HDSRF)){ in system_clock_120m_irc16m()
404 while(0U == (PMU_CS & PMU_CS_HDRF)){ in system_clock_120m_8m_hxtal()
409 while(0U == (PMU_CS & PMU_CS_HDSRF)){ in system_clock_120m_8m_hxtal()
472 while(0U == (PMU_CS & PMU_CS_HDRF)){ in system_clock_120m_25m_hxtal()
477 while(0U == (PMU_CS & PMU_CS_HDSRF)){ in system_clock_120m_25m_hxtal()
540 while(0U == (PMU_CS & PMU_CS_HDRF)){ in system_clock_168m_irc16m()
545 while(0U == (PMU_CS & PMU_CS_HDSRF)){ in system_clock_168m_irc16m()
604 while(0U == (PMU_CS & PMU_CS_HDRF)){ in system_clock_168m_8m_hxtal()
609 while(0U == (PMU_CS & PMU_CS_HDSRF)){ in system_clock_168m_8m_hxtal()
[all …]
/hal_gigadevice-latest/gd32f403/cmsis/gd/gd32f403/source/
Dsystem_gd32f403.c288 while(0U == (PMU_CS & PMU_CS_HDRF)){ in system_clock_48m_irc8m()
293 while(0U == (PMU_CS & PMU_CS_HDSRF)){ in system_clock_48m_irc8m()
357 while(0U == (PMU_CS & PMU_CS_HDRF)){ in system_clock_72m_irc8m()
362 while(0U == (PMU_CS & PMU_CS_HDSRF)){ in system_clock_72m_irc8m()
426 while(0U == (PMU_CS & PMU_CS_HDRF)){ in system_clock_108m_irc8m()
431 while(0U == (PMU_CS & PMU_CS_HDSRF)){ in system_clock_108m_irc8m()
495 while(0U == (PMU_CS & PMU_CS_HDRF)){ in system_clock_120m_irc8m()
500 while(0U == (PMU_CS & PMU_CS_HDSRF)){ in system_clock_120m_irc8m()
564 while(0U == (PMU_CS & PMU_CS_HDRF)){ in system_clock_168m_irc8m()
569 while(0U == (PMU_CS & PMU_CS_HDSRF)){ in system_clock_168m_irc8m()
[all …]
/hal_gigadevice-latest/gd32f4xx/standard_peripheral/source/
Dgd32f4xx_pmu.c319 PMU_CS |= PMU_CS_WUPEN; in pmu_wakeup_pin_enable()
330 PMU_CS &= ~PMU_CS_WUPEN; in pmu_wakeup_pin_disable()
343 PMU_CS &= ~PMU_CS_BLDOON; in pmu_backup_ldo_config()
344 PMU_CS |= bkp_ldo; in pmu_backup_ldo_config()
385 if(PMU_CS & flag) { in pmu_flag_get()
/hal_gigadevice-latest/gd32vf103/standard_peripheral/source/
Dgd32vf103_pmu.c193 PMU_CS |= PMU_CS_WUPEN; in pmu_wakeup_pin_enable()
204 PMU_CS &= ~PMU_CS_WUPEN; in pmu_wakeup_pin_disable()
241 if(PMU_CS & flag){ in pmu_flag_get()
/hal_gigadevice-latest/gd32e10x/standard_peripheral/source/
Dgd32e10x_pmu.c220 PMU_CS |= PMU_CS_WUPEN; in pmu_wakeup_pin_enable()
231 PMU_CS &= ~PMU_CS_WUPEN; in pmu_wakeup_pin_disable()
268 if(RESET != (PMU_CS & flag)){ in pmu_flag_get()
/hal_gigadevice-latest/gd32a50x/standard_peripheral/source/
Dgd32a50x_pmu.c293 PMU_CS |= wakeup_pin; in pmu_wakeup_pin_enable()
307 PMU_CS &= ~(wakeup_pin); in pmu_wakeup_pin_disable()
345 if(0U != (PMU_CS & flag)) { in pmu_flag_get()
/hal_gigadevice-latest/gd32f403/standard_peripheral/source/
Dgd32f403_pmu.c335 if(PMU_CS & flag){ in pmu_flag_get()
372 PMU_CS |= PMU_CS_WUPEN; in pmu_wakeup_pin_enable()
383 PMU_CS &= ~PMU_CS_WUPEN; in pmu_wakeup_pin_disable()
/hal_gigadevice-latest/gd32f3x0/standard_peripheral/source/
Dgd32f3x0_pmu.c324 PMU_CS |= wakeup_pin; in pmu_wakeup_pin_enable()
341 PMU_CS &= ~(wakeup_pin); in pmu_wakeup_pin_disable()
405 if(PMU_CS & flag){ in pmu_flag_get()
/hal_gigadevice-latest/gd32l23x/standard_peripheral/source/
Dgd32l23x_pmu.c292 PMU_CS |= wakeup_pin; in pmu_wakeup_pin_enable()
309 PMU_CS &= ~(wakeup_pin); in pmu_wakeup_pin_disable()
511 if(PMU_CS & flag) { in pmu_flag_get()
/hal_gigadevice-latest/gd32vf103/standard_peripheral/include/
Dgd32vf103_pmu.h46 #define PMU_CS REG32((PMU) + 0x04U) /*!< PMU control and status register… macro
/hal_gigadevice-latest/gd32e10x/standard_peripheral/include/
Dgd32e10x_pmu.h48 #define PMU_CS REG32((PMU) + 0x04U) /*!< PMU control and status register… macro
/hal_gigadevice-latest/gd32a50x/standard_peripheral/include/
Dgd32a50x_pmu.h45 #define PMU_CS REG32((PMU) + 0x00000004U) /*!< PMU control and status reg… macro
/hal_gigadevice-latest/gd32f403/standard_peripheral/include/
Dgd32f403_pmu.h47 #define PMU_CS REG32((PMU) + 0x04U) /*!< PMU control and status register… macro
/hal_gigadevice-latest/gd32f3x0/standard_peripheral/include/
Dgd32f3x0_pmu.h47 #define PMU_CS REG32(PMU + 0x00000004U) /*!< PMU control and status register… macro
/hal_gigadevice-latest/gd32f4xx/standard_peripheral/include/
Dgd32f4xx_pmu.h49 #define PMU_CS REG32((PMU) + 0x00000004U) /*!< PMU control and status… macro
/hal_gigadevice-latest/gd32l23x/standard_peripheral/include/
Dgd32l23x_pmu.h45 #define PMU_CS REG32((PMU) + 0x00000004U) /*!< PMU control and st… macro