1 /*! 2 \file gd32f403_pmu.h 3 \brief definitions for the PMU 4 5 \version 2017-02-10, V1.0.0, firmware for GD32F403 6 \version 2018-12-25, V2.0.0, firmware for GD32F403 7 \version 2020-09-30, V2.1.0, firmware for GD32F403 8 */ 9 10 /* 11 Copyright (c) 2020, GigaDevice Semiconductor Inc. 12 13 Redistribution and use in source and binary forms, with or without modification, 14 are permitted provided that the following conditions are met: 15 16 1. Redistributions of source code must retain the above copyright notice, this 17 list of conditions and the following disclaimer. 18 2. Redistributions in binary form must reproduce the above copyright notice, 19 this list of conditions and the following disclaimer in the documentation 20 and/or other materials provided with the distribution. 21 3. Neither the name of the copyright holder nor the names of its contributors 22 may be used to endorse or promote products derived from this software without 23 specific prior written permission. 24 25 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 26 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 27 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 29 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 30 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 31 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 32 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 34 OF SUCH DAMAGE. 35 */ 36 37 #ifndef GD32F403_PMU_H 38 #define GD32F403_PMU_H 39 40 #include "gd32f403.h" 41 42 /* PMU definitions */ 43 #define PMU PMU_BASE /*!< PMU base address */ 44 45 /* registers definitions */ 46 #define PMU_CTL REG32((PMU) + 0x00U) /*!< PMU control register */ 47 #define PMU_CS REG32((PMU) + 0x04U) /*!< PMU control and status register */ 48 49 /* bits definitions */ 50 /* PMU_CTL */ 51 #define PMU_CTL_LDOLP BIT(0) /*!< LDO low power mode */ 52 #define PMU_CTL_STBMOD BIT(1) /*!< standby mode */ 53 #define PMU_CTL_WURST BIT(2) /*!< wakeup flag reset */ 54 #define PMU_CTL_STBRST BIT(3) /*!< standby flag reset */ 55 #define PMU_CTL_LVDEN BIT(4) /*!< low voltage detector enable */ 56 #define PMU_CTL_LVDT BITS(5,7) /*!< low voltage detector threshold */ 57 #define PMU_CTL_BKPWEN BIT(8) /*!< backup domain write enable */ 58 #define PMU_CTL_LDLP BIT(10) /*!< low-driver mode when use low power LDO */ 59 #define PMU_CTL_LDNP BIT(11) /*!< low-driver mode when use normal power LDO */ 60 #define PMU_CTL_LDOVS BITS(14,15) /*!< LDO output voltage select */ 61 #define PMU_CTL_HDEN BIT(16) /*!< high-driver mode enable */ 62 #define PMU_CTL_HDS BIT(17) /*!< high-driver mode switch */ 63 #define PMU_CTL_LDEN BITS(18,19) /*!< low-driver mode enable in deep-sleep mode */ 64 65 /* PMU_CS */ 66 #define PMU_CS_WUF BIT(0) /*!< wakeup flag */ 67 #define PMU_CS_STBF BIT(1) /*!< standby flag */ 68 #define PMU_CS_LVDF BIT(2) /*!< low voltage detector status flag */ 69 #define PMU_CS_WUPEN BIT(8) /*!< wakeup pin enable */ 70 #define PMU_CS_LDOVSRF BIT(14) /*!< LDO voltage select ready flag */ 71 #define PMU_CS_HDRF BIT(16) /*!< high-driver ready flag */ 72 #define PMU_CS_HDSRF BIT(17) /*!< high-driver switch ready flag */ 73 #define PMU_CS_LDRF BITS(18,19) /*!< Low-driver mode ready flag */ 74 75 /* constants definitions */ 76 /* PMU low voltage detector threshold definitions */ 77 #define CTL_LVDT(regval) (BITS(5,7)&((uint32_t)(regval)<<5)) 78 #define PMU_LVDT_0 CTL_LVDT(0) /*!< voltage threshold is 2.1V */ 79 #define PMU_LVDT_1 CTL_LVDT(1) /*!< voltage threshold is 2.3V */ 80 #define PMU_LVDT_2 CTL_LVDT(2) /*!< voltage threshold is 2.4V */ 81 #define PMU_LVDT_3 CTL_LVDT(3) /*!< voltage threshold is 2.6V */ 82 #define PMU_LVDT_4 CTL_LVDT(4) /*!< voltage threshold is 2.7V */ 83 #define PMU_LVDT_5 CTL_LVDT(5) /*!< voltage threshold is 2.9V */ 84 #define PMU_LVDT_6 CTL_LVDT(6) /*!< voltage threshold is 3.0V */ 85 #define PMU_LVDT_7 CTL_LVDT(7) /*!< voltage threshold is 3.1V */ 86 87 /* PMU LDO output voltage select definitions */ 88 #define CTL_LDOVS(regval) (BITS(14,15)&((uint32_t)(regval)<<14)) 89 #define PMU_LDOVS_LOW CTL_LDOVS(1) /*!< LDO output voltage low mode */ 90 #define PMU_LDOVS_MID CTL_LDOVS(2) /*!< LDO output voltage mid mode */ 91 #define PMU_LDOVS_HIGH CTL_LDOVS(3) /*!< LDO output voltage high mode */ 92 93 /* PMU high-driver mode switch */ 94 #define CTL_HDS(regval) (BIT(17)&((uint32_t)(regval)<<17)) 95 #define PMU_HIGHDR_SWITCH_NONE CTL_HDS(0) /*!< no high-driver mode switch */ 96 #define PMU_HIGHDR_SWITCH_EN CTL_HDS(1) /*!< high-driver mode switch */ 97 98 /* PMU low-driver mode when use low power LDO */ 99 #define CTL_LDLP(regval) (BIT(10)&((uint32_t)(regval)<<10)) 100 #define PMU_NORMALDR_LOWPWR CTL_LDLP(0) /*!< normal driver when use low power LDO */ 101 #define PMU_LOWDR_LOWPWR CTL_LDLP(1) /*!< low-driver mode enabled when LDEN is 11 and use low power LDO */ 102 103 /* PMU low-driver mode when use normal power LDO */ 104 #define CTL_LDNP(regval) (BIT(11)&((uint32_t)(regval)<<11)) 105 #define PMU_NORMALDR_NORMALPWR CTL_LDNP(0) /*!< normal driver when use normal power LDO */ 106 #define PMU_LOWDR_NORMALPWR CTL_LDNP(1) /*!< low-driver mode enabled when LDEN is 11 and use normal power LDO */ 107 108 /* PMU low power mode ready flag definitions */ 109 #define CS_LDRF(regval) (BITS(18,19)&((uint32_t)(regval)<<18)) 110 #define PMU_LDRF_NORMAL CS_LDRF(0) /*!< normal driver in deep-sleep mode */ 111 #define PMU_LDRF_LOWDRIVER CS_LDRF(3) /*!< low-driver mode in deep-sleep mode */ 112 113 /* PMU flag definitions */ 114 #define PMU_FLAG_WAKEUP PMU_CS_WUF /*!< wakeup flag status */ 115 #define PMU_FLAG_STANDBY PMU_CS_STBF /*!< standby flag status */ 116 #define PMU_FLAG_LVD PMU_CS_LVDF /*!< lvd flag status */ 117 #define PMU_FLAG_LDOVSRF PMU_CS_LDOVSRF /*!< LDO voltage select ready flag */ 118 #define PMU_FLAG_HDRF PMU_CS_HDRF /*!< high-driver ready flag */ 119 #define PMU_FLAG_HDSRF PMU_CS_HDSRF /*!< high-driver switch ready flag */ 120 #define PMU_FLAG_LDRF PMU_CS_LDRF /*!< low-driver mode ready flag */ 121 122 /* PMU ldo definitions */ 123 #define PMU_LDO_NORMAL ((uint32_t)0x00000000U) /*!< LDO normal work when PMU enter deepsleep mode */ 124 #define PMU_LDO_LOWPOWER PMU_CTL_LDOLP /*!< LDO work at low power status when PMU enter deepsleep mode */ 125 126 /* PMU flag reset definitions */ 127 #define PMU_FLAG_RESET_WAKEUP ((uint8_t)0x00U) /*!< wakeup flag reset */ 128 #define PMU_FLAG_RESET_STANDBY ((uint8_t)0x01U) /*!< standby flag reset */ 129 130 /* PMU command constants definitions */ 131 #define WFI_CMD ((uint8_t)0x00U) /*!< use WFI command */ 132 #define WFE_CMD ((uint8_t)0x01U) /*!< use WFE command */ 133 134 /* function declarations */ 135 /* reset PMU registers */ 136 void pmu_deinit(void); 137 138 /* select low voltage detector threshold */ 139 void pmu_lvd_select(uint32_t lvdt_n); 140 /* select LDO output voltage */ 141 void pmu_ldo_output_select(uint32_t ldo_output); 142 /* disable PMU lvd */ 143 void pmu_lvd_disable(void); 144 145 /* functions of low-driver mode and high-driver mode in deep-sleep mode */ 146 /* switch high-driver mode */ 147 void pmu_highdriver_switch_select(uint32_t highdr_switch); 148 /* enable high-driver mode */ 149 void pmu_highdriver_mode_enable(void); 150 /* disable high-driver mode */ 151 void pmu_highdriver_mode_disable(void); 152 /* enable low-driver mode in deep-sleep mode */ 153 void pmu_lowdriver_mode_enable(void); 154 /* disable low-driver mode in deep-sleep mode */ 155 void pmu_lowdriver_mode_disable(void); 156 /* in deep-sleep mode, driver mode when use low power LDO */ 157 void pmu_lowpower_driver_config(uint32_t mode); 158 /* in deep-sleep mode, driver mode when use normal power LDO */ 159 void pmu_normalpower_driver_config(uint32_t mode); 160 161 /* set PMU mode */ 162 /* PMU work at sleep mode */ 163 void pmu_to_sleepmode(uint8_t sleepmodecmd); 164 /* PMU work at deepsleep mode */ 165 void pmu_to_deepsleepmode(uint32_t ldo, uint8_t deepsleepmodecmd); 166 /* PMU work at standby mode */ 167 void pmu_to_standbymode(uint8_t standbymodecmd); 168 /* enable PMU wakeup pin */ 169 void pmu_wakeup_pin_enable(void); 170 /* disable PMU wakeup pin */ 171 void pmu_wakeup_pin_disable(void); 172 173 /* backup related functions */ 174 /* enable backup domain write */ 175 void pmu_backup_write_enable(void); 176 /* disable backup domain write */ 177 void pmu_backup_write_disable(void); 178 179 /* flag functions */ 180 /* clear flag bit */ 181 void pmu_flag_clear(uint32_t flag_reset); 182 /* get flag state */ 183 FlagStatus pmu_flag_get(uint32_t flag); 184 185 #endif /* GD32F403_PMU_H */ 186
