1 /*!
2 \file gd32a50x_pmu.c
3 \brief PMU driver
4
5 \version 2022-01-30, V1.0.0, firmware for GD32A50x
6 */
7
8 /*
9 Copyright (c) 2022, GigaDevice Semiconductor Inc.
10
11 Redistribution and use in source and binary forms, with or without modification,
12 are permitted provided that the following conditions are met:
13
14 1. Redistributions of source code must retain the above copyright notice, this
15 list of conditions and the following disclaimer.
16 2. Redistributions in binary form must reproduce the above copyright notice,
17 this list of conditions and the following disclaimer in the documentation
18 and/or other materials provided with the distribution.
19 3. Neither the name of the copyright holder nor the names of its contributors
20 may be used to endorse or promote products derived from this software without
21 specific prior written permission.
22
23 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
25 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
26 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
27 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
28 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
29 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
31 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
32 OF SUCH DAMAGE.
33 */
34
35 #include "gd32a50x_pmu.h"
36
37 /*!
38 \brief reset PMU register
39 \param[in] none
40 \param[out] none
41 \retval none
42 */
pmu_deinit(void)43 void pmu_deinit(void)
44 {
45 /* reset PMU */
46 rcu_periph_reset_enable(RCU_PMURST);
47 rcu_periph_reset_disable(RCU_PMURST);
48 }
49
50 /*!
51 \brief select low voltage detector threshold
52 \param[in] lvdt_n:
53 only one parameter can be selected which is shown as below:
54 \arg PMU_LVDT_0: voltage threshold is 2.9V
55 \arg PMU_LVDT_1: voltage threshold is 3.1V
56 \arg PMU_LVDT_2: voltage threshold is 3.3V
57 \arg PMU_LVDT_3: voltage threshold is 3.5V
58 \arg PMU_LVDT_4: voltage threshold is 4.0V
59 \arg PMU_LVDT_5: voltage threshold is 4.2V
60 \arg PMU_LVDT_6: voltage threshold is 4.4V
61 \arg PMU_LVDT_7: voltage threshold is 4.6V
62 \param[out] none
63 \retval none
64 */
pmu_lvd_select(uint32_t lvdt_n)65 void pmu_lvd_select(uint32_t lvdt_n)
66 {
67 /* disable LVD */
68 PMU_CTL &= ~PMU_CTL_LVDEN;
69 /* clear LVDT bits */
70 PMU_CTL &= ~PMU_CTL_LVDT;
71 /* set LVDT bits according to lvdt_n */
72 PMU_CTL |= lvdt_n;
73 /* enable LVD */
74 PMU_CTL |= PMU_CTL_LVDEN;
75 }
76
77 /*!
78 \brief disable PMU lvd
79 \param[in] none
80 \param[out] none
81 \retval none
82 */
pmu_lvd_disable(void)83 void pmu_lvd_disable(void)
84 {
85 /* disable LVD */
86 PMU_CTL &= ~PMU_CTL_LVDEN;
87 }
88
89 /*!
90 \brief select over voltage detector threshold
91 \param[in] ovdt_n:
92 only one parameter can be selected which is shown as below:
93 \arg PMU_OVDT_0: voltage threshold is 5.0V
94 \arg PMU_OVDT_1: voltage threshold is 5.5V
95 \param[out] none
96 \retval none
97 */
pmu_ovd_select(uint32_t ovdt_n)98 void pmu_ovd_select(uint32_t ovdt_n)
99 {
100 /* disable OVD */
101 PMU_CTL &= ~PMU_CTL_OVDEN;
102 /* clear OVDT bits */
103 PMU_CTL &= ~PMU_CTL_OVDT;
104 /* set OVDT bits according to ovdt_n */
105 PMU_CTL |= ovdt_n;
106 /* enable OVD */
107 PMU_CTL |= PMU_CTL_OVDEN;
108 }
109
110 /*!
111 \brief disable PMU ovd
112 \param[in] none
113 \param[out] none
114 \retval none
115 */
pmu_ovd_disable(void)116 void pmu_ovd_disable(void)
117 {
118 /* disable OVD */
119 PMU_CTL &= ~PMU_CTL_OVDEN;
120 }
121
122 /*!
123 \brief enable low-driver mode in deep-sleep mode
124 \param[in] none
125 \param[out] none
126 \retval none
127 */
pmu_lowdriver_mode_enable(void)128 void pmu_lowdriver_mode_enable(void)
129 {
130 PMU_CTL |= PMU_CTL_LDEN;
131 }
132
133 /*!
134 \brief disable low-driver mode in deep-sleep mode
135 \param[in] none
136 \param[out] none
137 \retval none
138 */
pmu_lowdriver_mode_disable(void)139 void pmu_lowdriver_mode_disable(void)
140 {
141 PMU_CTL &= ~PMU_CTL_LDEN;
142 }
143
144 /*!
145 \brief SRAM1 power off in deep-sleep mode
146 \param[in] none
147 \param[out] none
148 \retval none
149 */
pmu_sram1_poweroff_mode_enable(void)150 void pmu_sram1_poweroff_mode_enable(void)
151 {
152 PMU_CTL |= PMU_CTL_SRAMSW1;
153 }
154
155 /*!
156 \brief SRAM1 power on in deep-sleep mode
157 \param[in] none
158 \param[out] none
159 \retval none
160 */
pmu_sram1_poweroff_mode_disable(void)161 void pmu_sram1_poweroff_mode_disable(void)
162 {
163 PMU_CTL &= ~PMU_CTL_SRAMSW1;
164 }
165
166 /*!
167 \brief SRAM2 power off in deep-sleep mode
168 \param[in] none
169 \param[out] none
170 \retval none
171 */
pmu_sram2_poweroff_mode_enable(void)172 void pmu_sram2_poweroff_mode_enable(void)
173 {
174 PMU_CTL |= PMU_CTL_SRAMSW2;
175 }
176
177 /*!
178 \brief SRAM2 power on in deep-sleep mode
179 \param[in] none
180 \param[out] none
181 \retval none
182 */
pmu_sram2_poweroff_mode_disable(void)183 void pmu_sram2_poweroff_mode_disable(void)
184 {
185 PMU_CTL &= ~PMU_CTL_SRAMSW2;
186 }
187
188 /*!
189 \brief PMU work in sleep mode
190 \param[in] sleepmodecmd:
191 only one parameter can be selected which is shown as below:
192 \arg WFI_CMD: use WFI command
193 \arg WFE_CMD: use WFE command
194 \param[out] none
195 \retval none
196 */
pmu_to_sleepmode(uint8_t sleepmodecmd)197 void pmu_to_sleepmode(uint8_t sleepmodecmd)
198 {
199 /* clear sleepdeep bit of Cortex-M33 system control register */
200 SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
201
202 /* select WFI or WFE command to enter sleep mode */
203 if(WFI_CMD == sleepmodecmd) {
204 __WFI();
205 } else {
206 __SEV();
207 __WFE();
208 __WFE();
209 }
210 }
211
212 /*!
213 \brief PMU work in deepsleep mode
214 \param[in] ldo:
215 only one parameter can be selected which is shown as below:
216 \arg PMU_LDO_NORMAL: LDO work in normal power mode when pmu enter deepsleep mode
217 \arg PMU_LDO_LOWPOWER: LDO work in low power mode when pmu enter deepsleep mode
218 \param[in] lowdrive:
219 only one parameter can be selected which is shown as below:
220 \arg PMU_LOWDRIVER_ENABLE: low-driver mode enable in deep-sleep mode
221 \arg PMU_LOWDRIVER_DISABLE: low-driver mode disable in deep-sleep mode
222 \param[in] deepsleepmodecmd:
223 only one parameter can be selected which is shown as below:
224 \arg WFI_CMD: use WFI command
225 \arg WFE_CMD: use WFE command
226 \param[out] none
227 \retval none
228 */
pmu_to_deepsleepmode(uint32_t ldo,uint32_t lowdrive,uint8_t deepsleepmodecmd)229 void pmu_to_deepsleepmode(uint32_t ldo, uint32_t lowdrive, uint8_t deepsleepmodecmd)
230 {
231 /* flash goto sleep mode when MCU enters deepsleep mode */
232 REG32(0x40022000) |= (uint32_t)(1<<14);
233
234 /* clear stbmod and ldolp bits */
235 PMU_CTL &= ~((uint32_t)(PMU_CTL_STBMOD | PMU_CTL_LDOLP | PMU_CTL_LDEN));
236
237 /* set ldolp bit according to pmu_ldo */
238 PMU_CTL |= (ldo | lowdrive);
239
240 /* set sleepdeep bit of Cortex-M33 system control register */
241 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
242
243 /* select WFI or WFE command to enter deepsleep mode */
244 if(WFI_CMD == deepsleepmodecmd) {
245 __WFI();
246 } else {
247 __SEV();
248 __WFE();
249 __WFE();
250 }
251
252 /* reset sleepdeep bit of Cortex-M33 system control register */
253 SCB->SCR &= ~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);
254 }
255
256 /*!
257 \brief pmu work in standby mode
258 \param[in] none
259 \param[out] none
260 \retval none
261 */
pmu_to_standbymode(void)262 void pmu_to_standbymode(void)
263 {
264 /* set stbmod bit */
265 PMU_CTL |= PMU_CTL_STBMOD;
266
267 /* reset wakeup flag */
268 PMU_CTL |= PMU_CTL_WURST;
269
270 /* set sleepdeep bit of Cortex-M33 system control register */
271 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
272
273 REG32(0xE000E010U) &= 0x00010004U;
274 REG32(0xE000E180U) = 0XFFFFFFF7U;
275 REG32(0xE000E184U) = 0XFFFFFFFFU;
276 REG32(0xE000E188U) = 0xFFFFFFFFU;
277
278 /* select WFI or WFE command to enter standby mode */
279 __WFI();
280 }
281
282 /*!
283 \brief enable wakeup pin
284 \param[in] wakeup_pin:
285 one or more parameters can be selected which are shown as below:
286 \arg PMU_WAKEUP_PIN0: WKUP Pin 0 (PA0)
287 \arg PMU_WAKEUP_PIN1: WKUP Pin 1 (PC13)
288 \param[out] none
289 \retval none
290 */
pmu_wakeup_pin_enable(uint32_t wakeup_pin)291 void pmu_wakeup_pin_enable(uint32_t wakeup_pin)
292 {
293 PMU_CS |= wakeup_pin;
294 }
295
296 /*!
297 \brief disable wakeup pin
298 \param[in] wakeup_pin:
299 one or more parameters can be selected which are shown as below:
300 \arg PMU_WAKEUP_PIN0: WKUP Pin 0 (PA0)
301 \arg PMU_WAKEUP_PIN1: WKUP Pin 1 (PC13)
302 \param[out] none
303 \retval none
304 */
pmu_wakeup_pin_disable(uint32_t wakeup_pin)305 void pmu_wakeup_pin_disable(uint32_t wakeup_pin)
306 {
307 PMU_CS &= ~(wakeup_pin);
308 }
309
310 /*!
311 \brief enable write access to the registers in backup domain
312 \param[in] none
313 \param[out] none
314 \retval none
315 */
pmu_backup_write_enable(void)316 void pmu_backup_write_enable(void)
317 {
318 PMU_CTL |= PMU_CTL_BKPWEN;
319 }
320
321 /*!
322 \brief disable write access to the registers in backup domain
323 \param[in] none
324 \param[out] none
325 \retval none
326 */
pmu_backup_write_disable(void)327 void pmu_backup_write_disable(void)
328 {
329 PMU_CTL &= ~PMU_CTL_BKPWEN;
330 }
331
332 /*!
333 \brief get flag state
334 \param[in] flag:
335 only one parameter can be selected which is shown as below:
336 \arg PMU_FLAG_WAKEUP: wakeup flag
337 \arg PMU_FLAG_STANDBY: standby flag
338 \arg PMU_FLAG_LVD: lvd flag
339 \arg PMU_FLAG_OVD: ovd flag
340 \param[out] none
341 \retval FlagStatus: SET or RESET
342 */
pmu_flag_get(uint32_t flag)343 FlagStatus pmu_flag_get(uint32_t flag)
344 {
345 if(0U != (PMU_CS & flag)) {
346 return SET;
347 } else {
348 return RESET;
349 }
350 }
351
352 /*!
353 \brief clear flag bit
354 \param[in] flag:
355 only one parameter can be selected which is shown as below:
356 \arg PMU_FLAG_RESET_WAKEUP: reset wakeup flag
357 \arg PMU_FLAG_RESET_STANDBY: reset standby flag
358 \param[out] none
359 \retval none
360 */
pmu_flag_clear(uint32_t flag)361 void pmu_flag_clear(uint32_t flag)
362 {
363 switch(flag) {
364 case PMU_FLAG_RESET_WAKEUP:
365 /* reset wakeup flag */
366 PMU_CTL |= PMU_CTL_WURST;
367 break;
368 case PMU_FLAG_RESET_STANDBY:
369 /* reset standby flag */
370 PMU_CTL |= PMU_CTL_STBRST;
371 break;
372 default:
373 break;
374 }
375 }
376
