1 /*! 2 \file gd32f4xx_pmu.h 3 \brief definitions for the PMU 4 5 \version 2016-08-15, V1.0.0, firmware for GD32F4xx 6 \version 2018-12-12, V2.0.0, firmware for GD32F4xx 7 \version 2020-09-30, V2.1.0, firmware for GD32F4xx 8 \version 2022-03-09, V3.0.0, firmware for GD32F4xx 9 */ 10 11 /* 12 Copyright (c) 2022, GigaDevice Semiconductor Inc. 13 14 Redistribution and use in source and binary forms, with or without modification, 15 are permitted provided that the following conditions are met: 16 17 1. Redistributions of source code must retain the above copyright notice, this 18 list of conditions and the following disclaimer. 19 2. Redistributions in binary form must reproduce the above copyright notice, 20 this list of conditions and the following disclaimer in the documentation 21 and/or other materials provided with the distribution. 22 3. Neither the name of the copyright holder nor the names of its contributors 23 may be used to endorse or promote products derived from this software without 24 specific prior written permission. 25 26 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 27 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 28 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 29 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 30 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 31 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 32 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 33 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 35 OF SUCH DAMAGE. 36 */ 37 38 39 #ifndef GD32F4XX_PMU_H 40 #define GD32F4XX_PMU_H 41 42 #include "gd32f4xx.h" 43 44 /* PMU definitions */ 45 #define PMU PMU_BASE /*!< PMU base address */ 46 47 /* registers definitions */ 48 #define PMU_CTL REG32((PMU) + 0x00000000U) /*!< PMU control register */ 49 #define PMU_CS REG32((PMU) + 0x00000004U) /*!< PMU control and status register */ 50 51 /* bits definitions */ 52 /* PMU_CTL */ 53 #define PMU_CTL_LDOLP BIT(0) /*!< LDO low power mode */ 54 #define PMU_CTL_STBMOD BIT(1) /*!< standby mode */ 55 #define PMU_CTL_WURST BIT(2) /*!< wakeup flag reset */ 56 #define PMU_CTL_STBRST BIT(3) /*!< standby flag reset */ 57 #define PMU_CTL_LVDEN BIT(4) /*!< low voltage detector enable */ 58 #define PMU_CTL_LVDT BITS(5,7) /*!< low voltage detector threshold */ 59 #define PMU_CTL_BKPWEN BIT(8) /*!< backup domain write enable */ 60 #define PMU_CTL_LDLP BIT(10) /*!< low-driver mode when use low power LDO */ 61 #define PMU_CTL_LDNP BIT(11) /*!< low-driver mode when use normal power LDO */ 62 #define PMU_CTL_LDOVS BITS(14,15) /*!< LDO output voltage select */ 63 #define PMU_CTL_HDEN BIT(16) /*!< high-driver mode enable */ 64 #define PMU_CTL_HDS BIT(17) /*!< high-driver mode switch */ 65 #define PMU_CTL_LDEN BITS(18,19) /*!< low-driver mode enable in deep-sleep mode */ 66 67 /* PMU_CS */ 68 #define PMU_CS_WUF BIT(0) /*!< wakeup flag */ 69 #define PMU_CS_STBF BIT(1) /*!< standby flag */ 70 #define PMU_CS_LVDF BIT(2) /*!< low voltage detector status flag */ 71 #define PMU_CS_BLDORF BIT(3) /*!< backup SRAM LDO ready flag */ 72 #define PMU_CS_WUPEN BIT(8) /*!< wakeup pin enable */ 73 #define PMU_CS_BLDOON BIT(9) /*!< backup SRAM LDO on */ 74 #define PMU_CS_LDOVSRF BIT(14) /*!< LDO voltage select ready flag */ 75 #define PMU_CS_HDRF BIT(16) /*!< high-driver ready flag */ 76 #define PMU_CS_HDSRF BIT(17) /*!< high-driver switch ready flag */ 77 #define PMU_CS_LDRF BITS(18,19) /*!< low-driver mode ready flag */ 78 79 /* constants definitions */ 80 /* PMU ldo definitions */ 81 #define PMU_LDO_NORMAL ((uint32_t)0x00000000U) /*!< LDO normal work when PMU enter deep-sleep mode */ 82 #define PMU_LDO_LOWPOWER PMU_CTL_LDOLP /*!< LDO work at low power status when PMU enter deep-sleep mode */ 83 84 /* PMU low voltage detector threshold definitions */ 85 #define CTL_LVDT(regval) (BITS(5,7)&((uint32_t)(regval)<<5)) 86 #define PMU_LVDT_0 CTL_LVDT(0) /*!< voltage threshold is 2.1V */ 87 #define PMU_LVDT_1 CTL_LVDT(1) /*!< voltage threshold is 2.3V */ 88 #define PMU_LVDT_2 CTL_LVDT(2) /*!< voltage threshold is 2.4V */ 89 #define PMU_LVDT_3 CTL_LVDT(3) /*!< voltage threshold is 2.6V */ 90 #define PMU_LVDT_4 CTL_LVDT(4) /*!< voltage threshold is 2.7V */ 91 #define PMU_LVDT_5 CTL_LVDT(5) /*!< voltage threshold is 2.9V */ 92 #define PMU_LVDT_6 CTL_LVDT(6) /*!< voltage threshold is 3.0V */ 93 #define PMU_LVDT_7 CTL_LVDT(7) /*!< voltage threshold is 3.1V */ 94 95 /* PMU low-driver mode when use low power LDO */ 96 #define CTL_LDLP(regval) (BIT(10)&((uint32_t)(regval)<<10)) 97 #define PMU_NORMALDR_LOWPWR CTL_LDLP(0) /*!< normal driver when use low power LDO */ 98 #define PMU_LOWDR_LOWPWR CTL_LDLP(1) /*!< low-driver mode enabled when LDEN is 11 and use low power LDO */ 99 100 /* PMU low-driver mode when use normal power LDO */ 101 #define CTL_LDNP(regval) (BIT(11)&((uint32_t)(regval)<<11)) 102 #define PMU_NORMALDR_NORMALPWR CTL_LDNP(0) /*!< normal driver when use normal power LDO */ 103 #define PMU_LOWDR_NORMALPWR CTL_LDNP(1) /*!< low-driver mode enabled when LDEN is 11 and use normal power LDO */ 104 105 /* PMU LDO output voltage select definitions */ 106 #define CTL_LDOVS(regval) (BITS(14,15)&((uint32_t)(regval)<<14)) 107 #define PMU_LDOVS_LOW CTL_LDOVS(1) /*!< LDO output voltage low mode */ 108 #define PMU_LDOVS_MID CTL_LDOVS(2) /*!< LDO output voltage mid mode */ 109 #define PMU_LDOVS_HIGH CTL_LDOVS(3) /*!< LDO output voltage high mode */ 110 111 112 /* PMU high-driver mode switch */ 113 #define CTL_HDS(regval) (BIT(17)&((uint32_t)(regval)<<17)) 114 #define PMU_HIGHDR_SWITCH_NONE CTL_HDS(0) /*!< no high-driver mode switch */ 115 #define PMU_HIGHDR_SWITCH_EN CTL_HDS(1) /*!< high-driver mode switch */ 116 117 /* PMU low-driver mode enable in deep-sleep mode */ 118 #define CTL_LDEN(regval) (BITS(18,19)&((uint32_t)(regval)<<18)) 119 #define PMU_LOWDRIVER_DISABLE CTL_LDEN(0) /*!< low-driver mode disable in deep-sleep mode */ 120 #define PMU_LOWDRIVER_ENABLE CTL_LDEN(3) /*!< low-driver mode enable in deep-sleep mode */ 121 122 /* PMU backup SRAM LDO on or off */ 123 #define CS_BLDOON(regval) (BIT(9)&((uint32_t)(regval)<<9)) 124 #define PMU_BLDOON_OFF CS_BLDOON(0) /*!< backup SRAM LDO off */ 125 #define PMU_BLDOON_ON CS_BLDOON(1) /*!< the backup SRAM LDO on */ 126 127 /* PMU low power mode ready flag definitions */ 128 #define CS_LDRF(regval) (BITS(18,19)&((uint32_t)(regval)<<18)) 129 #define PMU_LDRF_NORMAL CS_LDRF(0) /*!< normal driver in deep-sleep mode */ 130 #define PMU_LDRF_LOWDRIVER CS_LDRF(3) /*!< low-driver mode in deep-sleep mode */ 131 132 /* PMU flag definitions */ 133 #define PMU_FLAG_WAKEUP PMU_CS_WUF /*!< wakeup flag status */ 134 #define PMU_FLAG_STANDBY PMU_CS_STBF /*!< standby flag status */ 135 #define PMU_FLAG_LVD PMU_CS_LVDF /*!< lvd flag status */ 136 #define PMU_FLAG_BLDORF PMU_CS_BLDORF /*!< backup SRAM LDO ready flag */ 137 #define PMU_FLAG_LDOVSRF PMU_CS_LDOVSRF /*!< LDO voltage select ready flag */ 138 #define PMU_FLAG_HDRF PMU_CS_HDRF /*!< high-driver ready flag */ 139 #define PMU_FLAG_HDSRF PMU_CS_HDSRF /*!< high-driver switch ready flag */ 140 #define PMU_FLAG_LDRF PMU_CS_LDRF /*!< low-driver mode ready flag */ 141 142 /* PMU flag reset definitions */ 143 #define PMU_FLAG_RESET_WAKEUP ((uint8_t)0x00U) /*!< wakeup flag reset */ 144 #define PMU_FLAG_RESET_STANDBY ((uint8_t)0x01U) /*!< standby flag reset */ 145 146 /* PMU command constants definitions */ 147 #define WFI_CMD ((uint8_t)0x00U) /*!< use WFI command */ 148 #define WFE_CMD ((uint8_t)0x01U) /*!< use WFE command */ 149 150 /* function declarations */ 151 /* reset PMU registers */ 152 void pmu_deinit(void); 153 154 /* LVD functions */ 155 /* select low voltage detector threshold */ 156 void pmu_lvd_select(uint32_t lvdt_n); 157 /* disable PMU lvd */ 158 void pmu_lvd_disable(void); 159 160 /* LDO functions */ 161 /* select LDO output voltage */ 162 void pmu_ldo_output_select(uint32_t ldo_output); 163 164 /* functions of low-driver mode and high-driver mode */ 165 /* enable high-driver mode */ 166 void pmu_highdriver_mode_enable(void); 167 /* disable high-driver mode */ 168 void pmu_highdriver_mode_disable(void); 169 /* switch high-driver mode */ 170 void pmu_highdriver_switch_select(uint32_t highdr_switch); 171 /* enable low-driver mode in deep-sleep */ 172 void pmu_lowdriver_mode_enable(void); 173 /* disable low-driver mode in deep-sleep */ 174 void pmu_lowdriver_mode_disable(void); 175 /* in deep-sleep mode, driver mode when use low power LDO */ 176 void pmu_lowpower_driver_config(uint32_t mode); 177 /* in deep-sleep mode, driver mode when use normal power LDO */ 178 void pmu_normalpower_driver_config(uint32_t mode); 179 180 /* set PMU mode */ 181 /* PMU work in sleep mode */ 182 void pmu_to_sleepmode(uint8_t sleepmodecmd); 183 /* PMU work in deepsleep mode */ 184 void pmu_to_deepsleepmode(uint32_t ldo, uint32_t lowdrive, uint8_t deepsleepmodecmd); 185 /* PMU work in standby mode */ 186 void pmu_to_standbymode(uint8_t standbymodecmd); 187 /* enable PMU wakeup pin */ 188 void pmu_wakeup_pin_enable(void); 189 /* disable PMU wakeup pin */ 190 void pmu_wakeup_pin_disable(void); 191 192 /* backup related functions */ 193 /* backup SRAM LDO on */ 194 void pmu_backup_ldo_config(uint32_t bkp_ldo); 195 /* enable write access to the registers in backup domain */ 196 void pmu_backup_write_enable(void); 197 /* disable write access to the registers in backup domain */ 198 void pmu_backup_write_disable(void); 199 200 /* flag functions */ 201 /* get flag state */ 202 FlagStatus pmu_flag_get(uint32_t flag); 203 /* clear flag bit */ 204 void pmu_flag_clear(uint32_t flag); 205 206 #endif /* GD32F4XX_PMU_H */ 207
