1 /*! 2 \file gd32e10x_pmu.h 3 \brief definitions for the PMU 4 5 \version 2017-12-26, V1.0.0, firmware for GD32E10x 6 \version 2020-09-30, V1.1.0, firmware for GD32E10x 7 \version 2020-12-31, V1.2.0, firmware for GD32E10x 8 \version 2022-06-30, V1.3.0, firmware for GD32E10x 9 */ 10 11 /* 12 Copyright (c) 2022, GigaDevice Semiconductor Inc. 13 14 Redistribution and use in source and binary forms, with or without modification, 15 are permitted provided that the following conditions are met: 16 17 1. Redistributions of source code must retain the above copyright notice, this 18 list of conditions and the following disclaimer. 19 2. Redistributions in binary form must reproduce the above copyright notice, 20 this list of conditions and the following disclaimer in the documentation 21 and/or other materials provided with the distribution. 22 3. Neither the name of the copyright holder nor the names of its contributors 23 may be used to endorse or promote products derived from this software without 24 specific prior written permission. 25 26 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 27 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 28 WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 29 IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 30 INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 31 NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 32 PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 33 WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 34 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 35 OF SUCH DAMAGE. 36 */ 37 38 #ifndef GD32E10X_PMU_H 39 #define GD32E10X_PMU_H 40 41 #include "gd32e10x.h" 42 43 /* PMU definitions */ 44 #define PMU PMU_BASE /*!< PMU base address */ 45 46 /* registers definitions */ 47 #define PMU_CTL REG32((PMU) + 0x00U) /*!< PMU control register */ 48 #define PMU_CS REG32((PMU) + 0x04U) /*!< PMU control and status register */ 49 50 /* bits definitions */ 51 /* PMU_CTL */ 52 #define PMU_CTL_LDOLP BIT(0) /*!< LDO low power mode */ 53 #define PMU_CTL_STBMOD BIT(1) /*!< standby mode */ 54 #define PMU_CTL_WURST BIT(2) /*!< wakeup flag reset */ 55 #define PMU_CTL_STBRST BIT(3) /*!< standby flag reset */ 56 #define PMU_CTL_LVDEN BIT(4) /*!< low voltage detector enable */ 57 #define PMU_CTL_LVDT BITS(5,7) /*!< low voltage detector threshold */ 58 #define PMU_CTL_BKPWEN BIT(8) /*!< backup domain write enable */ 59 #define PMU_CTL_LDOVS BITS(14,15) /*!< LDO output voltage select */ 60 61 /* PMU_CS */ 62 #define PMU_CS_WUF BIT(0) /*!< wakeup flag */ 63 #define PMU_CS_STBF BIT(1) /*!< standby flag */ 64 #define PMU_CS_LVDF BIT(2) /*!< low voltage detector status flag */ 65 #define PMU_CS_WUPEN BIT(8) /*!< wakeup pin enable */ 66 67 /* constants definitions */ 68 /* PMU low voltage detector threshold definitions */ 69 #define CTL_LVDT(regval) (BITS(5,7)&((uint32_t)(regval)<<5)) 70 #define PMU_LVDT_0 CTL_LVDT(0) /*!< voltage threshold is 2.1V */ 71 #define PMU_LVDT_1 CTL_LVDT(1) /*!< voltage threshold is 2.3V */ 72 #define PMU_LVDT_2 CTL_LVDT(2) /*!< voltage threshold is 2.4V */ 73 #define PMU_LVDT_3 CTL_LVDT(3) /*!< voltage threshold is 2.6V */ 74 #define PMU_LVDT_4 CTL_LVDT(4) /*!< voltage threshold is 2.7V */ 75 #define PMU_LVDT_5 CTL_LVDT(5) /*!< voltage threshold is 2.9V */ 76 #define PMU_LVDT_6 CTL_LVDT(6) /*!< voltage threshold is 3.0V */ 77 #define PMU_LVDT_7 CTL_LVDT(7) /*!< voltage threshold is 3.1V */ 78 79 /* PMU LDO output voltage select definitions */ 80 #define CTL_LDOVS(regval) (BITS(14,15)&((uint32_t)(regval)<<14)) 81 #define PMU_LDOVS_NORMAL CTL_LDOVS(1) /*!< LDO output voltage select normal mode */ 82 #define PMU_LDOVS_LOW CTL_LDOVS(3) /*!< LDO output voltage select low mode */ 83 84 /* PMU ldo definitions */ 85 #define PMU_LDO_NORMAL ((uint32_t)0x00000000U) /*!< LDO normal work when PMU enter deepsleep mode */ 86 #define PMU_LDO_LOWPOWER PMU_CTL_LDOLP /*!< LDO work at low power status when PMU enter deepsleep mode */ 87 88 /* PMU flag definitions */ 89 #define PMU_FLAG_WAKEUP PMU_CS_WUF /*!< wakeup flag status */ 90 #define PMU_FLAG_STANDBY PMU_CS_STBF /*!< standby flag status */ 91 #define PMU_FLAG_LVD PMU_CS_LVDF /*!< lvd flag status */ 92 93 /* PMU flag reset definitions */ 94 #define PMU_FLAG_RESET_WAKEUP ((uint8_t)0x00U) /*!< wakeup flag reset */ 95 #define PMU_FLAG_RESET_STANDBY ((uint8_t)0x01U) /*!< standby flag reset */ 96 97 /* PMU command constants definitions */ 98 #define WFI_CMD ((uint8_t)0x00U) /*!< use WFI command */ 99 #define WFE_CMD ((uint8_t)0x01U) /*!< use WFE command */ 100 101 /* function declarations */ 102 /* reset PMU registers */ 103 void pmu_deinit(void); 104 105 /* select low voltage detector threshold */ 106 void pmu_lvd_select(uint32_t lvdt_n); 107 /* select LDO output voltage */ 108 void pmu_ldo_output_select(uint32_t ldo_output); 109 /* disable PMU lvd */ 110 void pmu_lvd_disable(void); 111 112 /* set PMU mode */ 113 /* PMU work at sleep mode */ 114 void pmu_to_sleepmode(uint8_t sleepmodecmd); 115 /* PMU work at deepsleep mode */ 116 void pmu_to_deepsleepmode(uint32_t ldo, uint8_t deepsleepmodecmd); 117 /* PMU work at standby mode */ 118 void pmu_to_standbymode(void); 119 120 /* wakeup pin related functions */ 121 /* enable PMU wakeup pin */ 122 void pmu_wakeup_pin_enable(void); 123 /* disable PMU wakeup pin */ 124 void pmu_wakeup_pin_disable(void); 125 126 /* backup related functions */ 127 /* enable write access to the registers in backup domain */ 128 void pmu_backup_write_enable(void); 129 /* disable write access to the registers in backup domain */ 130 void pmu_backup_write_disable(void); 131 132 /* flag functions */ 133 /* get flag state */ 134 FlagStatus pmu_flag_get(uint32_t flag); 135 /* clear flag bit */ 136 void pmu_flag_clear(uint32_t flag); 137 138 #endif /* GD32E10X_PMU_H */ 139
