Searched refs:b0 (Results 1 – 14 of 14) sorted by relevance
14 … Set this bit to disable Icache = False R/W (0b0)15 … Set this bit to disable Dcache = False R/W (0b0)16 … Set this bit to disable CAN function = False R/W (0b0)17 … Disable app cpu = False R/W (0b0)18 …CK0) Disable direct boot mode = False R/W (0b0)20 …K0) Set default power supply for GPIO33-GPIO37; set wh = VDD3P3_CPU R/W (0b0)32 … Flash ECC mode in ROM = 16to18 byte R/W (0b0)33 … SPI flash type = 4 data lines R/W (0b0)35 …) Set 1 to enable ECC for flash boot = False R/W (0b0)36 …LOCK0) Set this bit to force ROM code to send a resume co = False R/W (0b0)[all …]
34 … Set this bit to disable Icache = False R/W (0b0)35 … Set this bit to disable Dcache = False R/W (0b0)36 … Set this bit to disable the TWAI Controller functi = False R/W (0b0)38 …K0) Disables capability to Remap RAM to ROM address sp = False R/W (0b0)40 …(BLOCK0) Set this bit to disable Legacy SPI boot mode = False R/W (0b0)41 …BLOCK0) Selects the default UART for printing boot message = UART0 R/W (0b0)44 …K0) Set default power supply for GPIO33-GPIO37; set wh = VDD3P3_CPU R/W (0b0)55 … SPI flash type = 4 data lines R/W (0b0)56 …LOCK0) If set; forces ROM code to send an SPI flash resum = False R/W (0b0)62 …N_MAJOR (BLOCK0) Disables check of wafer version major = False R/W (0b0)[all …]
14 …K0) Represents whether power glitch function is enable = False R/W (0b0)16 … Represents whether TWAI function is disabled or en = False R/W (0b0)28 …CK0) Represents whether direct boot mode is disabled or = False R/W (0b0)34 … Represents whether the hysteresis function of corr = False R/W (0b0)42 …K0) HP system power source select. 0:LDO. 1: DCDC = False R/W (0b0)43 …) Select dcdc vset use efuse_dcdc_vset = False R/W (0b0)44 … Set this bit to disable super-watchdog = False R/W (0b0)53 … The type of interfaced flash. 0: four data lines; = False R/W (0b0)56 …) Set this bit to enable ecc for flash boot = False R/W (0b0)61 …LOCK0) Represents whether ROM code is forced to send a re = False R/W (0b0)[all …]
17 …CK0): Disables APP CPU = False R/W (0b0)18 … Disables Bluetooth = False R/W (0b0)19 … Disables cache = False R/W (0b0)20 …LOCK0): If set alongside EFUSE_RD_CHIP_CPU_FREQ_RATED; the = False R/W (0b0)25 …LOCK0): BLOCK3 partially served for ADC calibration data = False R/W (0b0)34 …LOCK0): = False R/W (0b0)35 …OCK0): Disable flash cache in UART bootloader = False R/W (0b0)43 …LOCK0): Chip package identifier #4bit = False R/W (0b0)54 …): Disable JTAG = False R/W (0b0)63 …LOCK0): Disable UART download mode. Valid for ESP32 V3 and = False R/W (0b0)[all …]
14 …LOCK0) Represents whether pad of uart and sdio is swapped = False R/W (0b0)16 … Represents whether icache is disabled or enabled. = False R/W (0b0)18 … Represents whether TWAI function is disabled or en = False R/W (0b0)20 …CK0) Represents whether direct boot mode is disabled or = False R/W (0b0)33 …LOCK0) Represents whether ROM code is forced to send a re = False R/W (0b0)41 …N_MAJOR (BLOCK0) Disables check of wafer version major = False R/W (0b0)42 …MAJOR (BLOCK0) Disables check of blk version major = False R/W (0b0)52 …CK0) Represents whether the selection between usb_to_jt = False R/W (0b0)59 …) Represents whether JTAG is disabled in the hard wa = False R/W (0b0)70 …(BLOCK0) Represents whether icache is disabled or enabled i = False R/W (0b0)[all …]
14 … Represents whether icache is disabled or enabled. = False R/W (0b0)16 …K0) Represents whether power glitch function is enable = False R/W (0b0)18 … Represents whether TWAI function is disabled or en = False R/W (0b0)20 …CK0) Represents whether direct boot mode is disabled or = False R/W (0b0)35 …LOCK0) Represents whether ROM code is forced to send a re = False R/W (0b0)45 …N_MAJOR (BLOCK1) Disables check of wafer version major = False R/W (0b0)51 …MAJOR (BLOCK2) Disables check of blk version major = False R/W (0b0)54 …CK0) Set this bit to enable selection between usb_to_jt = False R/W (0b0)60 …) Represents whether JTAG is disabled in the hard wa = False R/W (0b0)71 …BLOCK0) Represents whether the function that forces chip i = False R/W (0b0)[all …]
15 …CK0) This bit set means disable direct_boot mode = False R/W (0b0)18 …LOCK0) Set this bit to force ROM code to send a resume co = False R/W (0b0)26 …N_MAJOR (BLOCK0) Disables check of wafer version major = False R/W (0b0)27 …MAJOR (BLOCK0) Disables check of blk version major = False R/W (0b0)35 …) Set this bit to disable pad jtag = False R/W (0b0)38 …CK0) True if MAC_CUSTOM is burned = False R/W (0b0)45 …(BLOCK0) The bit be set to disable icache in download mode = False R/W (0b0)46 …ENCRYPT (BLOCK0) The bit be set to disable manual encryption = False R/W (0b0)49 … Flash encryption key length = 128 bits key R/W (0b0)50 …LOCK0) Set this bit to disable download mode (boot_mode[3 = False R/W (0b0)[all …]
32 … Set this bit to disable Icache = False R/W (0b0)33 … Set this bit to disable CAN function = False R/W (0b0)34 …CK0) Disable direct boot mode = False R/W (0b0)47 …LOCK0) Set this bit to force ROM code to send a resume co = False R/W (0b0)51 …N_MAJOR (BLOCK0) Disables check of wafer version major = False R/W (0b0)52 …MAJOR (BLOCK0) Disables check of blk version major = False R/W (0b0)56 …HI (BLOCK1) WAFER_VERSION_MINOR most significant bit = False R/W (0b0)68 …) Set this bit to disable JTAG in the hard way. JTAG = False R/W (0b0)78 …(BLOCK0) Set this bit to disable Icache in download mode (b = False R/W (0b0)80 …BLOCK0) Set this bit to disable the function that forces c = False R/W (0b0)[all …]
184 #define BLE_MESH_MODEL_OP_1(b0) (b0) argument185 #define BLE_MESH_MODEL_OP_2(b0, b1) (((b0) << 8) | (b1)) argument186 #define BLE_MESH_MODEL_OP_3(b0, cid) ((((b0) << 16) | 0xc00000) | (cid)) argument
267 #define ESP_BLE_MESH_MODEL_OP_1(b0) (b0) argument268 #define ESP_BLE_MESH_MODEL_OP_2(b0, b1) (((b0) << 8) | (b1)) argument269 #define ESP_BLE_MESH_MODEL_OP_3(b0, cid) ((((b0) << 16) | 0xC00000) | (cid)) argument
35 … - 'DIS_USB_JTAG' (Disables USB JTAG. JTAG access via pads is controlled separately) 0b0 -> 0b136 - 'VDD_SPI_AS_GPIO' (Set this bit to vdd spi pin function as gpio) 0b0 -> 0b1
18 …0)[FAIL:1] Selects RTC WDT timeout threshold at startup = False R/W (0b0)
135 … Secure boot V1 is enabled for bootloader image = False R/W (0b0)
101 … Flash encryption key length = 128 bits key R/W (0b0)
