1.. code-block:: none 2 3 > espefuse.py -p PORT summary 4 5 Connecting.... 6 Detecting chip type... ESP32-S2 7 8 === Run "summary" command === 9 EFUSE_NAME (Block) Description = [Meaningful Value] [Readable/Writeable] (Hex Value) 10 ---------------------------------------------------------------------------------------- 11 Calibration fuses: 12 ADC_CALIB (BLOCK2) 4 bit of ADC calibration = 0 R/W (0x0) 13 TEMP_CALIB (BLOCK2) Temperature calibration data = 3.2 R/W (0b000100000) 14 RTCCALIB_V1IDX_A10H (BLOCK2) = 55 R/W (0x37) 15 RTCCALIB_V1IDX_A11H (BLOCK2) = 51 R/W (0x33) 16 RTCCALIB_V1IDX_A12H (BLOCK2) = 52 R/W (0x34) 17 RTCCALIB_V1IDX_A13H (BLOCK2) = 53 R/W (0x35) 18 RTCCALIB_V1IDX_A20H (BLOCK2) = 56 R/W (0x38) 19 RTCCALIB_V1IDX_A21H (BLOCK2) = 55 R/W (0x37) 20 RTCCALIB_V1IDX_A22H (BLOCK2) = 55 R/W (0x37) 21 RTCCALIB_V1IDX_A23H (BLOCK2) = 59 R/W (0x3b) 22 RTCCALIB_V1IDX_A10L (BLOCK2) = 25 R/W (0b011001) 23 RTCCALIB_V1IDX_A11L (BLOCK2) = 17 R/W (0b010001) 24 RTCCALIB_V1IDX_A12L (BLOCK2) = 14 R/W (0b001110) 25 RTCCALIB_V1IDX_A13L (BLOCK2) = 7 R/W (0b000111) 26 RTCCALIB_V1IDX_A20L (BLOCK2) = 19 R/W (0b010011) 27 RTCCALIB_V1IDX_A21L (BLOCK2) = 14 R/W (0b001110) 28 RTCCALIB_V1IDX_A22L (BLOCK2) = 10 R/W (0b001010) 29 RTCCALIB_V1IDX_A23L (BLOCK2) = 6 R/W (0b000110) 30 31 Config fuses: 32 WR_DIS (BLOCK0) Disable programming of individual eFuses = 0 R/W (0x00000000) 33 RD_DIS (BLOCK0) Disable reading from BlOCK4-10 = 0 R/W (0b0000000) 34 DIS_ICACHE (BLOCK0) Set this bit to disable Icache = False R/W (0b0) 35 DIS_DCACHE (BLOCK0) Set this bit to disable Dcache = False R/W (0b0) 36 DIS_TWAI (BLOCK0) Set this bit to disable the TWAI Controller functi = False R/W (0b0) 37 on 38 DIS_BOOT_REMAP (BLOCK0) Disables capability to Remap RAM to ROM address sp = False R/W (0b0) 39 ace 40 DIS_LEGACY_SPI_BOOT (BLOCK0) Set this bit to disable Legacy SPI boot mode = False R/W (0b0) 41 UART_PRINT_CHANNEL (BLOCK0) Selects the default UART for printing boot message = UART0 R/W (0b0) 42 s 43 UART_PRINT_CONTROL (BLOCK0) Set the default UART boot message output mode = Enable R/W (0b00) 44 PIN_POWER_SELECTION (BLOCK0) Set default power supply for GPIO33-GPIO37; set wh = VDD3P3_CPU R/W (0b0) 45 en SPI flash is initialized 46 BLOCK_USR_DATA (BLOCK3) User data 47 = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W 48 BLOCK_SYS_DATA2 (BLOCK10) System data part 2 (reserved) 49 = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W 50 51 Flash fuses: 52 FLASH_TPUW (BLOCK0) Configures flash startup delay after SoC power-up; = 0 R/W (0x0) 53 in unit of (ms/2). When the value is 15; delay is 54 7.5 ms 55 FLASH_TYPE (BLOCK0) SPI flash type = 4 data lines R/W (0b0) 56 FORCE_SEND_RESUME (BLOCK0) If set; forces ROM code to send an SPI flash resum = False R/W (0b0) 57 e command during SPI boot 58 FLASH_VERSION (BLOCK1) Flash version = 1 R/W (0x1) 59 60 Identity fuses: 61 BLOCK0_VERSION (BLOCK0) BLOCK0 efuse version = 0 R/W (0b00) 62 DISABLE_WAFER_VERSION_MAJOR (BLOCK0) Disables check of wafer version major = False R/W (0b0) 63 DISABLE_BLK_VERSION_MAJOR (BLOCK0) Disables check of blk version major = False R/W (0b0) 64 WAFER_VERSION_MAJOR (BLOCK1) WAFER_VERSION_MAJOR = 0 R/W (0b00) 65 WAFER_VERSION_MINOR_HI (BLOCK1) WAFER_VERSION_MINOR most significant bit = False R/W (0b0) 66 BLK_VERSION_MAJOR (BLOCK1) BLK_VERSION_MAJOR = 0 R/W (0b00) 67 PSRAM_VERSION (BLOCK1) PSRAM version = 0 R/W (0x0) 68 PKG_VERSION (BLOCK1) Package version = 0 R/W (0x0) 69 WAFER_VERSION_MINOR_LO (BLOCK1) WAFER_VERSION_MINOR least significant bits = 0 R/W (0b000) 70 OPTIONAL_UNIQUE_ID (BLOCK2) Optional unique 128-bit ID 71 = d9 8f 05 d0 86 77 53 db 80 6c ee 40 df 5d ef b0 R/W 72 BLK_VERSION_MINOR (BLOCK2) BLK_VERSION_MINOR of BLOCK2 = ADC calib V1 R/W (0b001) 73 WAFER_VERSION_MINOR (BLOCK0) calc WAFER VERSION MINOR = WAFER_VERSION_MINOR_HI = 0 R/W (0x0) 74 << 3 + WAFER_VERSION_MINOR_LO (read only) 75 76 Jtag fuses: 77 SOFT_DIS_JTAG (BLOCK0) Software disables JTAG. When software disabled; JT = False R/W (0b0) 78 AG can be activated temporarily by HMAC peripheral 79 HARD_DIS_JTAG (BLOCK0) Hardware disables JTAG permanently = False R/W (0b0) 80 81 Mac fuses: 82 MAC (BLOCK1) MAC address 83 = 7c:df:a1:00:48:34 (OK) R/W 84 CUSTOM_MAC (BLOCK3) Custom MAC 85 = 00:00:00:00:00:00 (OK) R/W 86 87 Security fuses: 88 DIS_DOWNLOAD_ICACHE (BLOCK0) Disables Icache when SoC is in Download mode = False R/W (0b0) 89 DIS_DOWNLOAD_DCACHE (BLOCK0) Disables Dcache when SoC is in Download mode = False R/W (0b0) 90 DIS_FORCE_DOWNLOAD (BLOCK0) Set this bit to disable the function that forces c = False R/W (0b0) 91 hip into download mode 92 DIS_DOWNLOAD_MANUAL_ENCRYPT (BLOCK0) Disables flash encryption when in download boot mo = False R/W (0b0) 93 des 94 SPI_BOOT_CRYPT_CNT (BLOCK0) Enables flash encryption when 1 or 3 bits are set = Disable R/W (0b000) 95 and disabled otherwise 96 SECURE_BOOT_KEY_REVOKE0 (BLOCK0) Revoke 1st secure boot key = False R/W (0b0) 97 SECURE_BOOT_KEY_REVOKE1 (BLOCK0) Revoke 2nd secure boot key = False R/W (0b0) 98 SECURE_BOOT_KEY_REVOKE2 (BLOCK0) Revoke 3rd secure boot key = False R/W (0b0) 99 KEY_PURPOSE_0 (BLOCK0) Purpose of KEY0 = USER R/W (0x0) 100 KEY_PURPOSE_1 (BLOCK0) Purpose of KEY1 = USER R/W (0x0) 101 KEY_PURPOSE_2 (BLOCK0) Purpose of KEY2 = USER R/W (0x0) 102 KEY_PURPOSE_3 (BLOCK0) Purpose of KEY3 = USER R/W (0x0) 103 KEY_PURPOSE_4 (BLOCK0) Purpose of KEY4 = USER R/W (0x0) 104 KEY_PURPOSE_5 (BLOCK0) Purpose of KEY5 = USER R/W (0x0) 105 SECURE_BOOT_EN (BLOCK0) Set this bit to enable secure boot = False R/W (0b0) 106 SECURE_BOOT_AGGRESSIVE_REVOKE (BLOCK0) Set this bit to enable aggressive secure boot key = False R/W (0b0) 107 revocation mode 108 DIS_DOWNLOAD_MODE (BLOCK0) Set this bit to disable all download boot modes = False R/W (0b0) 109 ENABLE_SECURITY_DOWNLOAD (BLOCK0) Set this bit to enable secure UART download mode ( = False R/W (0b0) 110 read/write flash only) 111 SECURE_VERSION (BLOCK0) Secure version (used by ESP-IDF anti-rollback feat = 0 R/W (0x0000) 112 ure) 113 BLOCK_KEY0 (BLOCK4) 114 Purpose: USER 115 Key0 or user data 116 = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W 117 BLOCK_KEY1 (BLOCK5) 118 Purpose: USER 119 Key1 or user data 120 = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W 121 BLOCK_KEY2 (BLOCK6) 122 Purpose: USER 123 Key2 or user data 124 = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W 125 BLOCK_KEY3 (BLOCK7) 126 Purpose: USER 127 Key3 or user data 128 = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W 129 BLOCK_KEY4 (BLOCK8) 130 Purpose: USER 131 Key4 or user data 132 = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W 133 BLOCK_KEY5 (BLOCK9) 134 Purpose: USER 135 Key5 or user data 136 = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W 137 138 Spi Pad fuses: 139 SPI_PAD_CONFIG_CLK (BLOCK1) SPI_PAD_configure CLK = 0 R/W (0b000000) 140 SPI_PAD_CONFIG_Q (BLOCK1) SPI_PAD_configure Q(D1) = 0 R/W (0b000000) 141 SPI_PAD_CONFIG_D (BLOCK1) SPI_PAD_configure D(D0) = 0 R/W (0b000000) 142 SPI_PAD_CONFIG_CS (BLOCK1) SPI_PAD_configure CS = 0 R/W (0b000000) 143 SPI_PAD_CONFIG_HD (BLOCK1) SPI_PAD_configure HD(D3) = 0 R/W (0b000000) 144 SPI_PAD_CONFIG_WP (BLOCK1) SPI_PAD_configure WP(D2) = 0 R/W (0b000000) 145 SPI_PAD_CONFIG_DQS (BLOCK1) SPI_PAD_configure DQS = 0 R/W (0b000000) 146 SPI_PAD_CONFIG_D4 (BLOCK1) SPI_PAD_configure D4 = 0 R/W (0b000000) 147 SPI_PAD_CONFIG_D5 (BLOCK1) SPI_PAD_configure D5 = 0 R/W (0b000000) 148 SPI_PAD_CONFIG_D6 (BLOCK1) SPI_PAD_configure D6 = 0 R/W (0b000000) 149 SPI_PAD_CONFIG_D7 (BLOCK1) SPI_PAD_configure D7 = 0 R/W (0b000000) 150 151 Usb fuses: 152 DIS_USB (BLOCK0) Set this bit to disable USB OTG function = False R/W (0b0) 153 USB_EXCHG_PINS (BLOCK0) Set this bit to exchange USB D+ and D- pins = False R/W (0b0) 154 USB_EXT_PHY_ENABLE (BLOCK0) Set this bit to enable external USB PHY = False R/W (0b0) 155 USB_FORCE_NOPERSIST (BLOCK0) If set; forces USB BVALID to 1 = False R/W (0b0) 156 DIS_USB_DOWNLOAD_MODE (BLOCK0) Set this bit to disable use of USB OTG in UART dow = False R/W (0b0) 157 nload boot mode 158 159 Vdd fuses: 160 VDD_SPI_XPD (BLOCK0) If VDD_SPI_FORCE is 1; this value determines if th = False R/W (0b0) 161 e VDD_SPI regulator is powered on 162 VDD_SPI_TIEH (BLOCK0) If VDD_SPI_FORCE is 1; determines VDD_SPI voltage 163 = VDD_SPI connects to 1.8 V LDO R/W (0b0) 164 VDD_SPI_FORCE (BLOCK0) Set this bit to use XPD_VDD_PSI_REG and VDD_SPI_TI = False R/W (0b0) 165 EH to configure VDD_SPI LDO 166 167 Wdt fuses: 168 WDT_DELAY_SEL (BLOCK0) RTC watchdog timeout threshold; in unit of slow cl = 40000 R/W (0b00) 169 ock cycle 170 171 Flash voltage (VDD_SPI) determined by GPIO45 on reset (GPIO45=High: VDD_SPI pin is powered from internal 1.8V LDO 172 GPIO45=Low or NC: VDD_SPI pin is powered directly from VDD3P3_RTC_IO via resistor Rspi. Typically this voltage is 3.3 V). 173
