Home
last modified time | relevance | path

Searched refs:WRITE_PERI_REG (Results 1 – 25 of 55) sorted by relevance

123

/hal_espressif-latest/components/esp_system/port/soc/esp32c2/
Dsystem_internal.c79 WRITE_PERI_REG(GPIO_FUNC0_IN_SEL_CFG_REG, 0x30); in esp_restart_noos()
80 WRITE_PERI_REG(GPIO_FUNC1_IN_SEL_CFG_REG, 0x30); in esp_restart_noos()
81 WRITE_PERI_REG(GPIO_FUNC2_IN_SEL_CFG_REG, 0x30); in esp_restart_noos()
82 WRITE_PERI_REG(GPIO_FUNC3_IN_SEL_CFG_REG, 0x30); in esp_restart_noos()
83 WRITE_PERI_REG(GPIO_FUNC4_IN_SEL_CFG_REG, 0x30); in esp_restart_noos()
84 WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30); in esp_restart_noos()
/hal_espressif-latest/components/esp_system/port/soc/esp32c3/
Dsystem_internal.c92 WRITE_PERI_REG(GPIO_FUNC0_IN_SEL_CFG_REG, 0x30); in esp_restart_noos()
93 WRITE_PERI_REG(GPIO_FUNC1_IN_SEL_CFG_REG, 0x30); in esp_restart_noos()
94 WRITE_PERI_REG(GPIO_FUNC2_IN_SEL_CFG_REG, 0x30); in esp_restart_noos()
95 WRITE_PERI_REG(GPIO_FUNC3_IN_SEL_CFG_REG, 0x30); in esp_restart_noos()
96 WRITE_PERI_REG(GPIO_FUNC4_IN_SEL_CFG_REG, 0x30); in esp_restart_noos()
97 WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30); in esp_restart_noos()
/hal_espressif-latest/components/esp_system/port/soc/esp32s2/
Dsystem_internal.c102 WRITE_PERI_REG(GPIO_FUNC0_IN_SEL_CFG_REG, 0x30); in esp_restart_noos()
103 WRITE_PERI_REG(GPIO_FUNC1_IN_SEL_CFG_REG, 0x30); in esp_restart_noos()
104 WRITE_PERI_REG(GPIO_FUNC2_IN_SEL_CFG_REG, 0x30); in esp_restart_noos()
105 WRITE_PERI_REG(GPIO_FUNC3_IN_SEL_CFG_REG, 0x30); in esp_restart_noos()
106 WRITE_PERI_REG(GPIO_FUNC4_IN_SEL_CFG_REG, 0x30); in esp_restart_noos()
107 WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30); in esp_restart_noos()
/hal_espressif-latest/components/esp_system/port/soc/esp32/
Dsystem_internal.c114 WRITE_PERI_REG(GPIO_FUNC0_IN_SEL_CFG_REG, 0x30); in esp_restart_noos()
115 WRITE_PERI_REG(GPIO_FUNC1_IN_SEL_CFG_REG, 0x30); in esp_restart_noos()
116 WRITE_PERI_REG(GPIO_FUNC2_IN_SEL_CFG_REG, 0x30); in esp_restart_noos()
117 WRITE_PERI_REG(GPIO_FUNC3_IN_SEL_CFG_REG, 0x30); in esp_restart_noos()
118 WRITE_PERI_REG(GPIO_FUNC4_IN_SEL_CFG_REG, 0x30); in esp_restart_noos()
119 WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30); in esp_restart_noos()
/hal_espressif-latest/components/esp_system/port/soc/esp32s3/
Dsystem_internal.c121 WRITE_PERI_REG(GPIO_FUNC0_IN_SEL_CFG_REG, 0x30); in esp_restart_noos()
122 WRITE_PERI_REG(GPIO_FUNC1_IN_SEL_CFG_REG, 0x30); in esp_restart_noos()
123 WRITE_PERI_REG(GPIO_FUNC2_IN_SEL_CFG_REG, 0x30); in esp_restart_noos()
124 WRITE_PERI_REG(GPIO_FUNC3_IN_SEL_CFG_REG, 0x30); in esp_restart_noos()
125 WRITE_PERI_REG(GPIO_FUNC4_IN_SEL_CFG_REG, 0x30); in esp_restart_noos()
126 WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30); in esp_restart_noos()
/hal_espressif-latest/components/esp_system/
Dcrosscore_int.c65 WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_0_REG, 0); in esp_crosscore_isr()
67 WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_1_REG, 0); in esp_crosscore_isr()
70 WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_0_REG, 0); in esp_crosscore_isr()
146 WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_0_REG, SYSTEM_CPU_INTR_FROM_CPU_0); in esp_crosscore_int_send()
148 WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_1_REG, SYSTEM_CPU_INTR_FROM_CPU_1); in esp_crosscore_int_send()
151 WRITE_PERI_REG(SYSTEM_CPU_INTR_FROM_CPU_0_REG, SYSTEM_CPU_INTR_FROM_CPU_0); in esp_crosscore_int_send()
/hal_espressif-latest/components/esp_rom/patches/
Desp_rom_spiflash.c116 WRITE_PERI_REG(PERIPHS_SPI_FLASH_CMD, SPI_FLASH_CE); in esp_rom_spiflash_erase_chip_internal()
137 WRITE_PERI_REG(PERIPHS_SPI_FLASH_ADDR, addr & 0xffffff); in esp_rom_spiflash_erase_sector_internal()
138 WRITE_PERI_REG(PERIPHS_SPI_FLASH_CMD, SPI_FLASH_SE); in esp_rom_spiflash_erase_sector_internal()
153 WRITE_PERI_REG(PERIPHS_SPI_FLASH_ADDR, addr & 0xffffff); in esp_rom_spiflash_erase_block_internal()
154 WRITE_PERI_REG(PERIPHS_SPI_FLASH_CMD, SPI_FLASH_BE); in esp_rom_spiflash_erase_block_internal()
192 …WRITE_PERI_REG(PERIPHS_SPI_FLASH_ADDR, (temp_addr & 0xffffff) | ( ESP_ROM_SPIFLASH_BUFF_BYTE_WRITE… in esp_rom_spiflash_program_page_internal()
195 WRITE_PERI_REG(PERIPHS_SPI_FLASH_C0 + i * 4, *addr_source++); in esp_rom_spiflash_program_page_internal()
200 …WRITE_PERI_REG(PERIPHS_SPI_FLASH_ADDR, (temp_addr & 0xffffff) | (temp_bl << ESP_ROM_SPIFLASH_BYTES… in esp_rom_spiflash_program_page_internal()
204 WRITE_PERI_REG(PERIPHS_SPI_FLASH_C0 + i * 4, *addr_source++); in esp_rom_spiflash_program_page_internal()
209 WRITE_PERI_REG(PERIPHS_SPI_FLASH_CMD, SPI_FLASH_PP); in esp_rom_spiflash_program_page_internal()
[all …]
/hal_espressif-latest/zephyr/esp32/src/
Dsoc_random.c43 WRITE_PERI_REG(SYSCON_SARADC_SAR2_PATT_TAB1_REG, 0xADADADAD); in soc_random_enable()
44 WRITE_PERI_REG(SYSCON_SARADC_SAR2_PATT_TAB2_REG, 0xADADADAD); in soc_random_enable()
45 WRITE_PERI_REG(SYSCON_SARADC_SAR2_PATT_TAB3_REG, 0xADADADAD); in soc_random_enable()
46 WRITE_PERI_REG(SYSCON_SARADC_SAR2_PATT_TAB4_REG, 0xADADADAD); in soc_random_enable()
/hal_espressif-latest/components/bootloader_support/src/
Dbootloader_random_esp32.c53 WRITE_PERI_REG(SYSCON_SARADC_SAR2_PATT_TAB1_REG, 0xADADADAD); in bootloader_random_enable()
54 WRITE_PERI_REG(SYSCON_SARADC_SAR2_PATT_TAB2_REG, 0xADADADAD); in bootloader_random_enable()
55 WRITE_PERI_REG(SYSCON_SARADC_SAR2_PATT_TAB3_REG, 0xADADADAD); in bootloader_random_enable()
56 WRITE_PERI_REG(SYSCON_SARADC_SAR2_PATT_TAB4_REG, 0xADADADAD); in bootloader_random_enable()
Dbootloader_random_esp32s2.c56 …WRITE_PERI_REG(APB_SARADC_SAR1_PATT_TAB1_REG,0xafffffff); // set adc1 channel & bitwidth & atten in bootloader_random_enable()
59 WRITE_PERI_REG(APB_SARADC_SAR2_PATT_TAB1_REG,0xafffffff); //set adc2 channel & bitwidth & atten in bootloader_random_enable()
Dbootloader_random_esp32s3.c50 …WRITE_PERI_REG(APB_SARADC_SAR2_PATT_TAB1_REG,0xafffff); // Test internal voltage if the channel in… in bootloader_random_enable()
52 …WRITE_PERI_REG(APB_SARADC_SAR1_PATT_TAB1_REG,0xafffff); // Test internal voltage if the channel in… in bootloader_random_enable()
/hal_espressif-latest/components/soc/esp32c2/include/soc/
Dsoc.h107 #define WRITE_PERI_REG(addr, val) do { … macro
113 …WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask)))); …
118 …WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask))); …
133 …WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & (bit_map))<<(shift))…
/hal_espressif-latest/components/soc/esp32c6/include/soc/
Dsoc.h101 #define WRITE_PERI_REG(addr, val) do { … macro
107 …WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask)))); …
112 …WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask))); …
127 …WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & (bit_map))<<(shift))…
/hal_espressif-latest/components/soc/esp32s2/include/soc/
Dsoc.h105 #define WRITE_PERI_REG(addr, val) do { … macro
111 …WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask)))); …
116 …WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask))); …
131 …WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & (bit_map))<<(shift))…
/hal_espressif-latest/components/soc/esp32h2/include/soc/
Dsoc.h99 #define WRITE_PERI_REG(addr, val) do { … macro
105 …WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask)))); …
110 …WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask))); …
125 …WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & (bit_map))<<(shift))…
/hal_espressif-latest/components/soc/esp32c3/include/soc/
Dsoc.h99 #define WRITE_PERI_REG(addr, val) do { … macro
105 …WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask)))); …
110 …WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask))); …
125 …WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & (bit_map))<<(shift))…
/hal_espressif-latest/components/esp_hw_support/
Drtc_wdt.c20 WRITE_PERI_REG(RTC_CNTL_WDTWPROTECT_REG, RTC_CNTL_WDT_WKEY_VALUE); in rtc_wdt_protect_off()
25 WRITE_PERI_REG(RTC_CNTL_WDTWPROTECT_REG, 0); in rtc_wdt_protect_on()
96 WRITE_PERI_REG(get_addr_reg(stage), timeout); in rtc_wdt_set_time()
/hal_espressif-latest/components/soc/esp32/include/soc/
Dsoc.h112 #define WRITE_PERI_REG(addr, val) do { … macro
113 …ASSERT_IF_DPORT_REG((addr), WRITE_PERI_REG); …
120 …WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask)))); …
126 …WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask))); …
144 …WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & (bit_map))<<(shift))…
/hal_espressif-latest/components/soc/esp32s3/include/soc/
Dsoc.h114 #define WRITE_PERI_REG(addr, val) do { … macro
120 …WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask)))); …
125 …WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask))); …
140 …WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & (bit_map))<<(shift))…
/hal_espressif-latest/zephyr/esp32s2/src/
Dsoc_random.c51 WRITE_PERI_REG(APB_SARADC_SAR1_PATT_TAB1_REG, 0xafffffff); in soc_random_enable()
54 WRITE_PERI_REG(APB_SARADC_SAR2_PATT_TAB1_REG, 0xafffffff); in soc_random_enable()
/hal_espressif-latest/components/hal/esp32c2/include/hal/
Drtc_cntl_ll.h21 WRITE_PERI_REG(RTC_CNTL_SLP_TIMER0_REG, t & UINT32_MAX); in rtc_cntl_ll_set_wakeup_timer()
22 WRITE_PERI_REG(RTC_CNTL_SLP_TIMER1_REG, t >> 32); in rtc_cntl_ll_set_wakeup_timer()
/hal_espressif-latest/components/esp_hw_support/port/esp32h2/
Dpmu_init.c223 WRITE_PERI_REG(PMU_POWER_PD_TOP_CNTL_REG, 0); in pmu_init()
224 WRITE_PERI_REG(PMU_POWER_PD_HPAON_CNTL_REG, 0); in pmu_init()
225 WRITE_PERI_REG(PMU_POWER_PD_HPCPU_CNTL_REG, 0); in pmu_init()
226 WRITE_PERI_REG(PMU_POWER_PD_HPPERI_RESERVE_REG, 0); in pmu_init()
227 WRITE_PERI_REG(PMU_POWER_PD_HPWIFI_CNTL_REG, 0); in pmu_init()
228 WRITE_PERI_REG(PMU_POWER_PD_LPPERI_CNTL_REG, 0); in pmu_init()
/hal_espressif-latest/components/hal/esp32c3/include/hal/
Drtc_cntl_ll.h21 WRITE_PERI_REG(RTC_CNTL_SLP_TIMER0_REG, t & UINT32_MAX); in rtc_cntl_ll_set_wakeup_timer()
22 WRITE_PERI_REG(RTC_CNTL_SLP_TIMER1_REG, t >> 32); in rtc_cntl_ll_set_wakeup_timer()
/hal_espressif-latest/zephyr/esp32s3/src/
Dsoc_random.c56 WRITE_PERI_REG(APB_SARADC_SAR2_PATT_TAB1_REG, in soc_random_enable()
60 WRITE_PERI_REG(APB_SARADC_SAR1_PATT_TAB1_REG, in soc_random_enable()
/hal_espressif-latest/components/hal/esp32s2/include/hal/
Drtc_cntl_ll.h21 WRITE_PERI_REG(RTC_CNTL_SLP_TIMER0_REG, t & UINT32_MAX); in rtc_cntl_ll_set_wakeup_timer()
22 WRITE_PERI_REG(RTC_CNTL_SLP_TIMER1_REG, t >> 32); in rtc_cntl_ll_set_wakeup_timer()

123