1 /*
2 * SPDX-FileCopyrightText: 2018-2021 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <string.h>
8 #include "sdkconfig.h"
9 #include "esp_system.h"
10 #include "esp_private/system_internal.h"
11 #include "esp_attr.h"
12 #include "esp_efuse.h"
13 #include "esp_log.h"
14 #include "riscv/rv_utils.h"
15 #include "esp_rom_uart.h"
16 #include "soc/gpio_reg.h"
17 #include "soc/timer_group_reg.h"
18 #include "esp_cpu.h"
19 #include "soc/rtc.h"
20 #include "esp_private/rtc_clk.h"
21 #include "soc/rtc_periph.h"
22 #include "soc/syscon_reg.h"
23 #include "soc/system_reg.h"
24 #include "soc/uart_reg.h"
25 #include "hal/wdt_hal.h"
26 // #include "esp_private/cache_err_int.h"
27
28 #include "esp32c3/rom/cache.h"
29 #include "esp32c3/rom/rtc.h"
30
esp_system_reset_modules_on_exit(void)31 void IRAM_ATTR esp_system_reset_modules_on_exit(void)
32 {
33 // Flush any data left in UART FIFOs before reset the UART peripheral
34 esp_rom_uart_tx_wait_idle(0);
35 esp_rom_uart_tx_wait_idle(1);
36
37 // Reset wifi/bluetooth/ethernet/sdio (bb/mac)
38 SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG,
39 SYSTEM_WIFIBB_RST | SYSTEM_FE_RST | SYSTEM_WIFIMAC_RST | SYSTEM_SDIO_RST |
40 SYSTEM_EMAC_RST | SYSTEM_MACPWR_RST | SYSTEM_BTBB_RST | SYSTEM_BTBB_REG_RST |
41 SYSTEM_RW_BTMAC_RST | SYSTEM_RW_BTLP_RST | SYSTEM_RW_BTMAC_REG_RST | SYSTEM_RW_BTLP_REG_RST);
42 REG_WRITE(SYSTEM_CORE_RST_EN_REG, 0);
43
44 // Reset uart0 core first, then reset apb side.
45 // rom will clear this bit, as well as SYSTEM_UART_RST
46 SET_PERI_REG_MASK(UART_CLK_CONF_REG(0), UART_RST_CORE_M);
47
48 // Reset timer/spi/uart
49 SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG,
50 SYSTEM_TIMERS_RST | SYSTEM_SPI01_RST | SYSTEM_UART_RST | SYSTEM_SYSTIMER_RST);
51 REG_WRITE(SYSTEM_PERIP_RST_EN0_REG, 0);
52 // Reset dma
53 SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, SYSTEM_DMA_RST);
54 REG_WRITE(SYSTEM_PERIP_RST_EN1_REG, 0);
55 }
56
57 /* "inner" restart function for after RTOS, interrupts & anything else on this
58 * core are already stopped. Stalls other core, resets hardware,
59 * triggers restart.
60 */
esp_restart_noos(void)61 void IRAM_ATTR esp_restart_noos(void)
62 {
63 // Disable interrupts
64 rv_utils_intr_global_disable();
65 // Enable RTC watchdog for 1 second
66 wdt_hal_context_t rtc_wdt_ctx;
67 wdt_hal_init(&rtc_wdt_ctx, WDT_RWDT, 0, false);
68 uint32_t stage_timeout_ticks = (uint32_t)(1000ULL * rtc_clk_slow_freq_get_hz() / 1000ULL);
69 wdt_hal_write_protect_disable(&rtc_wdt_ctx);
70 wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE0, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_SYSTEM);
71 wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE1, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_RTC);
72 //Enable flash boot mode so that flash booting after restart is protected by the RTC WDT.
73 wdt_hal_set_flashboot_en(&rtc_wdt_ctx, true);
74 wdt_hal_write_protect_enable(&rtc_wdt_ctx);
75
76 // Disable TG0/TG1 watchdogs
77 wdt_hal_context_t wdt0_context = {.inst = WDT_MWDT0, .mwdt_dev = &TIMERG0};
78 wdt_hal_write_protect_disable(&wdt0_context);
79 wdt_hal_disable(&wdt0_context);
80 wdt_hal_write_protect_enable(&wdt0_context);
81
82 wdt_hal_context_t wdt1_context = {.inst = WDT_MWDT1, .mwdt_dev = &TIMERG1};
83 wdt_hal_write_protect_disable(&wdt1_context);
84 wdt_hal_disable(&wdt1_context);
85 wdt_hal_write_protect_enable(&wdt1_context);
86
87 // Disable cache
88 Cache_Disable_ICache();
89
90 // 2nd stage bootloader reconfigures SPI flash signals.
91 // Reset them to the defaults expected by ROM.
92 WRITE_PERI_REG(GPIO_FUNC0_IN_SEL_CFG_REG, 0x30);
93 WRITE_PERI_REG(GPIO_FUNC1_IN_SEL_CFG_REG, 0x30);
94 WRITE_PERI_REG(GPIO_FUNC2_IN_SEL_CFG_REG, 0x30);
95 WRITE_PERI_REG(GPIO_FUNC3_IN_SEL_CFG_REG, 0x30);
96 WRITE_PERI_REG(GPIO_FUNC4_IN_SEL_CFG_REG, 0x30);
97 WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30);
98
99 esp_system_reset_modules_on_exit();
100
101 // Set CPU back to XTAL source, same as hard reset, but keep BBPLL on so that USB Serial JTAG can log at 1st stage bootloader.
102 #if !CONFIG_IDF_ENV_FPGA
103 rtc_clk_cpu_set_to_default_config();
104 #endif
105
106 // Reset CPU
107 esp_rom_software_reset_cpu(0);
108 while (true) {
109 ;
110 }
111 }
112
