1 
2 /*
3  * SPDX-FileCopyrightText: 2018-2022 Espressif Systems (Shanghai) CO LTD
4  *
5  * SPDX-License-Identifier: Apache-2.0
6  */
7 
8 #include <zephyr/kernel.h>
9 
10 #include <string.h>
11 #include "sdkconfig.h"
12 #include "esp_system.h"
13 #include "esp_private/system_internal.h"
14 #include "esp_attr.h"
15 #include "esp_log.h"
16 #include "esp_rom_uart.h"
17 #include "soc/dport_reg.h"
18 #include "soc/gpio_reg.h"
19 #include "soc/timer_group_reg.h"
20 #include "esp_cpu.h"
21 #include "soc/rtc.h"
22 #include "esp_private/rtc_clk.h"
23 #include "soc/syscon_reg.h"
24 #include "soc/rtc_periph.h"
25 #include "hal/wdt_hal.h"
26 
27 #include "esp32s3/rom/cache.h"
28 #include "esp32s3/rom/rtc.h"
29 
30 #define ALIGN_DOWN(val, align)  ((val) & ~((align) - 1))
31 
32 extern int _bss_end;
33 
esp_system_reset_modules_on_exit(void)34 void IRAM_ATTR esp_system_reset_modules_on_exit(void)
35 {
36     // Flush any data left in UART FIFOs before reset the UART peripheral
37     esp_rom_uart_tx_wait_idle(0);
38     esp_rom_uart_tx_wait_idle(1);
39     esp_rom_uart_tx_wait_idle(2);
40 
41     // Reset wifi/bluetooth/ethernet/sdio (bb/mac)
42     SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG,
43                       SYSTEM_WIFIBB_RST | SYSTEM_FE_RST | SYSTEM_WIFIMAC_RST | SYSTEM_SDIO_RST |
44                       SYSTEM_EMAC_RST | SYSTEM_MACPWR_RST | SYSTEM_BTBB_RST | SYSTEM_BTBB_REG_RST |
45                       SYSTEM_RW_BTMAC_RST | SYSTEM_RW_BTLP_RST | SYSTEM_RW_BTMAC_REG_RST | SYSTEM_RW_BTLP_REG_RST);
46     REG_WRITE(SYSTEM_CORE_RST_EN_REG, 0);
47 
48     // Reset timer, systimer, spi, uart, mcpwm
49     SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG,
50                       SYSTEM_TIMERS_RST | SYSTEM_SPI01_RST | SYSTEM_UART_RST | SYSTEM_SYSTIMER_RST |
51                       SYSTEM_PWM0_RST | SYSTEM_PWM1_RST);
52     REG_WRITE(SYSTEM_PERIP_RST_EN0_REG, 0);
53 
54     // Reset dma
55     SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, SYSTEM_DMA_RST);
56     REG_WRITE(SYSTEM_PERIP_RST_EN1_REG, 0);
57 
58     SET_PERI_REG_MASK(SYSTEM_EDMA_CTRL_REG, SYSTEM_EDMA_RESET);
59     CLEAR_PERI_REG_MASK(SYSTEM_EDMA_CTRL_REG, SYSTEM_EDMA_RESET);
60 }
61 
62 /* "inner" restart function for after RTOS, interrupts & anything else on this
63  * core are already stopped. Stalls other core, resets hardware,
64  * triggers restart.
65 */
esp_restart_noos(void)66 void IRAM_ATTR esp_restart_noos(void)
67 {
68     // Disable interrupts
69     z_xt_ints_off(0xFFFFFFFF);
70 
71     // Enable RTC watchdog for 1 second
72     wdt_hal_context_t rtc_wdt_ctx;
73     wdt_hal_init(&rtc_wdt_ctx, WDT_RWDT, 0, false);
74     uint32_t stage_timeout_ticks = (uint32_t)(1000ULL * rtc_clk_slow_freq_get_hz() / 1000ULL);
75     wdt_hal_write_protect_disable(&rtc_wdt_ctx);
76     wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE0, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_SYSTEM);
77     wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE1, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_RTC);
78     //Enable flash boot mode so that flash booting after restart is protected by the RTC WDT.
79     wdt_hal_set_flashboot_en(&rtc_wdt_ctx, true);
80     wdt_hal_write_protect_enable(&rtc_wdt_ctx);
81 
82 
83     // Disable TG0/TG1 watchdogs
84     wdt_hal_context_t wdt0_context = {.inst = WDT_MWDT0, .mwdt_dev = &TIMERG0};
85     wdt_hal_write_protect_disable(&wdt0_context);
86     wdt_hal_disable(&wdt0_context);
87     wdt_hal_write_protect_enable(&wdt0_context);
88 
89     wdt_hal_context_t wdt1_context = {.inst = WDT_MWDT1, .mwdt_dev = &TIMERG1};
90     wdt_hal_write_protect_disable(&wdt1_context);
91     wdt_hal_disable(&wdt1_context);
92     wdt_hal_write_protect_enable(&wdt1_context);
93 
94 #ifdef CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY
95     if (esp_ptr_external_ram(esp_cpu_get_sp())) {
96         // If stack_addr is from External Memory (CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY is used)
97         // then need to switch SP to Internal Memory otherwise
98         // we will get the "Cache disabled but cached memory region accessed" error after Cache_Read_Disable.
99         uint32_t new_sp = ALIGN_DOWN(_bss_end, 16);
100         SET_STACK(new_sp);
101     }
102 #endif
103 
104     // Disable cache
105     Cache_Disable_ICache();
106     Cache_Disable_DCache();
107 
108     // Reset and stall the other CPU.
109     // CPU must be reset before stalling, in case it was running a s32c1i
110     // instruction. This would cause memory pool to be locked by arbiter
111     // to the stalled CPU, preventing current CPU from accessing this pool.
112     const uint32_t core_id = esp_cpu_get_core_id();
113 #if !CONFIG_FREERTOS_UNICORE
114     const uint32_t other_core_id = (core_id == 0) ? 1 : 0;
115     esp_rom_software_reset_cpu(other_core_id);
116     esp_cpu_stall(other_core_id);
117 #endif
118 
119     // 2nd stage bootloader reconfigures SPI flash signals.
120     // Reset them to the defaults expected by ROM.
121     WRITE_PERI_REG(GPIO_FUNC0_IN_SEL_CFG_REG, 0x30);
122     WRITE_PERI_REG(GPIO_FUNC1_IN_SEL_CFG_REG, 0x30);
123     WRITE_PERI_REG(GPIO_FUNC2_IN_SEL_CFG_REG, 0x30);
124     WRITE_PERI_REG(GPIO_FUNC3_IN_SEL_CFG_REG, 0x30);
125     WRITE_PERI_REG(GPIO_FUNC4_IN_SEL_CFG_REG, 0x30);
126     WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30);
127 
128     // reset necessary peripheral modules
129     esp_system_reset_modules_on_exit();
130 
131     // Set CPU back to XTAL source, same as hard reset, but keep BBPLL on so that USB Serial JTAG can log at 1st stage bootloader.
132 #if !CONFIG_IDF_ENV_FPGA
133     rtc_clk_cpu_set_to_default_config();
134 #endif
135 
136 #if !CONFIG_FREERTOS_UNICORE
137     // Clear entry point for APP CPU
138     REG_WRITE(SYSTEM_CORE_1_CONTROL_1_REG, 0);
139 #endif
140 
141     // Reset CPUs
142     if (core_id == 0) {
143         // Running on PRO CPU: APP CPU is stalled. Can reset both CPUs.
144 #if !CONFIG_FREERTOS_UNICORE
145         esp_rom_software_reset_cpu(1);
146 #endif
147         esp_rom_software_reset_cpu(0);
148     }
149 #if !CONFIG_FREERTOS_UNICORE
150     else {
151         // Running on APP CPU: need to reset PRO CPU and unstall it,
152         // then reset APP CPU
153         esp_rom_software_reset_cpu(0);
154         esp_cpu_unstall(0);
155         esp_rom_software_reset_cpu(1);
156     }
157 #endif
158     while (true) {
159         ;
160     }
161 }
162