1 /*
2 * SPDX-FileCopyrightText: 2018-2021 Espressif Systems (Shanghai) CO LTD
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7 #include <zephyr/kernel.h>
8
9 #include <string.h>
10 #include "esp_system.h"
11 #include "esp_private/system_internal.h"
12 #include "esp_attr.h"
13 #include "esp_efuse.h"
14 #include "esp_log.h"
15 #include "esp_ipc_isr.h"
16 #include "sdkconfig.h"
17 #include "esp_rom_uart.h"
18 #include "soc/dport_reg.h"
19 #include "soc/gpio_periph.h"
20 #include "soc/efuse_periph.h"
21 #include "soc/rtc_periph.h"
22 #include "soc/timer_periph.h"
23 #include "esp_cpu.h"
24 #include "soc/rtc.h"
25 #include "esp_private/rtc_clk.h"
26 #include "hal/wdt_hal.h"
27
28 #include "esp32/rom/cache.h"
29 #include "esp32/rom/rtc.h"
30
esp_system_reset_modules_on_exit(void)31 void IRAM_ATTR esp_system_reset_modules_on_exit(void)
32 {
33 // Flush any data left in UART FIFOs before reset the UART peripheral
34 esp_rom_uart_tx_wait_idle(0);
35 esp_rom_uart_tx_wait_idle(1);
36 esp_rom_uart_tx_wait_idle(2);
37
38 // Reset wifi/bluetooth/ethernet/sdio (bb/mac)
39 DPORT_SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG,
40 DPORT_WIFIBB_RST | DPORT_FE_RST | DPORT_WIFIMAC_RST | DPORT_BTBB_RST |
41 DPORT_BTMAC_RST | DPORT_SDIO_RST | DPORT_SDIO_HOST_RST | DPORT_EMAC_RST |
42 DPORT_MACPWR_RST | DPORT_RW_BTMAC_RST | DPORT_RW_BTLP_RST);
43 DPORT_REG_WRITE(DPORT_CORE_RST_EN_REG, 0);
44
45 // Reset timer, spi, uart, mcpwm
46 DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG,
47 //UART TX FIFO cannot be reset correctly on ESP32, so reset the UART memory by DPORT here.
48 DPORT_TIMERS_RST | DPORT_SPI01_RST | DPORT_SPI2_RST | DPORT_SPI3_RST |
49 DPORT_SPI_DMA_RST | DPORT_UART_RST | DPORT_UART1_RST | DPORT_UART2_RST |
50 DPORT_UART_MEM_RST | DPORT_PWM0_RST | DPORT_PWM1_RST);
51 DPORT_REG_WRITE(DPORT_PERIP_RST_EN_REG, 0);
52 }
53
54 /* "inner" restart function for after RTOS, interrupts & anything else on this
55 * core are already stopped. Stalls other core, resets hardware,
56 * triggers restart.
57 */
esp_restart_noos(void)58 void IRAM_ATTR esp_restart_noos(void)
59 {
60 // Disable interrupts
61 z_xt_ints_off(0xFFFFFFFF);
62
63 // Enable RTC watchdog for 1 second
64 wdt_hal_context_t rtc_wdt_ctx;
65 wdt_hal_init(&rtc_wdt_ctx, WDT_RWDT, 0, false);
66 uint32_t stage_timeout_ticks = (uint32_t)(1000ULL * rtc_clk_slow_freq_get_hz() / 1000ULL);
67 wdt_hal_write_protect_disable(&rtc_wdt_ctx);
68 wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE0, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_SYSTEM);
69 wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE1, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_RTC);
70
71 //Enable flash boot mode so that flash booting after restart is protected by the RTC WDT.
72 wdt_hal_set_flashboot_en(&rtc_wdt_ctx, true);
73
74 // Reset and stall the other CPU.
75 // CPU must be reset before stalling, in case it was running a s32c1i
76 // instruction. This would cause memory pool to be locked by arbiter
77 // to the stalled CPU, preventing current CPU from accessing this pool.
78 const uint32_t core_id = esp_cpu_get_core_id();
79 const uint32_t other_core_id = (core_id == 0) ? 1 : 0;
80 esp_rom_software_reset_cpu(other_core_id);
81 esp_cpu_stall(other_core_id);
82
83 // Other core is now stalled, can access DPORT registers directly
84 esp_ipc_isr_stall_abort();
85
86 //Todo: Refactor to use Interrupt or Task Watchdog API, and a system level WDT context
87 // Disable TG0/TG1 watchdogs
88 wdt_hal_context_t wdt0_context = {.inst = WDT_MWDT0, .mwdt_dev = &TIMERG0};
89 wdt_hal_write_protect_disable(&wdt0_context);
90 wdt_hal_disable(&wdt0_context);
91 wdt_hal_write_protect_enable(&wdt0_context);
92
93 wdt_hal_context_t wdt1_context = {.inst = WDT_MWDT1, .mwdt_dev = &TIMERG1};
94 wdt_hal_write_protect_disable(&wdt1_context);
95 wdt_hal_disable(&wdt1_context);
96 wdt_hal_write_protect_enable(&wdt1_context);
97
98 #ifdef CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY
99 if (esp_ptr_external_ram(esp_cpu_get_sp())) {
100 // If stack_addr is from External Memory (CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY is used)
101 // then need to switch SP to Internal Memory otherwise
102 // we will get the "Cache disabled but cached memory region accessed" error after Cache_Read_Disable.
103 uint32_t new_sp = SOC_DRAM_LOW + (SOC_DRAM_HIGH - SOC_DRAM_LOW) / 2;
104 SET_STACK(new_sp);
105 }
106 #endif
107
108 // Disable cache
109 Cache_Read_Disable(0);
110 Cache_Read_Disable(1);
111
112 // 2nd stage bootloader reconfigures SPI flash signals.
113 // Reset them to the defaults expected by ROM.
114 WRITE_PERI_REG(GPIO_FUNC0_IN_SEL_CFG_REG, 0x30);
115 WRITE_PERI_REG(GPIO_FUNC1_IN_SEL_CFG_REG, 0x30);
116 WRITE_PERI_REG(GPIO_FUNC2_IN_SEL_CFG_REG, 0x30);
117 WRITE_PERI_REG(GPIO_FUNC3_IN_SEL_CFG_REG, 0x30);
118 WRITE_PERI_REG(GPIO_FUNC4_IN_SEL_CFG_REG, 0x30);
119 WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30);
120
121 // reset necessary peripheral modules
122 esp_system_reset_modules_on_exit();
123
124 // Set CPU back to XTAL source, same as hard reset. PLL keeps on to match the behavior with chips.
125 rtc_clk_cpu_set_to_default_config();
126
127 // Clear entry point for APP CPU
128 DPORT_REG_WRITE(DPORT_APPCPU_CTRL_D_REG, 0);
129
130 // Reset CPUs
131 if (core_id == 0) {
132 // Running on PRO CPU: APP CPU is stalled. Can reset both CPUs.
133 esp_rom_software_reset_cpu(1);
134 esp_rom_software_reset_cpu(0);
135 } else {
136 // Running on APP CPU: need to reset PRO CPU and unstall it,
137 // then reset APP CPU
138 esp_rom_software_reset_cpu(0);
139 esp_cpu_unstall(0);
140 esp_rom_software_reset_cpu(1);
141 }
142 while (true) {
143 ;
144 }
145 }
146
