1 /*
2  * SPDX-FileCopyrightText: 2018-2022 Espressif Systems (Shanghai) CO LTD
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  */
6 
7 #include <zephyr/kernel.h>
8 
9 #include <string.h>
10 #include "sdkconfig.h"
11 #include "esp_system.h"
12 #include "esp_private/system_internal.h"
13 #include "esp_attr.h"
14 #include "esp_efuse.h"
15 #include "esp_log.h"
16 #include "esp32s2/rom/cache.h"
17 #include "esp_rom_uart.h"
18 #include "soc/dport_reg.h"
19 #include "soc/gpio_reg.h"
20 #include "soc/timer_group_reg.h"
21 #include "esp_cpu.h"
22 #include "soc/rtc.h"
23 #include "esp_private/rtc_clk.h"
24 #include "soc/syscon_reg.h"
25 #include "soc/rtc_periph.h"
26 #include "hal/wdt_hal.h"
27 
28 #include "esp32s2/rom/rtc.h"
29 
30 #define ALIGN_DOWN(val, align)  ((val) & ~((align) - 1))
31 
32 extern int _bss_end;
33 
esp_system_reset_modules_on_exit(void)34 void IRAM_ATTR esp_system_reset_modules_on_exit(void)
35 {
36     // Flush any data left in UART FIFOs before reset the UART peripheral
37     esp_rom_uart_tx_wait_idle(0);
38     esp_rom_uart_tx_wait_idle(1);
39 
40     // Reset wifi/bluetooth/ethernet/sdio (bb/mac)
41     DPORT_SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG,
42                             DPORT_WIFIBB_RST | DPORT_FE_RST | DPORT_WIFIMAC_RST | DPORT_BTBB_RST |
43                             DPORT_BTMAC_RST  | DPORT_SDIO_RST | DPORT_EMAC_RST | DPORT_MACPWR_RST |
44                             DPORT_RW_BTMAC_RST | DPORT_RW_BTLP_RST);
45     DPORT_REG_WRITE(DPORT_CORE_RST_EN_REG, 0);
46 
47     // Reset timer/spi/uart
48     DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG,
49                             DPORT_TIMERS_RST | DPORT_SPI01_RST | DPORT_SPI2_RST | DPORT_SPI3_RST |
50                             DPORT_SPI2_DMA_RST | DPORT_SPI3_DMA_RST | DPORT_UART_RST);
51     DPORT_REG_WRITE(DPORT_PERIP_RST_EN_REG, 0);
52 }
53 
54 /* "inner" restart function for after RTOS, interrupts & anything else on this
55  * core are already stopped. Stalls other core, resets hardware,
56  * triggers restart.
57 */
esp_restart_noos(void)58 void IRAM_ATTR esp_restart_noos(void)
59 {
60     // Disable interrupts
61     z_xt_ints_off(0xFFFFFFFF);
62 
63     // Enable RTC watchdog for 1 second
64     wdt_hal_context_t rtc_wdt_ctx;
65     wdt_hal_init(&rtc_wdt_ctx, WDT_RWDT, 0, false);
66     uint32_t stage_timeout_ticks = (uint32_t)(1000ULL * rtc_clk_slow_freq_get_hz() / 1000ULL);
67     wdt_hal_write_protect_disable(&rtc_wdt_ctx);
68     wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE0, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_SYSTEM);
69     wdt_hal_config_stage(&rtc_wdt_ctx, WDT_STAGE1, stage_timeout_ticks, WDT_STAGE_ACTION_RESET_RTC);
70     //Enable flash boot mode so that flash booting after restart is protected by the RTC WDT.
71     wdt_hal_set_flashboot_en(&rtc_wdt_ctx, true);
72     wdt_hal_write_protect_enable(&rtc_wdt_ctx);
73 
74     //Todo: Refactor to use Interrupt or Task Watchdog API, and a system level WDT context
75     // Disable TG0/TG1 watchdogs
76     wdt_hal_context_t wdt0_context = {.inst = WDT_MWDT0, .mwdt_dev = &TIMERG0};
77     wdt_hal_write_protect_disable(&wdt0_context);
78     wdt_hal_disable(&wdt0_context);
79     wdt_hal_write_protect_enable(&wdt0_context);
80 
81     wdt_hal_context_t wdt1_context = {.inst = WDT_MWDT1, .mwdt_dev = &TIMERG1};
82     wdt_hal_write_protect_disable(&wdt1_context);
83     wdt_hal_disable(&wdt1_context);
84     wdt_hal_write_protect_enable(&wdt1_context);
85 
86 #ifdef CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY
87     if (esp_ptr_external_ram(esp_cpu_get_sp())) {
88         // If stack_addr is from External Memory (CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY is used)
89         // then need to switch SP to Internal Memory otherwise
90         // we will get the "Cache disabled but cached memory region accessed" error after Cache_Read_Disable.
91         uint32_t new_sp = ALIGN_DOWN(_bss_end, 16);
92         SET_STACK(new_sp);
93     }
94 #endif
95 
96     // Disable cache
97     Cache_Disable_ICache();
98     Cache_Disable_DCache();
99 
100     // 2nd stage bootloader reconfigures SPI flash signals.
101     // Reset them to the defaults expected by ROM.
102     WRITE_PERI_REG(GPIO_FUNC0_IN_SEL_CFG_REG, 0x30);
103     WRITE_PERI_REG(GPIO_FUNC1_IN_SEL_CFG_REG, 0x30);
104     WRITE_PERI_REG(GPIO_FUNC2_IN_SEL_CFG_REG, 0x30);
105     WRITE_PERI_REG(GPIO_FUNC3_IN_SEL_CFG_REG, 0x30);
106     WRITE_PERI_REG(GPIO_FUNC4_IN_SEL_CFG_REG, 0x30);
107     WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30);
108 
109     esp_system_reset_modules_on_exit();
110 
111     // Set CPU back to XTAL source, same as hard reset, but keep BBPLL on so that USB CDC can log at 1st stage bootloader.
112     rtc_clk_cpu_set_to_default_config();
113 
114     // Reset CPUs
115     esp_rom_software_reset_cpu(0);
116     while (true) {
117         ;
118     }
119 }
120