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/hal_espressif-latest/tools/esptool_py/docs/en/espefuse/inc/
Dsummary_ESP32-S2.rst12 …2) 4 bit of ADC calibration = 0 R/W (0x0)
13 … Temperature calibration data = 3.2 R/W (0b000100000)
14 …H (BLOCK2) = 55 R/W (0x37)
15 …H (BLOCK2) = 51 R/W (0x33)
16 …H (BLOCK2) = 52 R/W (0x34)
17 …H (BLOCK2) = 53 R/W (0x35)
18 …H (BLOCK2) = 56 R/W (0x38)
19 …H (BLOCK2) = 55 R/W (0x37)
20 …H (BLOCK2) = 55 R/W (0x37)
21 …H (BLOCK2) = 59 R/W (0x3b)
[all …]
Dsummary_ESP32-C3.rst12 … BLOCK1 K_RTC_LDO = -36 R/W (0b1001001)
13 … BLOCK1 K_DIG_LDO = -64 R/W (0b1010000)
14 …K1) BLOCK1 voltage of rtc dbias20 = -40 R/W (0x8a)
15 …K1) BLOCK1 voltage of digital dbias20 = -76 R/W (0x93)
16 … BLOCK1 digital dbias when hvt = -28 R/W (0b10111)
17 … BLOCK1 pvt threshold when hvt = 2000 R/W (0b0111110100)
18 … Temperature calibration data = -7.2 R/W (0b101001000)
19 … ADC OCode = 78 R/W (0x4e)
20 …2) ADC1 init code at atten0 = 1560 R/W (0b0110000110)
21 …2) ADC1 init code at atten1 = -108 R/W (0b1000011011)
[all …]
Dsummary_ESP32-S3.rst12 … Disable programming of individual eFuses = 0 R/W (0x00000000)
13 … Disable reading from BlOCK4-10 = 0 R/W (0b0000000)
14 … Set this bit to disable Icache = False R/W (0b0)
15 … Set this bit to disable Dcache = False R/W (0b0)
16 … Set this bit to disable CAN function = False R/W (0b0)
17 … Disable app cpu = False R/W (0b0)
18 …CK0) Disable direct boot mode = False R/W (0b0)
19 …OCK0) Set the default UART boot message output mode = Enable R/W (0b00)
20 …K0) Set default power supply for GPIO33-GPIO37; set wh = VDD3P3_CPU R/W (0b0)
23 …00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
[all …]
Dsummary_ESP32.rst12 … True ADC reference voltage = 1121 R/W (0b00011)
15 … Efuse write disable mask = 0 R/W (0x0000)
16 … Disable reading from BlOCK1-3 = 0 R/W (0x0)
17 …CK0): Disables APP CPU = False R/W (0b0)
18 … Disables Bluetooth = False R/W (0b0)
19 … Disables cache = False R/W (0b0)
20 …LOCK0): If set alongside EFUSE_RD_CHIP_CPU_FREQ_RATED; the = False R/W (0b0)
23 … (BLOCK0): If set; the ESP32's maximum CPU frequency has been = True R/W (0b1)
25 …LOCK0): BLOCK3 partially served for ADC calibration data = False R/W (0b0)
26 …): 8MHz clock freq override = 51 R/W (0x33)
[all …]
Dsummary_ESP32-H2.rst12 … Disable programming of individual eFuses = 0 R/W (0x00000000)
13 … Disable reading from BlOCK4-10 = 0 R/W (0b0000000)
14 … Represents whether icache is disabled or enabled. = False R/W (0b0)
16 …K0) Represents whether power glitch function is enable = False R/W (0b0)
18 … Represents whether TWAI function is disabled or en = False R/W (0b0)
20 …CK0) Represents whether direct boot mode is disabled or = False R/W (0b0)
22 …OCK0) Set the default UARTboot message output mode = Enable R/W (0b00)
23 … Set bits to enable hysteresis function of PAD0~5 = 0 R/W (0b000000)
24 … Set bits to enable hysteresis function of PAD6~27 = 0 R/W (0b000000000000000…
26 …00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
[all …]
Dsummary_ESP32-C6.rst12 … Disable programming of individual eFuses = 0 R/W (0x00000000)
13 … Disable reading from BlOCK4-10 = 0 R/W (0b0000000)
14 …LOCK0) Represents whether pad of uart and sdio is swapped = False R/W (0b0)
16 … Represents whether icache is disabled or enabled. = False R/W (0b0)
18 … Represents whether TWAI function is disabled or en = False R/W (0b0)
20 …CK0) Represents whether direct boot mode is disabled or = False R/W (0b0)
22 …OCK0) Set the default UARTboot message output mode = Enable R/W (0b00)
24 …00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
26 …00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
29 …K0) Represents the flash waiting time after power-up; = 0 R/W (0x0)
[all …]
Dsummary_ESP32-P4.rst12 … Disable programming of individual eFuses = 0 R/W (0x00000000)
13 … Disable reading from BlOCK4-10 = 0 R/W (0b0000000)
14 …K0) Represents whether power glitch function is enable = False R/W (0b0)
16 … Represents whether TWAI function is disabled or en = False R/W (0b0)
18 …(BLOCK0) Set this bit to control validation of HUK generate = 0 R/W (0b000000)
20 …IGH (BLOCK0) Set this bit to control validation of HUK generate = 0 R/W (0b000)
22 …LE (BLOCK0) Set bits to control key manager random number swit = 0 R/W (0b00)
25 …NCE (BLOCK0) Set each bit to control whether corresponding key = 0 R/W (0x0)
28 …CK0) Represents whether direct boot mode is disabled or = False R/W (0b0)
30 …L (BLOCK0) Represents the type of UART printing. 00: force en = 0 R/W (0b00)
[all …]
Dsummary_ESP32-C2.rst12 … Disable programming of individual eFuses = 0 R/W (0x00)
13 … Disable reading from BlOCK3 = 0 R/W (0b00)
14 …OCK0) Set the default UARTboot message output mode = Enable R/W (0b00)
15 …CK0) This bit set means disable direct_boot mode = False R/W (0b0)
18 …LOCK0) Set this bit to force ROM code to send a resume co = False R/W (0b0)
20 …K0) Configures flash waiting time after power-up; in u = 0 R/W (0x0)
26 …N_MAJOR (BLOCK0) Disables check of wafer version major = False R/W (0b0)
27 …MAJOR (BLOCK0) Disables check of blk version major = False R/W (0b0)
28 …NOR (BLOCK2) WAFER_VERSION_MINOR = 0 R/W (0x0)
29 …OR (BLOCK2) WAFER_VERSION_MAJOR = 1 R/W (0b01)
[all …]
/hal_espressif-latest/components/mbedtls/port/sha/parallel_engine/
Desp_sha1.c147 #define R(t) \ in mbedtls_sha1_software_process() macro
184 P( E, A, B, C, D, R(16) ); in mbedtls_sha1_software_process()
185 P( D, E, A, B, C, R(17) ); in mbedtls_sha1_software_process()
186 P( C, D, E, A, B, R(18) ); in mbedtls_sha1_software_process()
187 P( B, C, D, E, A, R(19) ); in mbedtls_sha1_software_process()
195 P( A, B, C, D, E, R(20) ); in mbedtls_sha1_software_process()
196 P( E, A, B, C, D, R(21) ); in mbedtls_sha1_software_process()
197 P( D, E, A, B, C, R(22) ); in mbedtls_sha1_software_process()
198 P( C, D, E, A, B, R(23) ); in mbedtls_sha1_software_process()
199 P( B, C, D, E, A, R(24) ); in mbedtls_sha1_software_process()
[all …]
Desp_sha256.c169 #define R(t) \ macro
198 R( i ); in mbedtls_sha256_software_process()
223 P( A[0], A[1], A[2], A[3], A[4], A[5], A[6], A[7], R(i + 0), K[i + 0] ); in mbedtls_sha256_software_process()
224 P( A[7], A[0], A[1], A[2], A[3], A[4], A[5], A[6], R(i + 1), K[i + 1] ); in mbedtls_sha256_software_process()
225 P( A[6], A[7], A[0], A[1], A[2], A[3], A[4], A[5], R(i + 2), K[i + 2] ); in mbedtls_sha256_software_process()
226 P( A[5], A[6], A[7], A[0], A[1], A[2], A[3], A[4], R(i + 3), K[i + 3] ); in mbedtls_sha256_software_process()
227 P( A[4], A[5], A[6], A[7], A[0], A[1], A[2], A[3], R(i + 4), K[i + 4] ); in mbedtls_sha256_software_process()
228 P( A[3], A[4], A[5], A[6], A[7], A[0], A[1], A[2], R(i + 5), K[i + 5] ); in mbedtls_sha256_software_process()
229 P( A[2], A[3], A[4], A[5], A[6], A[7], A[0], A[1], R(i + 6), K[i + 6] ); in mbedtls_sha256_software_process()
230 P( A[1], A[2], A[3], A[4], A[5], A[6], A[7], A[0], R(i + 7), K[i + 7] ); in mbedtls_sha256_software_process()
/hal_espressif-latest/tools/esptool_py/docs/en/espefuse/
Dburn-efuse-cmd.rst66 SPI_PAD_CONFIG_CLK Override SD_CLK pad (GPIO6/SPICLK) = 0 R/W (0x0)
67 SPI_PAD_CONFIG_Q Override SD_DATA_0 pad (GPIO7/SPIQ) = 0 R/W (0x0)
68 SPI_PAD_CONFIG_D Override SD_DATA_1 pad (GPIO8/SPID) = 0 R/W (0x0)
69 SPI_PAD_CONFIG_HD Override SD_DATA_2 pad (GPIO9/SPIHD) = 0 R/W (0x0)
70 SPI_PAD_CONFIG_CS0 Override SD_CMD pad (GPIO11/SPICS0) = 0 R/W (0x0)
77 …FIG_CLK (BLOCK1) SPI CLK pad = 0 R/W (0b000000)
78 …FIG_Q (BLOCK1) SPI Q (D1) pad = 0 R/W (0b000000)
79 …FIG_D (BLOCK1) SPI D (D0) pad = 0 R/W (0b000000)
80 …FIG_CS (BLOCK1) SPI CS pad = 0 R/W (0b000000)
81 …FIG_HD (BLOCK1) SPI HD (D3) pad = 0 R/W (0b000000)
[all …]
Dburn-custom-mac-cmd.rst49 … Version of the MAC field = Custom MAC in BLOCK3 R/W (0x01)
51 = 48:63:92:15:72:16 (CRC 0x75 OK) R/W
52 …CK3): CRC of custom MAC = 117 R/W (0x75)
55 …75 48 63 92 15 72 16 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00 00 R/W
90 …OCK0) Enable CUSTOM_MAC programming = True R/W (0b1)
92 = 48:63:92:15:72:16 (OK) R/W
120 = 48:63:92:15:72:16 (OK) R/W
Dburn-key-digest-cmd.rst70 …a2 cd 39 85 df 00 d7 95 07 0f f6 7c 8b ab e1 7d 39 11 95 c4 5b 37 6e 7b f0 ec 04 5e 36 30 02 5d R/-
101 … Flash encryption key length = 128 bits key R/W (0b0)
104 …00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 02 c2 bd 9c 1a b4 b7 44 22 59 c6 d3 12 0b 79 1f R/-
107 = 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/-
110 = 02 c2 bd 9c 1a b4 b7 44 22 59 c6 d3 12 0b 79 1f R/-
159 … KEY0 purpose = SECURE_BOOT_DIGEST0 R/- (0x9)
160 … KEY1 purpose = SECURE_BOOT_DIGEST1 R/- (0xa)
161 … KEY2 purpose = SECURE_BOOT_DIGEST2 R/- (0xb)
166 …a2 cd 39 85 df 00 d7 95 07 0f f6 7c 8b ab e1 7d 39 11 95 c4 5b 37 6e 7b f0 ec 04 5e 36 30 02 5d R/-
170 …a3 cd 39 85 df 00 d7 95 07 0f f6 7c 8b ab e1 7d 39 11 95 c4 5b 37 6e 7b f0 ec 04 5e 36 30 02 5d R/-
[all …]
Dindex.rst148 …LOCK3) Module version (56-63) = 0 R/W (0x00)
149 …3) Device role (64-66) = 0 R/W (0b000)
150 … [SETTING_1_ALT_NAME] Setting 1 (67-72) = 0 R/W (0b000000)
151 … Setting 2 (73-77) = 0 R/W (0b00000)
152 … [MY_ID_NUM] comment (140-147) = 0 R/W (0x00)
153 … [MY_ID_NUM] comment (132-139) = 0 R/W (0x00)
154 … [MY_ID_NUM] comment (122-129) = 0 R/W (0x00)
155 …ON (BLOCK3) Custom secure version (78-93) = 0 R/W (0x0000)
156 …) [MY_ID_NUMK] comment (150-157) = 0 R/W (0x00)
157 …) [MY_ID_NUMK] comment (182-189) = 0 R/W (0x00)
[all …]
Dsummary-cmd.rst29 The ``R/W`` output indicates a protection status of a specific eFuse field/block:
38 - ``R/-`` indicates that write protection is set. No further bits can be set.
135 … Secure boot V1 is enabled for bootloader image = False R/W (0b0)
137 …00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 R/W
Dread-write-protections-cmd.rst26 The ``R/W`` output indicates a protection status of a specific eFuse field/block:
35 - ``R/-`` indicates that write protection is set. No further bits can be set.
/hal_espressif-latest/components/mbedtls/port/ecc/
Decc_alt.c18 static int esp_mbedtls_ecp_point_multiply(const mbedtls_ecp_group *grp, mbedtls_ecp_point *R, in esp_mbedtls_ecp_point_multiply() argument
42 MBEDTLS_MPI_CHK(mbedtls_mpi_read_binary(&R->MBEDTLS_PRIVATE(X), x_tmp, MAX_SIZE)); in esp_mbedtls_ecp_point_multiply()
43 MBEDTLS_MPI_CHK(mbedtls_mpi_read_binary(&R->MBEDTLS_PRIVATE(Y), y_tmp, MAX_SIZE)); in esp_mbedtls_ecp_point_multiply()
44 MBEDTLS_MPI_CHK(mbedtls_mpi_lset(&R->MBEDTLS_PRIVATE(Z), 1)); in esp_mbedtls_ecp_point_multiply()
51 int ecp_mul_restartable_internal( mbedtls_ecp_group *grp, mbedtls_ecp_point *R, in ecp_mul_restartable_internal() argument
59 return ecp_mul_restartable_internal_soft(grp, R, m, P, f_rng, p_rng, rs_ctx); in ecp_mul_restartable_internal()
69 MBEDTLS_MPI_CHK( esp_mbedtls_ecp_point_multiply(grp, R, m, P) ); in ecp_mul_restartable_internal()
/hal_espressif-latest/components/esp_hw_support/port/esp32c2/
Dcpu_region_protect.c55 const unsigned R = PMP_L | PMP_R; in esp_cpu_configure_region_protection() local
114 PMP_ENTRY_CFG_SET(5, PMP_NAPOT | R); in esp_cpu_configure_region_protection()
118 PMP_ENTRY_CFG_SET(7, PMP_TOR | R); in esp_cpu_configure_region_protection()
/hal_espressif-latest/components/esp_hw_support/port/esp32c3/
Dcpu_region_protect.c33 const unsigned R = PMP_L | PMP_TOR | PMP_R; in esp_cpu_configure_region_protection() local
52 PMP_ENTRY_SET(3, SOC_DRAM_LOW, R); in esp_cpu_configure_region_protection()
63 PMP_ENTRY_SET(5, SOC_DROM_MASK_HIGH, R); in esp_cpu_configure_region_protection()
/hal_espressif-latest/components/mbedtls/port/include/mbedtls/
Decp.h16 int ecp_mul_restartable_internal( mbedtls_ecp_group *grp, mbedtls_ecp_point *R,
23 int ecp_mul_restartable_internal_soft( mbedtls_ecp_group *grp, mbedtls_ecp_point *R,
/hal_espressif-latest/components/esp_hw_support/port/esp32h2/
Dcpu_region_protect.c23 #define CONDITIONAL_R R
105 __attribute__((unused)) const unsigned R = PMP_L | PMP_R; in esp_cpu_configure_region_protection() local
171 PMP_ENTRY_SET(10, drom_resv_end, PMP_TOR | R); in esp_cpu_configure_region_protection()
/hal_espressif-latest/components/esp_hw_support/port/esp32c6/
Dcpu_region_protect.c23 #define CONDITIONAL_R R
105 __attribute__((unused)) const unsigned R = PMP_L | PMP_R; in esp_cpu_configure_region_protection() local
171 PMP_ENTRY_SET(10, drom_resv_end, PMP_TOR | R); in esp_cpu_configure_region_protection()
/hal_espressif-latest/components/wpa_supplicant/src/crypto/
Dsha256-internal.c74 #define R(x, n) (((x)&0xFFFFFFFFUL)>>(n)) macro
77 #define Gamma0(x) (S(x, 7) ^ S(x, 18) ^ R(x, 3))
78 #define Gamma1(x) (S(x, 17) ^ S(x, 19) ^ R(x, 10))
Dsha512-internal.c95 #define R(x, n) (((x) & CONST64(0xFFFFFFFFFFFFFFFF)) >> ((u64) n)) macro
98 #define Gamma0(x) (S(x, 1) ^ S(x, 8) ^ R(x, 7))
99 #define Gamma1(x) (S(x, 19) ^ S(x, 61) ^ R(x, 6))
/hal_espressif-latest/tools/esptool_py/test/secure_images/
Drsa_secure_boot_signing_key.pem36 R+j+nvs9TUl6RnX9v8tPsjGMBoj9OSXCDVJlWSw9LpBliJ5eGyJfcsFsAUZLUXlq

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