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Searched refs:mclk (Results 1 – 25 of 33) sorted by relevance

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/Zephyr-latest/dts/arm/atmel/
Dsaml21.dtsi22 clocks = <&gclk 25>, <&mclk 0x1c 5>;
36 clocks = <&gclk 25>, <&mclk 0x1c 6>;
50 clocks = <&gclk 26>, <&mclk 0x1c 7>;
64 clocks = <&gclk 32>, <&mclk 0x1c 12>;
72 clocks = <&gclk 18>, <&mclk 0x1c 0>;
80 clocks = <&gclk 19>, <&mclk 0x1c 1>;
88 clocks = <&gclk 20>, <&mclk 0x1c 2>;
96 clocks = <&gclk 21>, <&mclk 0x1c 3>;
104 clocks = <&gclk 22>, <&mclk 0x1c 4>;
112 clocks = <&gclk 24>, <&mclk 0x20 1>;
[all …]
Dsamd5x.dtsi94 mclk: mclk@40000800 { label
95 compatible = "atmel,sam0-mclk";
181 clocks = <&gclk 7>, <&mclk 0x14 12>;
192 clocks = <&gclk 8>, <&mclk 0x14 13>;
203 clocks = <&gclk 23>, <&mclk 0x18 9>;
214 clocks = <&gclk 24>, <&mclk 0x18 10>;
225 clocks = <&gclk 34>, <&mclk 0x20 0>;
236 clocks = <&gclk 35>, <&mclk 0x20 1>;
247 clocks = <&gclk 36>, <&mclk 0x20 2>;
258 clocks = <&gclk 37>, <&mclk 0x20 3>;
[all …]
Dsamc2x.dtsi82 mclk: mclk@40000800 { label
83 compatible = "atmel,sam0-mclk";
135 clocks = <&gclk 33>, <&mclk 0x1c 17>;
150 clocks = <&gclk 19>, <&mclk 0x1c 1>;
161 clocks = <&gclk 20>, <&mclk 0x1c 2>;
172 clocks = <&gclk 21>, <&mclk 0x1c 3>;
183 clocks = <&gclk 22>, <&mclk 0x1c 4>;
194 clocks = <&gclk 28>, <&mclk 0x1c 9>;
208 clocks = <&gclk 28>, <&mclk 0x1c 10>;
222 clocks = <&gclk 29>, <&mclk 0x1c 11>;
[all …]
Dsamc21.dtsi24 clocks = <&gclk 34>, <&mclk 0x1c 18>;
39 clocks = <&gclk 23>, <&mclk 0x1c 5>;
50 clocks = <&gclk 25>, <&mclk 0x1c 6>;
62 clocks = <&gclk 26>, <&mclk 0x10 8>;
77 clocks = <&gclk 27>, <&mclk 0x10 9>;
Dsame5x.dtsi38 clocks = <&gclk 27>, <&mclk 0x10 17>;
53 clocks = <&gclk 28>, <&mclk 0x10 18>;
Dsaml2x.dtsi85 mclk: mclk@40000400 { label
86 compatible = "atmel,sam0-mclk";
203 clocks = <&osc32kctrl>, <&mclk 0x14 8>;
Dsamd2x.dtsi83 compatible = "atmel,sam0-mclk";
/Zephyr-latest/soc/atmel/sam0/common/
Datmel_sam0_dt.h29 COND_CODE_1(DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(mclk)), \
30 (ATMEL_SAM0_DT_INST_CELL_REG_ADDR_OFFSET(n, mclk)), \
36 COND_CODE_1(DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(mclk)), \
37 (ATMEL_SAM0_DT_INST_CELL_PERIPH_MASK(n, mclk, cell)), \
/Zephyr-latest/drivers/dac/
Ddac_sam0.c33 volatile uint32_t *mclk; member
85 *cfg->mclk |= cfg->mclk_mask; in dac_sam0_init()
136 .mclk = ATMEL_SAM0_DT_INST_MCLK_PM_REG_ADDR_OFFSET(n), \
/Zephyr-latest/drivers/pwm/
Dpwm_sam0_tcc.c31 volatile uint32_t *mclk; member
107 *cfg->mclk |= cfg->mclk_mask; in pwm_sam0_init()
157 .mclk = ATMEL_SAM0_DT_INST_MCLK_PM_REG_ADDR_OFFSET(inst), \
Dpwm_sam0_tc.c41 volatile uint32_t *mclk; member
137 *cfg->mclk |= cfg->mclk_mask; in pwm_sam0_init()
202 .mclk = ATMEL_SAM0_DT_INST_MCLK_PM_REG_ADDR_OFFSET(inst), \
/Zephyr-latest/drivers/can/
Dcan_sam0.c30 volatile uint32_t *mclk; member
116 *cfg->mclk |= cfg->mclk_mask; in can_sam0_clock_enable()
221 .mclk = ATMEL_SAM0_DT_INST_MCLK_PM_REG_ADDR_OFFSET(inst), \
/Zephyr-latest/drivers/i2s/
Di2s_mcux_sai.c427 static void get_mclk_rate(const struct device *dev, uint32_t *mclk) in get_mclk_rate() argument
438 *mclk = rate; in get_mclk_rate()
441 *mclk = rate; in get_mclk_rate()
457 uint32_t mclk; in i2s_mcux_config() local
494 get_mclk_rate(dev, &mclk); in i2s_mcux_config()
495 LOG_DBG("mclk is %d", mclk); in i2s_mcux_config()
618 SAI_TxSetBitClockRate(base, mclk, i2s_cfg->frame_clk_freq, word_size_bits, in i2s_mcux_config()
641 SAI_RxSetBitClockRate(base, mclk, i2s_cfg->frame_clk_freq, word_size_bits, in i2s_mcux_config()
1098 uint32_t mclk; in i2s_mcux_initialize() local
1145 get_mclk_rate(dev, &mclk); in i2s_mcux_initialize()
[all …]
Di2s_esp32.c102 i2s_hal_clock_info->mclk = i2s_cfg->frame_clk_freq * i2s_hal_clock_info->bclk_div; in i2s_esp32_calculate_clock()
106 i2s_hal_clock_info->mclk = i2s_cfg->frame_clk_freq * mclk_multiple; in i2s_esp32_calculate_clock()
107 i2s_hal_clock_info->bclk_div = i2s_hal_clock_info->mclk / i2s_hal_clock_info->bclk; in i2s_esp32_calculate_clock()
111 i2s_hal_clock_info->mclk_div = i2s_hal_clock_info->sclk / i2s_hal_clock_info->mclk; in i2s_esp32_calculate_clock()
/Zephyr-latest/drivers/timer/
Dsam0_rtc_timer.c252 volatile uint32_t *mclk = ATMEL_SAM0_DT_INST_MCLK_PM_REG_ADDR_OFFSET(0); in sys_clock_driver_init() local
255 *mclk |= mclk_mask; in sys_clock_driver_init()
/Zephyr-latest/dts/xtensa/nxp/
Dnxp_imx8m.dtsi45 mclk1: mclk {
103 mclk-is-output;
/Zephyr-latest/drivers/audio/
Dwm8904.c69 static int wm8904_audio_fmt_config(const struct device *dev, audio_dai_cfg_t *cfg, uint32_t mclk) in wm8904_audio_fmt_config() argument
111 fs = (mclk >> (mclkDiv & 0x1U)) / cfg->i2s.frame_clk_freq; in wm8904_audio_fmt_config()
675 .mclk_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR_BY_NAME(n, mclk)), \
676 .mclk_name = (clock_control_subsys_t)DT_INST_CLOCKS_CELL_BY_NAME(n, mclk, name)}; \
/Zephyr-latest/drivers/counter/
Dcounter_sam0_tc32.c37 volatile uint32_t *mclk; member
337 *cfg->mclk |= cfg->mclk_mask; in counter_sam0_tc32_initialize()
422 .mclk = ATMEL_SAM0_DT_INST_MCLK_PM_REG_ADDR_OFFSET(n), \
/Zephyr-latest/drivers/adc/
Dadc_sam0.c52 volatile uint32_t *mclk; member
453 *cfg->mclk |= cfg->mclk_mask; in adc_sam0_init()
570 .mclk = ATMEL_SAM0_DT_INST_MCLK_PM_REG_ADDR_OFFSET(n), \
/Zephyr-latest/drivers/spi/
Dspi_sam0.c34 volatile uint32_t *mclk; member
649 *cfg->mclk |= cfg->mclk_mask; in spi_sam0_init()
725 .mclk = ATMEL_SAM0_DT_INST_MCLK_PM_REG_ADDR_OFFSET(n), \
737 .mclk = ATMEL_SAM0_DT_INST_MCLK_PM_REG_ADDR_OFFSET(n), \
/Zephyr-latest/drivers/i2c/
Di2c_sam0.c40 volatile uint32_t *mclk; member
713 *cfg->mclk |= cfg->mclk_mask; in i2c_sam0_initialize()
826 .mclk = ATMEL_SAM0_DT_INST_MCLK_PM_REG_ADDR_OFFSET(n), \
839 .mclk = ATMEL_SAM0_DT_INST_MCLK_PM_REG_ADDR_OFFSET(n), \
/Zephyr-latest/drivers/dai/intel/ssp/
Ddai-params-intel-ipc4.h288 uint32_t mclk : 1; member
/Zephyr-latest/drivers/rtc/
Drtc_sam0.c47 volatile uint32_t *mclk; member
510 *cfg->mclk |= cfg->mclk_mask; in rtc_sam0_init()
611 .mclk = ATMEL_SAM0_DT_INST_MCLK_PM_REG_ADDR_OFFSET(n), \
/Zephyr-latest/drivers/serial/
Duart_sam0.c41 volatile uint32_t *mclk; member
513 *cfg->mclk |= cfg->mclk_mask; in uart_sam0_init()
1279 .mclk = ATMEL_SAM0_DT_INST_MCLK_PM_REG_ADDR_OFFSET(n), \
/Zephyr-latest/boards/nxp/mimxrt685_evk/
Dmimxrt685_evk_mimxrt685s_cm33.dts405 clock-names = "mclk";

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