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Searched refs:mclk (Results 1 – 25 of 28) sorted by relevance

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/Zephyr-latest/dts/arm/atmel/
Dsaml21.dtsi22 clocks = <&gclk 25>, <&mclk 0x1c 5>;
34 clocks = <&gclk 25>, <&mclk 0x1c 6>;
46 clocks = <&gclk 26>, <&mclk 0x1c 7>;
58 clocks = <&gclk 32>, <&mclk 0x1c 12>;
64 clocks = <&gclk 18>, <&mclk 0x1c 0>;
70 clocks = <&gclk 19>, <&mclk 0x1c 1>;
76 clocks = <&gclk 20>, <&mclk 0x1c 2>;
82 clocks = <&gclk 21>, <&mclk 0x1c 3>;
88 clocks = <&gclk 22>, <&mclk 0x1c 4>;
94 clocks = <&gclk 24>, <&mclk 0x20 1>;
[all …]
Dsamd5x.dtsi90 mclk: mclk@40000800 { label
91 compatible = "atmel,samd5x-mclk";
169 clocks = <&gclk 7>, <&mclk 0x14 12>;
178 clocks = <&gclk 8>, <&mclk 0x14 13>;
187 clocks = <&gclk 23>, <&mclk 0x18 9>;
196 clocks = <&gclk 24>, <&mclk 0x18 10>;
205 clocks = <&gclk 34>, <&mclk 0x20 0>;
214 clocks = <&gclk 35>, <&mclk 0x20 1>;
223 clocks = <&gclk 36>, <&mclk 0x20 2>;
232 clocks = <&gclk 37>, <&mclk 0x20 3>;
[all …]
Dsamc21.dtsi23 clocks = <&gclk 34>, <&mclk 0x1c 18>;
37 clocks = <&gclk 23>, <&mclk 0x1c 5>;
46 clocks = <&gclk 25>, <&mclk 0x1c 6>;
56 clocks = <&gclk 26>, <&mclk 0x10 8>;
69 clocks = <&gclk 27>, <&mclk 0x10 9>;
Dsamc2x.dtsi80 mclk: mclk@40000800 { label
81 compatible = "atmel,samc2x-mclk";
125 clocks = <&gclk 33>, <&mclk 0x1c 17>;
139 clocks = <&gclk 19>, <&mclk 0x1c 1>;
148 clocks = <&gclk 20>, <&mclk 0x1c 2>;
157 clocks = <&gclk 21>, <&mclk 0x1c 3>;
166 clocks = <&gclk 22>, <&mclk 0x1c 4>;
175 clocks = <&gclk 28>, <&mclk 0x1c 9>;
187 clocks = <&gclk 28>, <&mclk 0x1c 10>;
199 clocks = <&gclk 29>, <&mclk 0x1c 11>;
Dsame5x.dtsi37 clocks = <&gclk 27>, <&mclk 0x10 17>;
50 clocks = <&gclk 28>, <&mclk 0x10 18>;
Dsaml2x.dtsi91 mclk: mclk@40000400 { label
92 compatible = "atmel,saml2x-mclk";
/Zephyr-latest/soc/atmel/sam0/common/
Datmel_sam0_dt.h19 (DT_REG_ADDR(DT_INST_PHANDLE_BY_NAME(n, clocks, mclk)) + \
20 DT_INST_CLOCKS_CELL_BY_NAME(n, mclk, offset))
/Zephyr-latest/drivers/pwm/
Dpwm_sam0_tcc.c30 volatile uint32_t *mclk; member
113 *cfg->mclk |= cfg->mclk_mask; in pwm_sam0_init()
145 .mclk = (volatile uint32_t *)MCLK_MASK_DT_INT_REG_ADDR(inst), \
146 .mclk_mask = BIT(DT_INST_CLOCKS_CELL_BY_NAME(inst, mclk, bit)), \
Dpwm_sam0_tc.c41 volatile uint32_t *mclk; member
144 *cfg->mclk |= cfg->mclk_mask; in pwm_sam0_init()
190 .mclk = (volatile uint32_t *)MCLK_MASK_DT_INT_REG_ADDR(inst), \
191 .mclk_mask = BIT(DT_INST_CLOCKS_CELL_BY_NAME(inst, mclk, bit)), \
/Zephyr-latest/drivers/can/
Dcan_sam0.c27 volatile uint32_t *mclk; member
130 *cfg->mclk |= cfg->mclk_mask; in can_sam0_clock_enable()
214 .mclk = (volatile uint32_t *)MCLK_MASK_DT_INT_REG_ADDR(inst), \
215 .mclk_mask = BIT(DT_INST_CLOCKS_CELL_BY_NAME(inst, mclk, bit)), \
/Zephyr-latest/drivers/i2s/
Di2s_mcux_sai.c419 static void get_mclk_rate(const struct device *dev, uint32_t *mclk) in get_mclk_rate() argument
430 *mclk = rate; in get_mclk_rate()
433 *mclk = rate; in get_mclk_rate()
443 uint32_t mclk; in i2s_mcux_config() local
507 get_mclk_rate(dev, &mclk); in i2s_mcux_config()
508 LOG_DBG("mclk is %d", mclk); in i2s_mcux_config()
647 SAI_TxSetBitClockRate(base, mclk, i2s_cfg->frame_clk_freq, word_size_bits, in i2s_mcux_config()
670 SAI_RxSetBitClockRate(base, mclk, i2s_cfg->frame_clk_freq, word_size_bits, in i2s_mcux_config()
1100 uint32_t mclk; in i2s_mcux_initialize() local
1147 get_mclk_rate(dev, &mclk); in i2s_mcux_initialize()
[all …]
Di2s_esp32.c102 i2s_hal_clock_info->mclk = i2s_cfg->frame_clk_freq * i2s_hal_clock_info->bclk_div; in i2s_esp32_calculate_clock()
106 i2s_hal_clock_info->mclk = i2s_cfg->frame_clk_freq * mclk_multiple; in i2s_esp32_calculate_clock()
107 i2s_hal_clock_info->bclk_div = i2s_hal_clock_info->mclk / i2s_hal_clock_info->bclk; in i2s_esp32_calculate_clock()
111 i2s_hal_clock_info->mclk_div = i2s_hal_clock_info->sclk / i2s_hal_clock_info->mclk; in i2s_esp32_calculate_clock()
/Zephyr-latest/dts/xtensa/nxp/
Dnxp_imx8m.dtsi45 mclk1: mclk {
103 mclk-is-output;
/Zephyr-latest/drivers/counter/
Dcounter_sam0_tc32.c35 volatile uint32_t *mclk; member
345 *cfg->mclk |= cfg->mclk_mask; in counter_sam0_tc32_initialize()
408 .mclk = (volatile uint32_t *)MCLK_MASK_DT_INT_REG_ADDR(n), \
409 .mclk_mask = BIT(DT_INST_CLOCKS_CELL_BY_NAME(n, mclk, bit)), \
/Zephyr-latest/drivers/audio/
Dwm8904.c69 static int wm8904_audio_fmt_config(const struct device *dev, audio_dai_cfg_t *cfg, uint32_t mclk) in wm8904_audio_fmt_config() argument
111 fs = (mclk >> (mclkDiv & 0x1U)) / cfg->i2s.frame_clk_freq; in wm8904_audio_fmt_config()
675 .mclk_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR_BY_NAME(n, mclk)), \
676 .mclk_name = (clock_control_subsys_t)DT_INST_CLOCKS_CELL_BY_NAME(n, mclk, name)}; \
/Zephyr-latest/drivers/i2c/
Di2c_sam0.c38 volatile uint32_t *mclk; member
719 *cfg->mclk |= cfg->mclk_mask; in i2c_sam0_initialize()
825 .mclk = (volatile uint32_t *)MCLK_MASK_DT_INT_REG_ADDR(n), \
826 .mclk_mask = BIT(DT_INST_CLOCKS_CELL_BY_NAME(n, mclk, bit)), \
/Zephyr-latest/drivers/spi/
Dspi_sam0.c31 volatile uint32_t *mclk; member
654 *cfg->mclk |= cfg->mclk_mask; in spi_sam0_init()
724 .mclk = (volatile uint32_t *)MCLK_MASK_DT_INT_REG_ADDR(n), \
725 .mclk_mask = BIT(DT_INST_CLOCKS_CELL_BY_NAME(n, mclk, bit)), \
/Zephyr-latest/drivers/dai/intel/ssp/
Ddai-params-intel-ipc4.h288 uint32_t mclk : 1; member
/Zephyr-latest/drivers/serial/
Duart_sam0.c39 volatile uint32_t *mclk; member
519 *cfg->mclk |= cfg->mclk_mask; in uart_sam0_init()
1280 .mclk = (volatile uint32_t *)MCLK_MASK_DT_INT_REG_ADDR(n), \
1281 .mclk_mask = BIT(DT_INST_CLOCKS_CELL_BY_NAME(n, mclk, bit)), \
/Zephyr-latest/dts/arm/nxp/
Dnxp_imx95_m7.dtsi190 mclk-is-output;
Dnxp_rt1010.dtsi298 /* The maximum input frequency into the SAI mclk input is 300MHz
/Zephyr-latest/drivers/adc/
Dadc_sam0.c519 .mclk_mask = BIT(DT_INST_CLOCKS_CELL_BY_NAME(n, mclk, bit)), \
/Zephyr-latest/boards/nxp/mimxrt685_evk/
Dmimxrt685_evk_mimxrt685s_cm33.dts405 clock-names = "mclk";
/Zephyr-latest/boards/nxp/mimxrt595_evk/
Dmimxrt595_evk_mimxrt595s_cm33.dts477 clock-names = "mclk";
/Zephyr-latest/dts/arm64/nxp/
Dnxp_mimx93_a55.dtsi367 mclk-is-output;

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