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Searched refs:gclk (Results 1 – 25 of 26) sorted by relevance

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/Zephyr-latest/dts/arm/atmel/
Dsaml21.dtsi22 clocks = <&gclk 25>, <&mclk 0x1c 5>;
24 atmel,assigned-clocks = <&gclk 0>;
36 clocks = <&gclk 25>, <&mclk 0x1c 6>;
38 atmel,assigned-clocks = <&gclk 0>;
50 clocks = <&gclk 26>, <&mclk 0x1c 7>;
52 atmel,assigned-clocks = <&gclk 0>;
64 clocks = <&gclk 32>, <&mclk 0x1c 12>;
66 atmel,assigned-clocks = <&gclk 0>;
72 clocks = <&gclk 18>, <&mclk 0x1c 0>;
74 atmel,assigned-clocks = <&gclk 0>;
[all …]
Dsamd20.dtsi22 clocks = <&gclk 0x13>, <&pm 0x20 8>;
24 atmel,assigned-clocks = <&gclk 0>;
33 clocks = <&gclk 0x14>, <&pm 0x20 10>;
35 atmel,assigned-clocks = <&gclk 0>;
44 clocks = <&gclk 0x16>, <&pm 0x20 14>;
46 atmel,assigned-clocks = <&gclk 0>;
55 clocks = <&gclk 26>, <&pm 0x20 18>;
57 atmel,assigned-clocks = <&gclk 0>;
62 clocks = <&gclk 2>, <&pm 0x18 5>;
64 atmel,assigned-clocks = <&gclk 4>;
[all …]
Dsamd21.dtsi42 clocks = <&gclk 0x1d>, <&pm 0x20 14>;
44 atmel,assigned-clocks = <&gclk 0>;
53 clocks = <&gclk 26>, <&pm 0x20 8>;
55 atmel,assigned-clocks = <&gclk 0>;
67 clocks = <&gclk 26>, <&pm 0x20 9>;
69 atmel,assigned-clocks = <&gclk 0>;
81 clocks = <&gclk 27>, <&pm 0x20 10>;
83 atmel,assigned-clocks = <&gclk 0>;
95 clocks = <&gclk 33>, <&pm 0x20 18>;
97 atmel,assigned-clocks = <&gclk 0>;
[all …]
Dsamc21.dtsi24 clocks = <&gclk 34>, <&mclk 0x1c 18>;
26 atmel,assigned-clocks = <&gclk 0>;
39 clocks = <&gclk 23>, <&mclk 0x1c 5>;
41 atmel,assigned-clocks = <&gclk 0>;
50 clocks = <&gclk 25>, <&mclk 0x1c 6>;
52 atmel,assigned-clocks = <&gclk 0>;
62 clocks = <&gclk 26>, <&mclk 0x10 8>;
64 atmel,assigned-clocks = <&gclk 0>;
77 clocks = <&gclk 27>, <&mclk 0x10 9>;
79 atmel,assigned-clocks = <&gclk 0>;
Dsamd5x.dtsi108 gclk: gclk@40001c00 { label
109 compatible = "atmel,sam0-gclk";
181 clocks = <&gclk 7>, <&mclk 0x14 12>;
183 atmel,assigned-clocks = <&gclk 0>;
192 clocks = <&gclk 8>, <&mclk 0x14 13>;
194 atmel,assigned-clocks = <&gclk 0>;
203 clocks = <&gclk 23>, <&mclk 0x18 9>;
205 atmel,assigned-clocks = <&gclk 0>;
214 clocks = <&gclk 24>, <&mclk 0x18 10>;
216 atmel,assigned-clocks = <&gclk 0>;
[all …]
Dsamc2x.dtsi96 gclk: gclk@40001c00 { label
97 compatible = "atmel,sam0-gclk";
135 clocks = <&gclk 33>, <&mclk 0x1c 17>;
137 atmel,assigned-clocks = <&gclk 0>;
150 clocks = <&gclk 19>, <&mclk 0x1c 1>;
152 atmel,assigned-clocks = <&gclk 0>;
161 clocks = <&gclk 20>, <&mclk 0x1c 2>;
163 atmel,assigned-clocks = <&gclk 0>;
172 clocks = <&gclk 21>, <&mclk 0x1c 3>;
174 atmel,assigned-clocks = <&gclk 0>;
[all …]
Dsame5x.dtsi38 clocks = <&gclk 27>, <&mclk 0x10 17>;
40 atmel,assigned-clocks = <&gclk 0>;
53 clocks = <&gclk 28>, <&mclk 0x10 18>;
55 atmel,assigned-clocks = <&gclk 0>;
Dsamd2x.dtsi90 gclk: gclk@40000c00 { label
91 compatible = "atmel,sam0-gclk";
194 clocks = <&gclk 4 4>, <&pm 0x18 5>;
Dsaml2x.dtsi100 gclk: gclk@40001800 { label
101 compatible = "atmel,sam0-gclk";
/Zephyr-latest/soc/atmel/sam0/common/
Dsoc_samd2x.c44 static void gclk_connect(uint8_t gclk, uint32_t src, uint32_t div, uint32_t flags) in gclk_connect() argument
46 GCLK->GENDIV.reg = GCLK_GENDIV_ID(gclk) in gclk_connect()
52 GCLK->GENCTRL.reg = GCLK_GENCTRL_ID(gclk) in gclk_connect()
Dsoc_samd5x.c133 static void gclk_connect(uint8_t gclk, uint8_t src, uint8_t div) in gclk_connect() argument
135 GCLK->GENCTRL[gclk].reg = GCLK_GENCTRL_SRC(src) in gclk_connect()
/Zephyr-latest/drivers/dac/
Ddac_sam0.c134 .gclk_gen = ASSIGNED_CLOCKS_CELL_BY_NAME(n, gclk, gen), \
135 .gclk_id = DT_INST_CLOCKS_CELL_BY_NAME(n, gclk, id), \
/Zephyr-latest/drivers/pwm/
Dpwm_sam0_tcc.c155 .gclk_gen = ASSIGNED_CLOCKS_CELL_BY_NAME(inst, gclk, gen), \
156 .gclk_id = DT_INST_CLOCKS_CELL_BY_NAME(inst, gclk, id), \
Dpwm_sam0_tc.c200 .gclk_gen = ASSIGNED_CLOCKS_CELL_BY_NAME(inst, gclk, gen), \
201 .gclk_id = DT_INST_CLOCKS_CELL_BY_NAME(inst, gclk, id), \
/Zephyr-latest/drivers/timer/
Dsam0_rtc_timer.c261 | GCLK_CLKCTRL_GEN(ASSIGNED_CLOCKS_CELL_BY_NAME(0, gclk, gen)) in sys_clock_driver_init()
262 | GCLK_CLKCTRL_ID(DT_INST_CLOCKS_CELL_BY_NAME(0, gclk, id)); in sys_clock_driver_init()
/Zephyr-latest/drivers/can/
Dcan_sam0.c219 .gclk_gen = ASSIGNED_CLOCKS_CELL_BY_NAME(inst, gclk, gen), \
220 .gclk_id = DT_INST_CLOCKS_CELL_BY_NAME(inst, gclk, id), \
/Zephyr-latest/drivers/adc/
Dadc_sam0.c555 ASSIGNED_CLOCKS_CELL_BY_NAME(n, gclk, gen)), \
568 .gclk_gen = ASSIGNED_CLOCKS_CELL_BY_NAME(n, gclk, gen), \
569 .gclk_id = DT_INST_CLOCKS_CELL_BY_NAME(n, gclk, id), \
/Zephyr-latest/drivers/spi/
Dspi_sam0.c723 .gclk_gen = ASSIGNED_CLOCKS_CELL_BY_NAME(n, gclk, gen), \
724 .gclk_id = DT_INST_CLOCKS_CELL_BY_NAME(n, gclk, id), \
735 .gclk_gen = ASSIGNED_CLOCKS_CELL_BY_NAME(n, gclk, gen), \
736 .gclk_id = DT_INST_CLOCKS_CELL_BY_NAME(n, gclk, id), \
/Zephyr-latest/drivers/i2c/
Di2c_sam0.c824 .gclk_gen = ASSIGNED_CLOCKS_CELL_BY_NAME(n, gclk, gen), \
825 .gclk_id = DT_INST_CLOCKS_CELL_BY_NAME(n, gclk, id), \
837 .gclk_gen = ASSIGNED_CLOCKS_CELL_BY_NAME(n, gclk, gen), \
838 .gclk_id = DT_INST_CLOCKS_CELL_BY_NAME(n, gclk, id), \
/Zephyr-latest/drivers/counter/
Dcounter_sam0_tc32.c420 .gclk_gen = ASSIGNED_CLOCKS_CELL_BY_NAME(n, gclk, gen), \
421 .gclk_id = DT_INST_CLOCKS_CELL_BY_NAME(n, gclk, id), \
/Zephyr-latest/drivers/rtc/
Drtc_sam0.c575 COND_CODE_1(DT_INST_CLOCKS_HAS_NAME(n, gclk), \
578 .gclk_gen = ASSIGNED_CLOCKS_CELL_BY_NAME(n, gclk, gen), \
579 .gclk_id = DT_INST_CLOCKS_CELL_BY_NAME(n, gclk, id) \
/Zephyr-latest/drivers/serial/
Duart_sam0.c1277 .gclk_gen = ASSIGNED_CLOCKS_CELL_BY_NAME(n, gclk, gen), \
1278 .gclk_id = DT_INST_CLOCKS_CELL_BY_NAME(n, gclk, id), \
/Zephyr-latest/doc/releases/
Drelease-notes-4.1.rst594 * :dtcompatible:`atmel,sam0-gclk`
Drelease-notes-2.4.rst1346 * :github:`26617` - devicetree: sam0 gclk
Drelease-notes-3.2.rst1067 * :dtcompatible:`atmel,saml2x-gclk`

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