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Searched refs:gclk (Results 1 – 22 of 22) sorted by relevance

/Zephyr-latest/dts/arm/atmel/
Dsamd20.dtsi21 clocks = <&gclk 0x13>, <&pm 0x20 8>;
30 clocks = <&gclk 0x14>, <&pm 0x20 10>;
39 clocks = <&gclk 0x16>, <&pm 0x20 14>;
48 clocks = <&gclk 26>, <&pm 0x20 18>;
54 clocks = <&gclk 0xd>, <&pm 0x20 2>;
60 clocks = <&gclk 0xe>, <&pm 0x20 3>;
66 clocks = <&gclk 0xf>, <&pm 0x20 4>;
72 clocks = <&gclk 0x10>, <&pm 0x20 5>;
78 clocks = <&gclk 0x11>, <&pm 0x20 6>;
84 clocks = <&gclk 0x12>, <&pm 0x20 7>;
[all …]
Dsaml21.dtsi22 clocks = <&gclk 25>, <&mclk 0x1c 5>;
34 clocks = <&gclk 25>, <&mclk 0x1c 6>;
46 clocks = <&gclk 26>, <&mclk 0x1c 7>;
58 clocks = <&gclk 32>, <&mclk 0x1c 12>;
64 clocks = <&gclk 18>, <&mclk 0x1c 0>;
70 clocks = <&gclk 19>, <&mclk 0x1c 1>;
76 clocks = <&gclk 20>, <&mclk 0x1c 2>;
82 clocks = <&gclk 21>, <&mclk 0x1c 3>;
88 clocks = <&gclk 22>, <&mclk 0x1c 4>;
94 clocks = <&gclk 24>, <&mclk 0x20 1>;
[all …]
Dsamd21.dtsi41 clocks = <&gclk 0x1d>, <&pm 0x20 14>;
50 clocks = <&gclk 26>, <&pm 0x20 8>;
62 clocks = <&gclk 26>, <&pm 0x20 9>;
74 clocks = <&gclk 27>, <&pm 0x20 10>;
86 clocks = <&gclk 33>, <&pm 0x20 18>;
92 clocks = <&gclk 0x14>, <&pm 0x20 2>;
98 clocks = <&gclk 0x15>, <&pm 0x20 3>;
104 clocks = <&gclk 0x16>, <&pm 0x20 4>;
110 clocks = <&gclk 0x17>, <&pm 0x20 5>;
116 clocks = <&gclk 0x18>, <&pm 0x20 6>;
[all …]
Dsamc21.dtsi23 clocks = <&gclk 34>, <&mclk 0x1c 18>;
29 gclk = <0>;
37 clocks = <&gclk 23>, <&mclk 0x1c 5>;
46 clocks = <&gclk 25>, <&mclk 0x1c 6>;
56 clocks = <&gclk 26>, <&mclk 0x10 8>;
69 clocks = <&gclk 27>, <&mclk 0x10 9>;
Dsamd5x.dtsi97 gclk: gclk@40001c00 { label
98 compatible = "atmel,samd5x-gclk";
169 clocks = <&gclk 7>, <&mclk 0x14 12>;
178 clocks = <&gclk 8>, <&mclk 0x14 13>;
187 clocks = <&gclk 23>, <&mclk 0x18 9>;
196 clocks = <&gclk 24>, <&mclk 0x18 10>;
205 clocks = <&gclk 34>, <&mclk 0x20 0>;
214 clocks = <&gclk 35>, <&mclk 0x20 1>;
223 clocks = <&gclk 36>, <&mclk 0x20 2>;
232 clocks = <&gclk 37>, <&mclk 0x20 3>;
[all …]
Dsamc2x.dtsi87 gclk: gclk@40001c00 { label
88 compatible = "atmel,samc2x-gclk";
125 clocks = <&gclk 33>, <&mclk 0x1c 17>;
131 gclk = <0>;
139 clocks = <&gclk 19>, <&mclk 0x1c 1>;
148 clocks = <&gclk 20>, <&mclk 0x1c 2>;
157 clocks = <&gclk 21>, <&mclk 0x1c 3>;
166 clocks = <&gclk 22>, <&mclk 0x1c 4>;
175 clocks = <&gclk 28>, <&mclk 0x1c 9>;
187 clocks = <&gclk 28>, <&mclk 0x1c 10>;
[all …]
Dsame5x.dtsi37 clocks = <&gclk 27>, <&mclk 0x10 17>;
50 clocks = <&gclk 28>, <&mclk 0x10 18>;
Dsamd2x.dtsi87 gclk: gclk@40000c00 { label
88 compatible = "atmel,samd2x-gclk";
206 gclk = <3>;
Dsaml2x.dtsi98 gclk: gclk@40001800 { label
99 compatible = "atmel,saml2x-gclk";
216 gclk = <3>;
/Zephyr-latest/drivers/adc/
Dadc_sam0.c55 uint32_t gclk; member
459 GCLK->CLKCTRL.reg = cfg->gclk | GCLK_CLKCTRL_CLKEN; in adc_sam0_init()
521 DT_INST_PROP(n, gclk)), \
522 .gclk_id = DT_INST_CLOCKS_CELL_BY_NAME(n, gclk, periph_ch), \
538 .gclk = UTIL_CAT(GCLK_CLKCTRL_GEN_GCLK, DT_INST_PROP(n, gclk)) |\
569 DT_INST_PROP(n, gclk)), \
/Zephyr-latest/soc/atmel/sam0/common/
Dsoc_samd5x.c106 static void gclk_connect(uint8_t gclk, uint8_t src, uint8_t div) in gclk_connect() argument
108 GCLK->GENCTRL[gclk].reg = GCLK_GENCTRL_SRC(src) in gclk_connect()
/Zephyr-latest/drivers/pwm/
Dpwm_sam0_tcc.c147 .gclk_id = DT_INST_CLOCKS_CELL_BY_NAME(inst, gclk, periph_ch)
151 .gclk_clkctrl_id = DT_INST_CLOCKS_CELL_BY_NAME(inst, gclk, clkctrl_id)
Dpwm_sam0_tc.c192 .gclk_id = DT_INST_CLOCKS_CELL_BY_NAME(inst, gclk, periph_ch)
196 .gclk_clkctrl_id = DT_INST_CLOCKS_CELL_BY_NAME(inst, gclk, clkctrl_id)
/Zephyr-latest/drivers/dac/
Ddac_sam0.c124 DT_INST_CLOCKS_CELL_BY_NAME(n, gclk, clkctrl_id), \
/Zephyr-latest/drivers/counter/
Dcounter_sam0_tc32.c410 .gclk_id = DT_INST_CLOCKS_CELL_BY_NAME(n, gclk, periph_ch),
414 .gclk_clkctrl_id = DT_INST_CLOCKS_CELL_BY_NAME(n, gclk, clkctrl_id),
/Zephyr-latest/drivers/can/
Dcan_sam0.c216 .gclk_core_id = DT_INST_CLOCKS_CELL_BY_NAME(inst, gclk, periph_ch), \
/Zephyr-latest/drivers/i2c/
Di2c_sam0.c827 .gclk_core_id = DT_INST_CLOCKS_CELL_BY_NAME(n, gclk, periph_ch),\
838 .gclk_clkctrl_id = DT_INST_CLOCKS_CELL_BY_NAME(n, gclk, clkctrl_id),\
/Zephyr-latest/drivers/spi/
Dspi_sam0.c726 .gclk_core_id = DT_INST_CLOCKS_CELL_BY_NAME(n, gclk, periph_ch),\
736 .gclk_clkctrl_id = DT_INST_CLOCKS_CELL_BY_NAME(n, gclk, clkctrl_id),\
/Zephyr-latest/drivers/serial/
Duart_sam0.c1282 .gclk_core_id = DT_INST_CLOCKS_CELL_BY_NAME(n, gclk, periph_ch),\
1295 .gclk_clkctrl_id = DT_INST_CLOCKS_CELL_BY_NAME(n, gclk, clkctrl_id),\
/Zephyr-latest/doc/releases/
Drelease-notes-2.4.rst1346 * :github:`26617` - devicetree: sam0 gclk
Drelease-notes-3.2.rst1067 * :dtcompatible:`atmel,saml2x-gclk`
Drelease-notes-3.3.rst1251 - :dtcompatible:`atmel,samc2x-gclk`