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Searched refs:STM32_RESET (Results 1 – 25 of 100) sorted by relevance

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/Zephyr-latest/dts/arm/st/f4/
Dstm32f413.dtsi17 resets = <&rctl STM32_RESET(APB1, 19U)>;
26 resets = <&rctl STM32_RESET(APB1, 20U)>;
35 resets = <&rctl STM32_RESET(APB1, 30U)>;
44 resets = <&rctl STM32_RESET(APB1, 31U)>;
53 resets = <&rctl STM32_RESET(APB2, 6U)>;
62 resets = <&rctl STM32_RESET(APB2, 7U)>;
Dstm32f405.dtsi50 resets = <&rctl STM32_RESET(APB1, 18U)>;
59 resets = <&rctl STM32_RESET(APB1, 19U)>;
68 resets = <&rctl STM32_RESET(APB1, 20U)>;
77 resets = <&rctl STM32_RESET(APB1, 4U)>;
93 resets = <&rctl STM32_RESET(APB1, 5U)>;
109 resets = <&rctl STM32_RESET(APB2, 1U)>;
132 resets = <&rctl STM32_RESET(APB1, 6U)>;
154 resets = <&rctl STM32_RESET(APB1, 7U)>;
176 resets = <&rctl STM32_RESET(APB1, 8U)>;
/Zephyr-latest/dts/arm/st/f0/
Dstm32f030Xc.dtsi33 resets = <&rctl STM32_RESET(APB1, 18U)>;
42 resets = <&rctl STM32_RESET(APB1, 19U)>;
51 resets = <&rctl STM32_RESET(APB1, 20U)>;
60 resets = <&rctl STM32_RESET(APB2, 5U)>;
69 resets = <&rctl STM32_RESET(APB1, 5U)>;
Dstm32f091.dtsi23 resets = <&rctl STM32_RESET(APB1, 20U)>;
32 resets = <&rctl STM32_RESET(APB2, 5U)>;
41 resets = <&rctl STM32_RESET(APB2, 6U)>;
50 resets = <&rctl STM32_RESET(APB2, 7U)>;
Dstm32f070Xb.dtsi32 resets = <&rctl STM32_RESET(APB1, 18U)>;
41 resets = <&rctl STM32_RESET(APB1, 19U)>;
72 resets = <&rctl STM32_RESET(APB1, 4U)>;
83 resets = <&rctl STM32_RESET(APB1, 5U)>;
Dstm32f071.dtsi48 resets = <&rctl STM32_RESET(APB1, 18U)>;
57 resets = <&rctl STM32_RESET(APB1, 19U)>;
66 resets = <&rctl STM32_RESET(APB1, 5U)>;
Dstm32f030X8.dtsi25 resets = <&rctl STM32_RESET(APB1, 17U)>;
56 resets = <&rctl STM32_RESET(APB1, 4U)>;
67 resets = <&rctl STM32_RESET(APB2, 16U)>;
Dstm32f051.dtsi17 resets = <&rctl STM32_RESET(APB1, 17U)>;
48 resets = <&rctl STM32_RESET(APB1, 4U)>;
59 resets = <&rctl STM32_RESET(APB2, 16U)>;
/Zephyr-latest/dts/arm/st/h5/
Dstm32h562.dtsi130 resets = <&rctl STM32_RESET(APB1L, 19U)>;
139 resets = <&rctl STM32_RESET(APB1L, 20U)>;
148 resets = <&rctl STM32_RESET(APB1L, 30U)>;
157 resets = <&rctl STM32_RESET(APB1L, 31U)>;
166 resets = <&rctl STM32_RESET(APB1H, 0U)>;
175 resets = <&rctl STM32_RESET(APB1L, 25U)>;
184 resets = <&rctl STM32_RESET(APB1L, 26U)>;
193 resets = <&rctl STM32_RESET(APB1L, 27U)>;
202 resets = <&rctl STM32_RESET(APB1H, 1U)>;
294 resets = <&rctl STM32_RESET(APB1L, 2U)>;
[all …]
/Zephyr-latest/dts/arm/st/f1/
Dstm32f103Xg.dtsi36 resets = <&rctl STM32_RESET(APB2, 19U)>;
53 resets = <&rctl STM32_RESET(APB2, 20U)>;
70 resets = <&rctl STM32_RESET(APB2, 21U)>;
87 resets = <&rctl STM32_RESET(APB1, 6U)>;
104 resets = <&rctl STM32_RESET(APB1, 7U)>;
121 resets = <&rctl STM32_RESET(APB1, 8U)>;
Dstm32f103Xc.dtsi30 resets = <&rctl STM32_RESET(APB1, 19U)>;
39 resets = <&rctl STM32_RESET(APB1, 20U)>;
48 resets = <&rctl STM32_RESET(APB1, 3U)>;
65 resets = <&rctl STM32_RESET(APB1, 4U)>;
76 resets = <&rctl STM32_RESET(APB1, 5U)>;
144 resets = <&rctl STM32_RESET(APB2, 13U)>;
Dstm32f105.dtsi68 resets = <&rctl STM32_RESET(APB1, 19U)>;
77 resets = <&rctl STM32_RESET(APB1, 20U)>;
106 resets = <&rctl STM32_RESET(APB1, 3U)>;
123 resets = <&rctl STM32_RESET(APB1, 4U)>;
134 resets = <&rctl STM32_RESET(APB1, 5U)>;
/Zephyr-latest/dts/arm/st/g0/
Dstm32g070.dtsi18 resets = <&rctl STM32_RESET(APB1L, 18U)>;
27 resets = <&rctl STM32_RESET(APB1L, 19U)>;
36 resets = <&rctl STM32_RESET(APB1H, 16U)>;
Dstm32g051.dtsi17 resets = <&rctl STM32_RESET(APB1L, 4U)>;
32 resets = <&rctl STM32_RESET(APB1L, 5U)>;
48 resets = <&rctl STM32_RESET(APB1H, 16U)>;
Dstm32g031.dtsi18 resets = <&rctl STM32_RESET(APB1L, 20U)>;
27 resets = <&rctl STM32_RESET(APB1L, 0U)>;
Dstm32g050.dtsi17 resets = <&rctl STM32_RESET(APB1L, 4U)>;
28 resets = <&rctl STM32_RESET(APB1L, 5U)>;
/Zephyr-latest/dts/arm/st/l0/
Dstm32l071.dtsi61 resets = <&rctl STM32_RESET(APB1, 1U)>;
83 resets = <&rctl STM32_RESET(APB1, 4U)>;
99 resets = <&rctl STM32_RESET(APB1, 5U)>;
115 resets = <&rctl STM32_RESET(APB2, 5U)>;
137 resets = <&rctl STM32_RESET(APB2, 14U)>;
146 resets = <&rctl STM32_RESET(APB1, 19U)>;
155 resets = <&rctl STM32_RESET(APB1, 20U)>;
Dstm32l051.dtsi39 resets = <&rctl STM32_RESET(APB2, 14U)>;
48 resets = <&rctl STM32_RESET(APB2, 5U)>;
65 resets = <&rctl STM32_RESET(APB1, 4U)>;
/Zephyr-latest/dts/arm/st/l4/
Dstm32l471.dtsi52 resets = <&rctl STM32_RESET(APB1L, 18U)>;
61 resets = <&rctl STM32_RESET(APB1L, 19U)>;
70 resets = <&rctl STM32_RESET(APB1L, 20U)>;
111 resets = <&rctl STM32_RESET(APB1L, 1U)>;
133 resets = <&rctl STM32_RESET(APB1L, 2U)>;
155 resets = <&rctl STM32_RESET(APB1L, 3U)>;
177 resets = <&rctl STM32_RESET(APB1L, 5U)>;
193 resets = <&rctl STM32_RESET(APB2, 13U)>;
210 resets = <&rctl STM32_RESET(APB2, 18U)>;
242 resets = <&rctl STM32_RESET(APB2, 10U)>;
Dstm32l4p5.dtsi101 resets = <&rctl STM32_RESET(APB1L, 18U)>;
110 resets = <&rctl STM32_RESET(APB1L, 19U)>;
119 resets = <&rctl STM32_RESET(APB1L, 20U)>;
172 resets = <&rctl STM32_RESET(APB1L, 1U)>;
194 resets = <&rctl STM32_RESET(APB1L, 2U)>;
216 resets = <&rctl STM32_RESET(APB1L, 3U)>;
238 resets = <&rctl STM32_RESET(APB1L, 5U)>;
260 resets = <&rctl STM32_RESET(APB2, 13U)>;
277 resets = <&rctl STM32_RESET(APB2, 18U)>;
343 resets = <&rctl STM32_RESET(AHB2, 22U)>;
[all …]
/Zephyr-latest/dts/arm/st/f3/
Dstm32f373.dtsi72 resets = <&rctl STM32_RESET(APB1, 2U)>;
89 resets = <&rctl STM32_RESET(APB1, 3U)>;
106 resets = <&rctl STM32_RESET(APB1, 6U)>;
123 resets = <&rctl STM32_RESET(APB1, 7U)>;
140 resets = <&rctl STM32_RESET(APB1, 8U)>;
157 resets = <&rctl STM32_RESET(APB1, 9U)>;
174 resets = <&rctl STM32_RESET(APB2, 19U)>;
/Zephyr-latest/dts/arm/st/f2/
Dstm32f2.dtsi235 resets = <&rctl STM32_RESET(APB2, 4U)>;
244 resets = <&rctl STM32_RESET(APB1, 17U)>;
253 resets = <&rctl STM32_RESET(APB1, 18U)>;
262 resets = <&rctl STM32_RESET(APB2, 5U)>;
271 resets = <&rctl STM32_RESET(APB1, 19U)>;
280 resets = <&rctl STM32_RESET(APB1, 20U)>;
413 resets = <&rctl STM32_RESET(APB2, 0U)>;
430 resets = <&rctl STM32_RESET(APB1, 0U)>;
447 resets = <&rctl STM32_RESET(APB1, 1U)>;
469 resets = <&rctl STM32_RESET(APB1, 2U)>;
[all …]
/Zephyr-latest/dts/arm/st/f7/
Dstm32f7.dtsi258 resets = <&rctl STM32_RESET(APB2, 4U)>;
267 resets = <&rctl STM32_RESET(APB1, 17U)>;
276 resets = <&rctl STM32_RESET(APB1, 18U)>;
285 resets = <&rctl STM32_RESET(APB1, 19U)>;
294 resets = <&rctl STM32_RESET(APB1, 20U)>;
303 resets = <&rctl STM32_RESET(APB2, 5U)>;
312 resets = <&rctl STM32_RESET(APB1, 30U)>;
321 resets = <&rctl STM32_RESET(APB1, 31U)>;
425 resets = <&rctl STM32_RESET(APB2, 0U)>;
442 resets = <&rctl STM32_RESET(APB1, 0U)>;
[all …]
/Zephyr-latest/include/zephyr/dt-bindings/reset/
Dstm32-common.h20 #define STM32_RESET(bus, bit) (((STM32_RESET_BUS_##bus) << 5U) | (bit)) macro
/Zephyr-latest/dts/arm/st/u0/
Dstm32u0.dtsi195 resets = <&rctl STM32_RESET(APB1H, 14U)>;
204 resets = <&rctl STM32_RESET(APB1L, 17U)>;
213 resets = <&rctl STM32_RESET(APB1L, 18U)>;
222 resets = <&rctl STM32_RESET(APB1L, 20U)>;
231 resets = <&rctl STM32_RESET(APB1L, 7U)>;
375 resets = <&rctl STM32_RESET(AHB1, 16U)>;
396 resets = <&rctl STM32_RESET(APB1H, 11U)>;
418 resets = <&rctl STM32_RESET(APB1L, 0U)>;
440 resets = <&rctl STM32_RESET(APB1L, 1U)>;
462 resets = <&rctl STM32_RESET(APB1L, 4U)>;
[all …]

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