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Searched refs:STM32_CLOCK_BUS_APB1 (Results 1 – 25 of 160) sorted by relevance

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/Zephyr-latest/include/zephyr/dt-bindings/clock/
Dstm32l1_clock.h14 #define STM32_CLOCK_BUS_APB1 0x024 macro
17 #define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB1
Dstm32f1_clock.h16 #define STM32_CLOCK_BUS_APB1 0x01c macro
19 #define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB1
Dstm32l0_clock.h15 #define STM32_CLOCK_BUS_APB1 0x038 macro
18 #define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB1
Dstm32f0_clock.h14 #define STM32_CLOCK_BUS_APB1 0x01c macro
17 #define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB1
Dstm32f3_clock.h14 #define STM32_CLOCK_BUS_APB1 0x01c macro
17 #define STM32_PERIPH_BUS_MAX STM32_CLOCK_BUS_APB1
Dstm32_clock.h12 #define STM32_CLOCK_BUS_APB1 2 macro
Dstm32wb0_clock.h24 #define STM32_CLOCK_BUS_APB1 0x58 macro
Dstm32f4_clock.h17 #define STM32_CLOCK_BUS_APB1 0x040 macro
Dstm32c0_clock.h14 #define STM32_CLOCK_BUS_APB1 0x03c macro
Dstm32h7_clock.h47 #define STM32_CLOCK_BUS_APB1 0x0E8 macro
52 #define STM32_SRC_PCLK1 STM32_CLOCK_BUS_APB1
/Zephyr-latest/tests/drivers/clock_control/stm32_clock_configuration/stm32_common_devices/boards/
Dg0_i2c1_hsi_lptim1_lse_adc1_pllp.overlay68 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>,
74 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>,
Dg0_i2c1_sysclk_lptim1_lsi.overlay68 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>,
74 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>,
Dwb_i2c1_hsi_lptim1_lse.overlay74 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>,
80 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>,
Dl4_i2c1_hsi_lptim1_lse.overlay75 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>,
82 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>,
Dl4_i2c1_sysclk_lptim1_lsi.overlay75 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>,
82 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>,
Dwl_i2c1_sysclk_lptim1_lsi.overlay71 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>,
79 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>,
Dwl_i2c1_hsi_lptim1_lse_adc1_pllp.overlay85 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00200000>,
93 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>,
/Zephyr-latest/boards/st/nucleo_g0b1re/
Dnucleo_g0b1re.dts106 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000400>,
182 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00001000>,
190 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00001000>,
225 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>,
/Zephyr-latest/boards/weact/stm32g431_core/
Dweact_stm32g431_core.dts118 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000400>,
124 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>,
183 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00800000>,
/Zephyr-latest/boards/antmicro/myra_sip_baseboard/
Dmyra_sip_baseboard.dts133 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>,
139 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000400>,
197 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>,
/Zephyr-latest/boards/others/candlelightfd/
Dcandlelightfd_stm32g0b1xx_dual.dts24 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00001000>,
/Zephyr-latest/boards/seeed/lora_e5_mini/
Dlora_e5_mini.dts50 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>,
87 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000400>,
/Zephyr-latest/boards/st/nucleo_g474re/
Dnucleo_g474re.dts159 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>,
165 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000400>,
223 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x02000000>,
/Zephyr-latest/boards/we/oceanus1ev/
Dwe_oceanus1ev.dts56 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x80000000>,
116 clocks = <&rcc STM32_CLOCK_BUS_APB1 0x00000400>,
/Zephyr-latest/drivers/clock_control/
Dclock_stm32_ll_mp1.c25 case STM32_CLOCK_BUS_APB1: in stm32_clock_control_on()
76 case STM32_CLOCK_BUS_APB1: in stm32_clock_control_off()
128 case STM32_CLOCK_BUS_APB1: in stm32_clock_control_get_subsys_rate()

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