| /Zephyr-latest/soc/sifive/sifive_freedom/fe300/ |
| D | clock.c | 25 BUILD_ASSERT(MHZ(16) == CORECLK_HZ || in soc_early_init_hook()
26 (MHZ(48) <= CORECLK_HZ && MHZ(320) >= CORECLK_HZ && in soc_early_init_hook()
27 (CORECLK_HZ % MHZ(8)) == 0), in soc_early_init_hook()
32 if (MHZ(16) == CORECLK_HZ) { in soc_early_init_hook()
41 if (MHZ(768) / 8 >= CORECLK_HZ) { in soc_early_init_hook()
43 } else if (MHZ(768) / 4 >= CORECLK_HZ) { in soc_early_init_hook()
49 const int pll_f = ((CORECLK_HZ / MHZ(1)) >> (4 - pll_q)) - 1; in soc_early_init_hook()
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| /Zephyr-latest/tests/drivers/clock_control/nrf_clock_control/src/ |
| D | main.c | 21 .frequency = MHZ(128),
26 .frequency = MHZ(320),
31 .frequency = MHZ(64),
40 .frequency = MHZ(16),
45 .frequency = MHZ(16),
50 .frequency = MHZ(16),
66 .frequency = MHZ(16),
71 .frequency = MHZ(19),
76 .frequency = MHZ(16),
109 .frequency = MHZ(320),
[all …]
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| /Zephyr-latest/drivers/clock_control/ |
| D | clock_control_npcx.c | 159 BUILD_ASSERT(CORE_CLK <= MAX_OFMCLK && CORE_CLK >= MHZ(4) &&
164 CORE_CLK / (FIUDIV_VAL + 1) >= MHZ(4),
168 CORE_CLK / (FIU1DIV_VAL + 1) >= MHZ(4),
172 CORE_CLK / (AHB6DIV_VAL + 1) >= MHZ(4),
175 APBSRC_CLK / (APB1DIV_VAL + 1) >= MHZ(4) &&
179 APBSRC_CLK / (APB2DIV_VAL + 1) >= MHZ(8) &&
188 APBSRC_CLK / (APB4DIV_VAL + 1) >= MHZ(8) &&
193 BUILD_ASSERT(OFMCLK / (MCLKD_SL + 1) <= MHZ(50) &&
194 OFMCLK / (MCLKD_SL + 1) >= MHZ(40),
196 BUILD_ASSERT(APBSRC_CLK / (APB4DIV_VAL + 1) >= MHZ(20),
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| D | clock_stm32l0_l1.c | 90 if (hclk_freq <= MHZ(4.2)) { in config_regulator_voltage()
92 } else if (hclk_freq <= MHZ(16)) { in config_regulator_voltage()
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| D | clock_stm32_ll_h5.c | 366 if (MHZ(1) <= vco_freq && vco_freq <= MHZ(2)) { in get_vco_input_range()
368 } else if (MHZ(2) < vco_freq && vco_freq <= MHZ(4)) { in get_vco_input_range()
370 } else if (MHZ(4) < vco_freq && vco_freq <= MHZ(8)) { in get_vco_input_range()
372 } else if (MHZ(8) < vco_freq && vco_freq <= MHZ(16)) { in get_vco_input_range()
394 if (hclk_freq <= MHZ(100)) { in set_regu_voltage()
396 } else if (hclk_freq <= MHZ(150)) { in set_regu_voltage()
398 } else if (hclk_freq <= MHZ(200)) { in set_regu_voltage()
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| D | clock_control_ast10x0.c | 18 #define HPLL_FREQ MHZ(1000)
110 src = MHZ(480); in aspeed_clock_control_get_rate()
140 *rate = MHZ(24) / 13; in aspeed_clock_control_get_rate()
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| D | clock_stm32_ll_u5.c | 407 if (MHZ(4) <= vco_freq && vco_freq <= MHZ(8)) { in get_vco_input_range()
409 } else if (MHZ(8) < vco_freq && vco_freq <= MHZ(16)) { in get_vco_input_range()
420 if (hclk_freq < MHZ(25)) { in set_regu_voltage()
422 } else if (hclk_freq < MHZ(55)) { in set_regu_voltage()
424 } else if (hclk_freq < MHZ(110)) { in set_regu_voltage()
452 if (MHZ(55) <= CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC) { in set_epod_booster()
469 } else if (IS_ENABLED(STM32_PLL_SRC_HSE) && (MHZ(16) < STM32_HSE_FREQ)) { in set_epod_booster()
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| D | clock_stm32_ll_wba.c | 196 __ASSERT(ahb5_clock <= MHZ(32), "AHB5 clock frequency exceeds 32 MHz"); in stm32_clock_control_get_subsys_rate()
321 if (MHZ(4) <= vco_freq && vco_freq <= MHZ(8)) { in get_vco_input_range()
323 } else if (MHZ(8) < vco_freq && vco_freq <= MHZ(16)) { in get_vco_input_range()
334 if (hclk_freq <= MHZ(16)) { in set_regu_voltage()
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| D | clock_control_nrf2_hsfll.c | 24 #define HSFLL_FREQ_LOW MHZ(64)
25 #define HSFLL_FREQ_MEDLOW MHZ(128)
26 #define HSFLL_FREQ_HIGH MHZ(320)
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| D | clock_stm32g4.c | 61 if (sys_clock_hw_cycles_per_sec() >= MHZ(150)) { in config_pll_sysclock()
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| /Zephyr-latest/include/zephyr/sd/ |
| D | sd_spec.h | 373 HS_MAX_DTR = MHZ(50),
379 UHS_SDR12_MAX_DTR = MHZ(25),
380 UHS_SDR25_MAX_DTR = MHZ(50),
381 UHS_SDR50_MAX_DTR = MHZ(100),
382 UHS_SDR104_MAX_DTR = MHZ(208),
383 UHS_DDR50_MAX_DTR = MHZ(50),
432 SD_CLOCK_25MHZ = MHZ(25),
433 SD_CLOCK_50MHZ = MHZ(50),
434 SD_CLOCK_100MHZ = MHZ(100),
435 SD_CLOCK_208MHZ = MHZ(208),
[all …]
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| /Zephyr-latest/tests/boards/espressif/rtc_clk/src/ |
| D | rtc_clk_test.c | 56 clk_cfg.cpu.xtal_freq = (DT_PROP(DT_INST(0, DT_CPU_COMPAT), xtal_freq) / MHZ(1)); in ZTEST()
70 zassert_equal(cpu_rate, clk_cfg.cpu.cpu_freq * MHZ(1), in ZTEST()
96 clk_cfg.cpu.xtal_freq = (DT_PROP(DT_INST(0, DT_CPU_COMPAT), xtal_freq) / MHZ(1)); in ZTEST()
99 clk_cfg.cpu.cpu_freq = rtc_pll_src_freq_mhz[i] / MHZ(1); in ZTEST()
110 zassert_equal(cpu_rate, clk_cfg.cpu.cpu_freq * MHZ(1), in ZTEST()
139 clk_cfg.cpu.xtal_freq = (DT_PROP(DT_INST(0, DT_CPU_COMPAT), xtal_freq) / MHZ(1)); in ZTEST()
191 clk_cfg.cpu.xtal_freq = (DT_PROP(DT_INST(0, DT_CPU_COMPAT), xtal_freq) / MHZ(1)); in ZTEST()
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| /Zephyr-latest/soc/ite/ec/it8xxx2/ |
| D | soc.c | 55 pllfreq = MHZ(8); in chip_get_pll_freq()
58 pllfreq = MHZ(16); in chip_get_pll_freq()
61 pllfreq = MHZ(24); in chip_get_pll_freq()
64 pllfreq = MHZ(32); in chip_get_pll_freq()
67 pllfreq = MHZ(48); in chip_get_pll_freq()
70 pllfreq = MHZ(64); in chip_get_pll_freq()
73 pllfreq = MHZ(72); in chip_get_pll_freq()
76 pllfreq = MHZ(96); in chip_get_pll_freq()
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| /Zephyr-latest/soc/nxp/kinetis/ke1xz/ |
| D | soc.c | 55 #if MHZ(2) == DT_PROP(SCG_CLOCK_NODE(sirc_clk), clock_frequency)
57 #elif MHZ(8) == DT_PROP(SCG_CLOCK_NODE(sirc_clk), clock_frequency)
70 #if MHZ(48) == DT_PROP(SCG_CLOCK_NODE(firc_clk), clock_frequency)
72 #elif MHZ(52) == DT_PROP(SCG_CLOCK_NODE(firc_clk), clock_frequency)
74 #elif MHZ(56) == DT_PROP(SCG_CLOCK_NODE(firc_clk), clock_frequency)
76 #elif MHZ(60) == DT_PROP(SCG_CLOCK_NODE(firc_clk), clock_frequency)
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| /Zephyr-latest/boards/intel/ish/ |
| D | Kconfig.defconfig | 13 default 2000 if APIC_TIMER_TSC # APIC timer's frequency is 19.2 MHZ or 100 MHZ
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| /Zephyr-latest/soc/renesas/ra/ra4m1/ |
| D | soc.c | 28 #if HOCO_FREQ == MHZ(24)
30 #elif HOCO_FREQ == MHZ(32)
32 #elif HOCO_FREQ == MHZ(48)
34 #elif HOCO_FREQ == MHZ(64)
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| /Zephyr-latest/soc/nuvoton/npcx/common/ |
| D | soc_clock.h | 109 #if (OFMCLK == MHZ(120)) /* MCLkD must between 40 mhz to 50 mhz*/
111 #elif (OFMCLK <= MHZ(100) && OFMCLK >= MHZ(80))
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| /Zephyr-latest/soc/microchip/mec/mec15xx/ |
| D | soc.h | 10 #define SYSCLK_DEFAULT_IOSC_HZ MHZ(48)
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| /Zephyr-latest/soc/microchip/mec/mec174x/ |
| D | soc.h | 10 #define SYSCLK_DEFAULT_IOSC_HZ MHZ(96)
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| /Zephyr-latest/soc/microchip/mec/mec175x/ |
| D | soc.h | 10 #define SYSCLK_DEFAULT_IOSC_HZ MHZ(96)
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| /Zephyr-latest/soc/microchip/mec/mech172x/ |
| D | soc.h | 10 #define SYSCLK_DEFAULT_IOSC_HZ MHZ(96)
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| /Zephyr-latest/soc/nxp/kinetis/ke1xf/ |
| D | soc.c | 89 #if MHZ(2) == DT_PROP(SCG_CLOCK_NODE(sirc_clk), clock_frequency)
91 #elif MHZ(8) == DT_PROP(SCG_CLOCK_NODE(sirc_clk), clock_frequency)
107 #if MHZ(48) == DT_PROP(SCG_CLOCK_NODE(firc_clk), clock_frequency)
109 #elif MHZ(52) == DT_PROP(SCG_CLOCK_NODE(firc_clk), clock_frequency)
111 #elif MHZ(56) == DT_PROP(SCG_CLOCK_NODE(firc_clk), clock_frequency)
113 #elif MHZ(60) == DT_PROP(SCG_CLOCK_NODE(firc_clk), clock_frequency)
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| /Zephyr-latest/samples/net/zperf/src/ |
| D | nrf5340_cpu_boost.c | 30 LOG_INF("Starting %s with CPU frequency: %d MHz", CONFIG_BOARD, SystemCoreClock/MHZ(1)); in nrf53_cpu_boost()
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| /Zephyr-latest/drivers/spi/ |
| D | spi_nrfx_spim.c | 169 if (frequency >= MHZ(32) && (NRF_SPIM_HAS_32_MHZ_FREQ || NRF_SPIM_HAS_PRESCALER)) { in get_nrf_spim_frequency()
170 return MHZ(32); in get_nrf_spim_frequency()
171 } else if (frequency >= MHZ(16) && (NRF_SPIM_HAS_16_MHZ_FREQ || NRF_SPIM_HAS_PRESCALER)) { in get_nrf_spim_frequency()
172 return MHZ(16); in get_nrf_spim_frequency()
173 } else if (frequency >= MHZ(8)) { in get_nrf_spim_frequency()
174 return MHZ(8); in get_nrf_spim_frequency()
175 } else if (frequency >= MHZ(4)) { in get_nrf_spim_frequency()
176 return MHZ(4); in get_nrf_spim_frequency()
177 } else if (frequency >= MHZ(2)) { in get_nrf_spim_frequency()
178 return MHZ(2); in get_nrf_spim_frequency()
[all …]
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| /Zephyr-latest/soc/sifive/sifive_freedom/fu500/ |
| D | clock.c | 12 BUILD_ASSERT(MHZ(1000) == DT_PROP(DT_NODELABEL(coreclk), clock_frequency),
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