Searched refs:GD32_RESET_TIMER6 (Results 1 – 13 of 13) sorted by relevance
44 #define GD32_RESET_TIMER6 GD32_RESET_CONFIG(APB1RST, 5U) macro
48 #define GD32_RESET_TIMER6 GD32_RESET_CONFIG(APB1RST, 5U) macro
47 #define GD32_RESET_TIMER6 GD32_RESET_CONFIG(APB1RST, 5U) macro
52 #define GD32_RESET_TIMER6 GD32_RESET_CONFIG(APB1RST, 5U) macro
53 #define GD32_RESET_TIMER6 GD32_RESET_CONFIG(APB1RST, 5U) macro
58 #define GD32_RESET_TIMER6 GD32_RESET_CONFIG(APB1RST, 5U) macro
68 #define GD32_RESET_TIMER6 GD32_RESET_CONFIG(APB1RST, 5U) macro
336 resets = <&rctl GD32_RESET_TIMER6>;
402 resets = <&rctl GD32_RESET_TIMER6>;
401 resets = <&rctl GD32_RESET_TIMER6>;
343 resets = <&rctl GD32_RESET_TIMER6>;
367 resets = <&rctl GD32_RESET_TIMER6>;
495 resets = <&rctl GD32_RESET_TIMER6>;
