Searched refs:GD32_RESET_TIMER5 (Results 1 – 14 of 14) sorted by relevance
42 #define GD32_RESET_TIMER5 GD32_RESET_CONFIG(APB1RST, 4U) macro
43 #define GD32_RESET_TIMER5 GD32_RESET_CONFIG(APB1RST, 4U) macro
47 #define GD32_RESET_TIMER5 GD32_RESET_CONFIG(APB1RST, 4U) macro
46 #define GD32_RESET_TIMER5 GD32_RESET_CONFIG(APB1RST, 4U) macro
51 #define GD32_RESET_TIMER5 GD32_RESET_CONFIG(APB1RST, 4U) macro
52 #define GD32_RESET_TIMER5 GD32_RESET_CONFIG(APB1RST, 4U) macro
57 #define GD32_RESET_TIMER5 GD32_RESET_CONFIG(APB1RST, 4U) macro
67 #define GD32_RESET_TIMER5 GD32_RESET_CONFIG(APB1RST, 4U) macro
325 resets = <&rctl GD32_RESET_TIMER5>;
391 resets = <&rctl GD32_RESET_TIMER5>;
390 resets = <&rctl GD32_RESET_TIMER5>;
332 resets = <&rctl GD32_RESET_TIMER5>;
356 resets = <&rctl GD32_RESET_TIMER5>;
484 resets = <&rctl GD32_RESET_TIMER5>;
