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Searched refs:GD32_RESET_TIMER0 (Results 1 – 13 of 13) sorted by relevance

/Zephyr-latest/include/zephyr/dt-bindings/reset/
Dgd32f3x0.h32 #define GD32_RESET_TIMER0 GD32_RESET_CONFIG(APB2RST, 11U) macro
Dgd32vf103.h37 #define GD32_RESET_TIMER0 GD32_RESET_CONFIG(APB2RST, 11U) macro
Dgd32a50x.h63 #define GD32_RESET_TIMER0 GD32_RESET_CONFIG(APB2RST, 11U) macro
Dgd32e10x.h38 #define GD32_RESET_TIMER0 GD32_RESET_CONFIG(APB2RST, 11U) macro
Dgd32f403.h40 #define GD32_RESET_TIMER0 GD32_RESET_CONFIG(APB2RST, 11U) macro
Dgd32e50x.h40 #define GD32_RESET_TIMER0 GD32_RESET_CONFIG(APB2RST, 11U) macro
Dgd32f4xx.h91 #define GD32_RESET_TIMER0 GD32_RESET_CONFIG(APB2RST, 0U) macro
/Zephyr-latest/dts/arm/gd/gd32a50x/
Dgd32a50x.dtsi289 resets = <&rctl GD32_RESET_TIMER0>;
/Zephyr-latest/dts/riscv/gd/
Dgd32vf103.dtsi305 resets = <&rctl GD32_RESET_TIMER0>;
/Zephyr-latest/dts/arm/gd/gd32e50x/
Dgd32e50x.dtsi302 resets = <&rctl GD32_RESET_TIMER0>;
/Zephyr-latest/dts/arm/gd/gd32e10x/
Dgd32e10x.dtsi246 resets = <&rctl GD32_RESET_TIMER0>;
/Zephyr-latest/dts/arm/gd/gd32f403/
Dgd32f403.dtsi304 resets = <&rctl GD32_RESET_TIMER0>;
/Zephyr-latest/dts/arm/gd/gd32f4xx/
Dgd32f4xx.dtsi396 resets = <&rctl GD32_RESET_TIMER0>;