| /Zephyr-latest/boards/cypress/cy8ckit_062_ble/ |
| D | cy8ckit_062_ble_cy8c6347_m0_0_0_0.overlay | 10 uart-5 = &uart5;
14 zephyr,console = &uart5;
15 zephyr,shell-uart = &uart5;
19 &uart5 {
29 arduino_serial: &uart5 {};
|
| D | cy8ckit_062_ble_cy8c6347_m0_1_0_0.overlay | 31 &uart5 {
42 arduino_serial: &uart5 {};
|
| D | cy8ckit_062_ble_cy8c6347-pinctrl.dtsi | 9 /* Configure pin control bias mode for uart5 pins */
|
| /Zephyr-latest/boards/cypress/cy8ckit_062_wifi_bt/ |
| D | cy8ckit_062_wifi_bt_cy8c6247_m4.dts | 17 uart-5 = &uart5;
23 zephyr,console = &uart5;
24 zephyr,shell-uart = &uart5;
28 &uart5 {
|
| D | cy8ckit_062_wifi_bt_cy8c6247-pinctrl.dtsi | 9 /* Configure pin control bias mode for uart5 pins */
|
| /Zephyr-latest/boards/aspeed/ast1030_evb/ |
| D | ast1030_evb.dts | 15 zephyr,console = &uart5;
16 zephyr,shell-uart = &uart5;
25 &uart5 {
|
| /Zephyr-latest/boards/infineon/cy8cproto_063_ble/ |
| D | cy8cproto_063_ble.dts | 19 uart-5 = &uart5;
28 zephyr,console = &uart5;
29 zephyr,shell-uart = &uart5;
82 uart5: &scb5 { label
|
| D | cy8cproto_063_ble-pinctrl.dtsi | 7 /* Configure pin control bias mode for uart5 pins */
|
| /Zephyr-latest/boards/udoo/udoo_neo_full/ |
| D | udoo_neo_full_mcimx6x_m4.dts | 41 zephyr,console = &uart5;
42 zephyr,shell-uart = &uart5;
54 &uart5 {
|
| /Zephyr-latest/boards/adi/sdp_k1/ |
| D | adi_sdp_k1.dts | 18 zephyr,console = &uart5;
19 zephyr,shell-uart = &uart5;
82 &uart5 {
|
| /Zephyr-latest/boards/infineon/cy8cproto_062_4343w/ |
| D | cy8cproto_062_4343w.dts | 17 uart-5 = &uart5;
26 zephyr,console = &uart5;
27 zephyr,shell-uart = &uart5;
36 uart5: &scb5 { label
|
| D | cy8cproto_062_4343w-pinctrl.dtsi | 23 /* Configure pin control bias mode for uart5 pins */
|
| /Zephyr-latest/boards/infineon/cy8ckit_062s2_ai/ |
| D | cy8ckit_062s2_ai.dts | 17 zephyr,console = &uart5;
18 zephyr,shell-uart = &uart5;
91 uart5: &scb5 { label
|
| /Zephyr-latest/dts/arm/infineon/cat1a/legacy/ |
| D | pinctrl_cypress_psoc6.h | 65 * DT_CYPRESS_PIN(uart5, rx, 5, 0, act_6);
75 * DT_CYPRESS_PIN(uart5, rx, 5, 0, act_6, bias-pull-up, input-enable);
|
| /Zephyr-latest/dts/bindings/pinctrl/ |
| D | infineon,cat1-pinctrl.yaml | 86 &uart5 {
91 /* Configure pin control bias mode for uart5 pins */
|
| /Zephyr-latest/dts/arm/aspeed/ |
| D | ast10x0.dtsi | 42 uart5: serial@7e784000 { label
|
| /Zephyr-latest/boards/technexion/pico_pi/ |
| D | pico_pi_mcimx7d_m4.dts | 34 &uart5 {
|
| /Zephyr-latest/dts/arm/nxp/ |
| D | nxp_k22fx512.dtsi | 41 uart5: uart@400eb000 { label
|
| /Zephyr-latest/dts/arm/st/f3/ |
| D | stm32f302Xc.dtsi | 31 uart5: serial@40005000 { label
|
| /Zephyr-latest/dts/arm/st/f4/ |
| D | stm32f413.dtsi | 22 uart5: serial@40005000 { label
|
| /Zephyr-latest/dts/arm/st/g4/ |
| D | stm32g491.dtsi | 72 uart5: serial@40005000 { label
|
| /Zephyr-latest/dts/sparc/gaisler/ |
| D | gr716a.dtsi | 87 uart5: apbuart@80305000 { label
|
| /Zephyr-latest/boards/aspeed/ast1030_evb/doc/ |
| D | index.rst | 60 UART5 is configured for serial logs. The default serial setup is 115200 8N1.
|
| /Zephyr-latest/dts/arm64/ti/ |
| D | ti_am62x_a53.dtsi | 115 uart5: serial@2850000 { label
|
| /Zephyr-latest/soc/nxp/imx/imx6sx/ |
| D | soc.c | 42 #if DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(uart5)) in SOC_RdcInit()
44 RDC_SetPdapAccess(RDC, rdcPdapUart5, RDC_DT_VAL(uart5), false, false); in SOC_RdcInit()
|
