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/Zephyr-latest/dts/bindings/clock/
Dst,stm32wb0-rcc.yaml2 # SPDX-License-Identifier: Apache-2.0
5 STM32WB0 Reset and Clock controller node for STM32WB0 devices
6 This node is in charge of the system clock ('SYSCLK') source
9 compatible: "st,stm32wb0-rcc"
11 include: [clock-controller.yaml, base.yaml]
17 "#clock-cells":
20 clock-frequency:
24 default frequency in Hz for clock output
26 slow-clock:
29 Slow clock source selection.
[all …]
Despressif,esp32-rtc.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: ESP32 RTC (Power & Clock Controller Module) Module
6 compatible: "espressif,esp32-rtc"
8 include: [clock-controller.yaml, base.yaml]
14 fast-clk-src:
18 RTC fast clock source.
19 - 0: ESP32_RTC_FAST_CLK_SRC_XTAL_D2 - Main XTAL divided by 2 (C3/S3)
21 - 1: ESP32_RTC_FAST_CLK_SRC_RC_FAST - 8 MHz
23 - 0
24 - 1
[all …]
/Zephyr-latest/soc/atmel/sam/common/
DKconfig4 # SPDX-License-Identifier: Apache-2.0
11 bool "Use external crystal oscillator for slow clock"
14 the slow clock. Note that this adds a few seconds to boot time, as the
15 crystal needs to stabilize after power-up.
17 Says n if you do not need accurate and precise timers. The slow clock
21 bool "Use external crystal oscillator for main clock"
24 The main clock is being used to drive the PLL, and thus driving the
25 processor clock.
28 main clock. Note that this adds about a second to boot time, as the
29 crystal needs to stabilize after power-up.
[all …]
/Zephyr-latest/dts/bindings/i3c/
Dnxp,mcux-i3c.yaml4 # SPDX-License-Identifier: Apache-2.0
8 compatible: "nxp,mcux-i3c"
10 include: [i3c-controller.yaml, pinctrl-device.yaml]
19 i3c-od-scl-hz:
25 clk-divider:
27 description: Main clock divider for I3C
30 clk-divider-tc:
32 description: TC clock divider for I3C
35 clk-divider-slow:
37 description: Slow clock divider for I3C
[all …]
/Zephyr-latest/samples/sensor/lps22hh_i3c/boards/
Dmimxrt685_evk_mimxrt685s_cm33.overlay7 * cannot tolerate high clock speed. So slow
8 * down the clock.
10 i2c-scl-hz = <400000>;
11 i3c-scl-hz = <400000>;
12 i3c-od-scl-hz = <400000>;
14 clk-divider = <12>;
15 clk-divider-slow = <1>;
16 clk-divider-tc = <1>;
/Zephyr-latest/samples/sensor/lsm6dso_i2c_on_i3c/boards/
Dmimxrt685_evk_mimxrt685s_cm33.overlay7 * cannot tolerate high clock speed. So slow
8 * down the clock.
10 i2c-scl-hz = <400000>;
11 i3c-scl-hz = <400000>;
12 i3c-od-scl-hz = <400000>;
14 clk-divider = <12>;
15 clk-divider-slow = <1>;
16 clk-divider-tc = <1>;
/Zephyr-latest/samples/boards/espressif/xt_wdt/
DREADME.rst1 .. zephyr:code-sample:: esp32-xt-wdt
14 the XT WDT interrupt. Internally the hardware switch the RTC SLOW clock source from
23 * ESP32-C3
24 * ESP32-S2
25 * ESP32-S3
33 .. code-block:: console
35 west build -p -b esp32s3_devkitm/esp32s3/procpu samples/boards/espressif/xt_wdt
49 .. code-block:: console
53 .. code-block:: console
55 *** Booting Zephyr OS build v3.6.0-3896-gb4a7f061524f ***
[all …]
/Zephyr-latest/include/zephyr/dt-bindings/clock/
Desp32c2_clock.h4 * SPDX-License-Identifier: Apache-2.0
10 /* Supported CPU clock Sources */
27 /* Supported RTC fast clock sources */
31 /* Supported RTC slow clock sources */
36 /* RTC slow clock frequencies */
54 #define ESP32_TIMG1_MODULE 5 /* No timg1 on esp32c2, TODO: IDF-3825 */
Desp32c3_clock.h4 * SPDX-License-Identifier: Apache-2.0
10 /* Supported CPU clock Sources */
24 /* Supported RTC fast clock sources */
28 /* Supported RTC slow clock sources */
34 /* RTC slow clock frequencies */
Desp32s2_clock.h4 * SPDX-License-Identifier: Apache-2.0
10 /* Supported CPU clock Sources */
25 /* Supported RTC fast clock sources */
29 /* Supported RTC slow clock sources */
35 /* RTC slow clock frequencies */
Dkinetis_pcc.h4 * SPDX-License-Identifier: Apache-2.0
10 /* NXP Kinetis Peripheral Clock Controller IP sources */
11 #define KINETIS_PCC_SRC_NONE_OR_EXT 0 /* Clock off or external clock is used */
12 #define KINETIS_PCC_SRC_SOSC_ASYNC 1 /* System Oscillator async clock */
13 #define KINETIS_PCC_SRC_SIRC_ASYNC 2 /* Slow IRC async clock */
14 #define KINETIS_PCC_SRC_FIRC_ASYNC 3 /* Fast IRC async clock */
15 #define KINETIS_PCC_SRC_SPLL_ASYNC 6 /* System PLL async clock */
Desp32c6_clock.h4 * SPDX-License-Identifier: Apache-2.0
10 /* Supported CPU clock Sources */
24 /* Supported RTC fast clock sources */
28 /* Supported RTC slow clock frequencies */
34 /* RTC slow clock frequencies */
79 /* Peripherals clock managed by the modem_clock driver must be listed last */
Desp32_clock.h5 * SPDX-License-Identifier: Apache-2.0
11 /* Supported CPU clock Sources */
28 /* Supported RTC fast clock sources */
32 /* Supported RTC slow clock sources */
38 /* RTC slow clock frequencies */
Desp32s3_clock.h4 * SPDX-License-Identifier: Apache-2.0
10 /* Supported CPU clock Sources */
25 /* Supported RTC fast clock sources */
29 /* Supported RTC slow clock sources */
35 /* RTC slow clock frequencies */
/Zephyr-latest/tests/drivers/spi/spi_loopback/boards/
Dmec172xevb_assy6906.overlay4 * SPDX-License-Identifier: Apache-2.0
9 compatible = "microchip,xec-qmspi-ldma";
10 clock-frequency = <12000000>;
12 chip-select = <0>;
14 slow@0 {
15 compatible = "test-spi-loopback-slow";
17 spi-max-frequency = <500000>;
20 compatible = "test-spi-loopback-fast";
22 spi-max-frequency = <16000000>;
Ds32z2xxdc2_s32z270_rtu0.overlay4 * SPDX-License-Identifier: Apache-2.0
11 output-enable;
15 input-enable;
21 pinctrl-0 = <&spi0_default>;
22 pinctrl-names = "default";
23 clock-frequency = <100000000>;
26 slow@0 {
27 compatible = "test-spi-loopback-slow";
29 spi-max-frequency = <500000>;
33 compatible = "test-spi-loopback-fast";
[all …]
Ds32z2xxdc2_s32z270_rtu1.overlay4 * SPDX-License-Identifier: Apache-2.0
11 output-enable;
15 input-enable;
21 pinctrl-0 = <&spi0_default>;
22 pinctrl-names = "default";
23 clock-frequency = <100000000>;
26 slow@0 {
27 compatible = "test-spi-loopback-slow";
29 spi-max-frequency = <500000>;
33 compatible = "test-spi-loopback-fast";
[all …]
Dnucleo_h723zg.overlay4 * SPDX-License-Identifier: Apache-2.0
7 /* Set div-q to get test clk freq into acceptable SPI freq range */
9 /delete-property/ div-q;
10 div-q = <8>;
13 /* Define PLL1_Q as SPI1 kernel clock source */
15 /delete-property/ clocks;
18 slow@0 {
19 compatible = "test-spi-loopback-slow";
21 spi-max-frequency = <500000>;
24 compatible = "test-spi-loopback-fast";
[all …]
Dnucleo_g431rb.overlay4 * SPDX-License-Identifier: Apache-2.0
10 dma-names = "tx", "rx";
11 slow@0 {
12 compatible = "test-spi-loopback-slow";
14 spi-max-frequency = <500000>;
17 compatible = "test-spi-loopback-fast";
19 spi-max-frequency = <16000000>;
33 * Reduce bus clock speed to be able to reach
36 apb2-prescaler = <2>;
Dnucleo_g474re.overlay4 * SPDX-License-Identifier: Apache-2.0
9 * Reduce bus clock speed to be able
13 apb2-prescaler = <2>;
19 dma-names = "tx", "rx";
20 slow@0 {
21 compatible = "test-spi-loopback-slow";
23 spi-max-frequency = <500000>;
26 compatible = "test-spi-loopback-fast";
28 spi-max-frequency = <16000000>;
/Zephyr-latest/dts/arm/st/wb0/
Dstm32wb0.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv6-m.dtsi>
8 #include <zephyr/dt-bindings/i2c/i2c.h>
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/pwm/pwm.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/clock/stm32wb0_clock.h>
13 #include <zephyr/dt-bindings/reset/stm32wb0_reset.h>
14 #include <zephyr/dt-bindings/dma/stm32_dma.h>
25 zephyr,flash-controller = &flash;
[all …]
/Zephyr-latest/tests/drivers/pwm/pwm_loopback/boards/
Dfrdm_ke17z.overlay4 * SPDX-License-Identifier: Apache-2.0
12 drive-strength = "low";
13 slew-rate = "slow";
20 drive-strength = "low";
21 slew-rate = "slow";
27 * PTB14(J3-11) ---> PTE11(J2-2)
32 compatible = "test-pwm-loopback";
40 compatible = "nxp,ftm-pwm";
43 #pwm-cells = <3>;
44 pinctrl-0 = <&ftm0_default>;
[all …]
Dfrdm_ke17z512.overlay4 * SPDX-License-Identifier: Apache-2.0
12 drive-strength = "low";
13 slew-rate = "slow";
20 drive-strength = "low";
21 slew-rate = "slow";
27 * PTB14(J3-11) ---> PTE11(J2-11)
32 compatible = "test-pwm-loopback";
40 compatible = "nxp,ftm-pwm";
43 #pwm-cells = <3>;
44 pinctrl-0 = <&ftm0_default>;
[all …]
/Zephyr-latest/samples/boards/espressif/xt_wdt/src/
Dmain.c4 * SPDX-License-Identifier: Apache-2.0
33 LOG_ERR("Clock device is not ready"); in main()
34 return -EIO; in main()
39 return -EIO; in main()
47 LOG_INF("Current RTC SLOW clock rate: %d Hz", clk_rate); in main()
66 LOG_INF("Current RTC SLOW clock rate: %d Hz", clk_rate); in main()
/Zephyr-latest/soc/microchip/mec/
DKconfig5 # SPDX-License-Identifier: Apache-2.0
18 Boot-ROM. Use the full Microchip SPI image generator program for
19 authentication and all other Boot-ROM loader features. Refer to the MCHP
30 prompt "Clock rate to use for SPI flash"
33 This selects the SPI clock frequency that will be used for loading
37 bool "SPI flash clock rate of 12 MHz"
40 bool "SPI flash clock rate of 16 MHz"
43 bool "SPI flash clock rate of 24 MHz"
46 bool "SPI flash clock rate of 48 MHz"
65 bool "SPI flash operates full-duplex with frequency (< 25 MHz)"
[all …]

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