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/Zephyr-latest/dts/bindings/spi/
Dnxp,imx-flexspi.yaml1 # Copyright 2018-2023, NXP
2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "nxp,imx-flexspi"
8 include: [spi-controller.yaml, pinctrl-device.yaml]
17 ahb-bufferable:
23 ahb-cacheable:
29 ahb-prefetch:
34 ahb-read-addr-opt:
40 combination-mode:
46 sck-differential-clock:
[all …]
Datmel,sam0-spi.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "atmel,sam0-spi"
9 - name: spi-controller.yaml
10 - name: pinctrl-device.yaml
19 clock-names:
34 Optional TX & RX dma specifiers. Each specifier will have a phandle
36 trigger source.
38 For example dmas for TX, RX on SERCOM3
41 dma-names:
43 Required if the dmas property exists. This should be "tx" and "rx"
[all …]
/Zephyr-latest/dts/bindings/i2s/
Dnxp,mcux-i2s.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: NXP mcux SAI-I2S controller
6 compatible: "nxp,mcux-i2s"
8 include: [i2s-controller.yaml, pinctrl-device.yaml]
17 dma-names:
20 nxp,tx-dma-channel:
25 nxp,rx-dma-channel:
28 description: rx dma channel number
30 nxp,tx-sync-mode:
34 nxp,rx-sync-mode:
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/Zephyr-latest/drivers/ethernet/nxp_enet/
DKconfig3 # Copyright (c) 2016-2017 ARM Ltd
5 # SPDX-License-Identifier: Apache-2.0
62 - IPv4, UDP and TCP checksum (both Rx and Tx)
65 int "Number of RX buffers for ethernet driver"
69 Set the number of RX buffers provided to the NXP ENET driver.
79 int "NXP ENET RX thread stack size"
82 ENET RX thread stack size in bytes.
85 int "NXP ENET driver RX cooperative thread priority"
88 ENET MAC Driver handles RX in cooperative workqueue thread.
113 - IPv4, UDP and TCP checksum (both Rx and Tx)
[all …]
/Zephyr-latest/dts/bindings/i2c/
Datmel,sam0-i2c.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "atmel,sam0-i2c"
9 - name: i2c-controller.yaml
10 - name: pinctrl-device.yaml
22 clock-names:
27 Optional TX & RX dma specifiers. Each specifier will have a phandle
29 trigger source.
31 For example dmas for TX, RX on SERCOM3
34 dma-names:
36 Required if the dmas property exists. This should be "tx" and "rx"
[all …]
/Zephyr-latest/drivers/ethernet/
DKconfig.stm32_hal5 # SPDX-License-Identifier: Apache-2.0
43 int "RX thread stack size"
46 RX thread stack size
49 int "STM32 Ethernet RX Thread Priority"
52 This option allows to configure the priority of the RX thread that
83 Set the RX idle timeout period in milliseconds after which the
84 PHY's carrier status is re-evaluated.
93 bool "Use TX and RX hardware checksum"
119 bool "STM32 HAL PTP clock driver support"
123 Enable STM32 PTP clock support.
[all …]
/Zephyr-latest/dts/bindings/serial/
Drenesas,smartbond-uart.yaml3 compatible: "renesas,smartbond-uart"
5 include: [uart-controller.yaml, pinctrl-device.yaml]
14 periph-clock-config:
16 description: Peripheral clock register configuration (COM domain)
19 current-speed:
24 - 4800
25 - 9600
26 - 14400
27 - 19200
28 - 28800
[all …]
Dmicrochip,xec-uart.yaml3 compatible: "microchip,xec-uart"
5 include: [uart-controller.yaml, pinctrl-device.yaml]
27 description: UART Power Clock Reset(PCR) register index and bit position
29 pinctrl-0:
32 pinctrl-names:
35 wakerx-gpios:
36 type: phandle-array
37 description: GPIO configured as UART RX wake source
/Zephyr-latest/dts/arm/nuvoton/npcx/
Dnpcx4.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include "npcx4/npcx4-alts-map.dtsi"
9 /* npcx4 series mapping table between MIWU wui bits and source device */
10 #include "npcx4/npcx4-miwus-wui-map.dtsi"
12 #include "npcx4/npcx4-miwus-int-map.dtsi"
14 #include "npcx4/npcx4-espi-vws-map.dtsi"
15 /* npcx4 series low-voltage io controls mapping table */
16 #include "npcx4/npcx4-lvol-ctrl-map.dtsi"
18 #include "zephyr/dt-bindings/reset/npcx4_reset.h"
26 cpu-power-states = <&suspend_to_idle0>;
[all …]
Dnpcx9.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include "npcx9/npcx9-alts-map.dtsi"
9 /* NPCX9 series mapping table between MIWU wui bits and source device */
10 #include "npcx9/npcx9-miwus-wui-map.dtsi"
12 #include "npcx9/npcx9-miwus-int-map.dtsi"
14 #include "npcx9/npcx9-espi-vws-map.dtsi"
15 /* NPCX9 series low-voltage io controls mapping table */
16 #include "npcx9/npcx9-lvol-ctrl-map.dtsi"
24 cpu-power-states = <&suspend_to_idle0 &suspend_to_idle1>;
27 power-states {
[all …]
/Zephyr-latest/drivers/serial/
Duart_stm32.h2 * Copyright (c) 2016 Open-RnD Sp. z o.o.
4 * SPDX-License-Identifier: Apache-2.0
32 /* clock subsystem driving this peripheral */
34 /* number of clock subsystems */
38 /* enable tx/rx pin swap */
40 /* enable rx pin inversion */
61 /* Device defined as wake-up source */
89 /* clock device */
90 const struct device *clock; member
/Zephyr-latest/boards/arm/mps3/
Dmps3_common_soc_peripheral.dtsi2 * Copyright (c) 2019-2021 Linaro Limited
3 * Copyright 2024 Arm Limited and/or its affiliates <open-source-office@arm.com>
5 * SPDX-License-Identifier: Apache-2.0
8 sysclk: system-clock {
9 compatible = "fixed-clock";
10 clock-frequency = <25000000>;
11 #clock-cells = <0>;
15 compatible = "arm,cmsdk-gpio";
18 gpio-controller;
19 #gpio-cells = <2>;
[all …]
/Zephyr-latest/boards/nxp/frdm_rw612/
Dfrdm_rw612_common.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include "frdm_rw612-pinctrl.dtsi"
15 usart-0 = &flexcomm3;
16 i2c-0 = &flexcomm2;
17 pwm-0 = &sctimer;
24 zephyr,shell-uart = &flexcomm3;
28 compatible = "gpio-leds";
36 compatible = "nxp,lpc-usart";
38 current-speed = <115200>;
39 pinctrl-0 = <&pinmux_flexcomm3_usart>;
[all …]
/Zephyr-latest/soc/microchip/mec/common/reg/
Dmec_uart.h4 * SPDX-License-Identifier: Apache-2.0
43 /* FIFO Control Register, Write-Only */
46 #define MCHP_UART_FCR_EXRF 0x01u /* Enable TX & RX FIFO's */
47 #define MCHP_UART_FCR_CLR_RX_FIFO 0x02u /* Clear RX FIFO, bit is self-clearing */
48 #define MCHP_UART_FCR_CLR_TX_FIFO 0x04u /* Clear TX FIFO, bit is self-clearing */
50 #define MCHP_UART_FCR_RX_FIFO_LVL_MASK 0xc0u /* RX FIFO trigger level mask */
56 /* Interrupt Identification Register, Read-Only */
67 * Highest-1. RX data available or RX FIFO trigger level reached
68 * Highest-2. RX timeout
69 * Highest-3. TX Holding register empty
[all …]
/Zephyr-latest/soc/snps/arc_iot/
Dsysconf.h4 * SPDX-License-Identifier: Apache-2.0
19 volatile uint32_t AHBCLKDIV; /* AHB clock divisor */
20 volatile uint32_t APBCLKDIV; /* APB clock divisor */
21 volatile uint32_t APBCLKEN; /* APB module clock enable */
22 volatile uint32_t CLKODIV; /* AHB clock output enable and divisor set */
26 volatile uint32_t AHBCLKDIV_SEL; /* AHB clock divisor select */
27 volatile uint32_t CLKSEL; /* main clock source select */
31 volatile uint32_t AHBCLKEN; /* AHB module clock enable */
34 volatile uint32_t I2S_RX_SCLKDIV; /* I2S RX SCLK divisor */
35 volatile uint32_t I2S_RX_SCLKSEL; /* I2S RX SCLK source select */
[all …]
/Zephyr-latest/dts/arm/nxp/
Dnxp_k6x.dtsi1 /* SPDX-License-Identifier: Apache-2.0 */
4 #include <arm/armv7-m.dtsi>
5 #include <zephyr/dt-bindings/adc/adc.h>
6 #include <zephyr/dt-bindings/clock/kinetis_sim.h>
7 #include <zephyr/dt-bindings/clock/kinetis_mcg.h>
8 #include <zephyr/dt-bindings/gpio/gpio.h>
9 #include <zephyr/dt-bindings/i2c/i2c.h>
18 zephyr,flash-controller = &ftfe;
22 #address-cells = <1>;
23 #size-cells = <0>;
[all …]
Dnxp_rt10xx.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <arm/armv7-m.dtsi>
9 #include <zephyr/dt-bindings/adc/adc.h>
10 #include <zephyr/dt-bindings/clock/imx_ccm.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/i2c/i2c.h>
13 #include <zephyr/dt-bindings/pwm/pwm.h>
14 #include <zephyr/dt-bindings/memory-controller/nxp,flexram.h>
19 die-temp0 = &tempmon;
23 #address-cells = <1>;
[all …]
Dnxp_ke1xf.dtsi2 * Copyright (c) 2019-2021 Vestas Wind Systems A/S
4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv7-m.dtsi>
8 #include <zephyr/dt-bindings/adc/adc.h>
9 #include <zephyr/dt-bindings/clock/kinetis_pcc.h>
10 #include <zephyr/dt-bindings/clock/kinetis_scg.h>
11 #include <zephyr/dt-bindings/gpio/gpio.h>
12 #include <zephyr/dt-bindings/i2c/i2c.h>
20 zephyr,flash-controller = &ftfe;
24 #address-cells = <1>;
[all …]
Dnxp_mcxn23x_common.dtsi4 * SPDX-License-Identifier: Apache-2.0
8 #include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
9 #include <zephyr/dt-bindings/reset/nxp_syscon_reset_common.h>
10 #include <zephyr/dt-bindings/gpio/gpio.h>
11 #include <arm/armv8-m.dtsi>
12 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
16 #address-cells = <1>;
17 #size-cells = <0>;
20 compatible = "arm,cortex-m33f";
22 #address-cells = <1>;
[all …]
/Zephyr-latest/boards/seeed/xiao_esp32s3/
Dxiao_esp32s3_procpu_sense.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
13 compatible = "seeed,xiao-esp32s3";
22 clock-frequency = <I2C_BITRATE_STANDARD>;
23 pinctrl-0 = <&i2c1_default>;
24 pinctrl-names = "default";
30 clock-rate-control = <0x80>;
33 remote-endpoint-label = "dvp_ep_in";
45 cam-clk = <10000000>;
46 pinctrl-0 = <&lcd_cam_default>;
[all …]
/Zephyr-latest/drivers/disk/
DKconfig.sdmmc3 # SPDX-License-Identifier: Apache-2.0
57 overrun (RX mode) errors.
66 bool "Runtime SDMMC 48MHz clock check"
70 Enable SDMMC clock 48MHz configuration runtime check.
75 module-str = sdmmc
76 source "subsys/logging/Kconfig.template.log_config"
/Zephyr-latest/drivers/i2s/
Di2s_nrfx.c4 * SPDX-License-Identifier: Apache-2.0
33 struct stream_cfg rx; member
39 bool stop; /* stop after the current (TX or RX) block */
40 bool discard_rx; /* discard further RX blocks */
59 /* Finds the clock settings that give the frame clock frequency closest to
81 (NRF_I2S_HAS_CLKCONFIG && drv_cfg->clk_src == ACLK) in find_suitable_clock()
83 * make sure that the ACLK clock source is only used when it is in find_suitable_clock()
84 * available and only with the "hfclkaudio-frequency" property in find_suitable_clock()
89 ? DT_PROP_OR(DT_NODELABEL(clock), hfclkaudio_frequency, 0) in find_suitable_clock()
91 uint32_t bits_per_frame = 2 * i2s_cfg->word_size; in find_suitable_clock()
[all …]
/Zephyr-latest/boards/nxp/frdm_ke17z512/
Dfrdm_ke17z512.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
10 #include "frdm_ke17z512-pinctrl.dtsi"
11 #include <zephyr/dt-bindings/input/input-event-codes.h>
12 #include <zephyr/dt-bindings/pwm/pwm.h>
21 zephyr,code-partition = &slot0_partition;
22 zephyr,uart-mcumgr = &lpuart2;
24 zephyr,shell-uart = &lpuart2;
34 pwm-led0 = &red_pwm_led;
35 pwm-led1 = &green_pwm_led;
[all …]
/Zephyr-latest/boards/nxp/mimxrt595_evk/
Dmimxrt595_evk_mimxrt595s_cm33.dts2 * Copyright 2022-2023, NXP
4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
10 #include <zephyr/dt-bindings/input/input-event-codes.h>
12 #include "mimxrt595_evk_mimxrt595s_cm33-pinctrl.dtsi"
16 model = "NXP MIMXRT595-EVK board";
25 usart-0 = &flexcomm0;
30 pwm-0 = &sc_timer;
31 dmic-dev = &dmic0;
32 mcuboot-button0 = &user_button_1;
[all …]
/Zephyr-latest/dts/bindings/espi/
Dnuvoton,npcx-espi.yaml2 # SPDX-License-Identifier: Apache-2.0
4 description: Nuvoton, NPCX-eSPI node
6 compatible: "nuvoton,npcx-espi"
8 include: [espi-controller.yaml, pinctrl-device.yaml]
17 description: configurations of device source clock controller
19 pinctrl-0:
22 pinctrl-names:
25 espi-rst-wui:
29 Mapping table between Wake-Up Input (WUI) and ESPI_RST signal.
32 espi-rst-wui = <&wui_cr_sin1>;
[all …]

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