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/Zephyr-latest/dts/bindings/bluetooth/
Dzephyr,bt-hci-spi.yaml1 # Copyright (c) 2018, I-SENSE group of ICCS
2 # SPDX-License-Identifier: Apache-2.0
8 compatible: "zephyr,bt-hci-spi"
10 include: [spi-device.yaml, bt-hci.yaml]
13 irq-gpios:
14 type: phandle-array
17 reset-gpios:
18 type: phandle-array
21 reset-assert-duration-ms:
24 Minimum duration to hold the reset-gpios pin low for.
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/Zephyr-latest/soc/nordic/nrf52/
DKconfig3 # Copyright (c) 2016-2023 Nordic Semiconductor ASA
4 # SPDX-License-Identifier: Apache-2.0
42 regulator-initial-mode = <NRF5X_REG_MODE_DCDC>;
62 bool "[DEPRECATED] GPIO as pin reset (reset button)"
69 gpio-as-nreset;
73 bool "The instruction cache (I-Cache)"
78 int "Anomaly 132 workaround delay (microseconds)"
84 window after stopping (230 us to 330 us). Software reset also stops the
86 to start at reboot. A delay is added before starting LF clock to ensure
87 that anomaly conditions are not met. Delay should be long enough to ensure
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/Zephyr-latest/dts/bindings/fpga/
Dlattice,ice40-fpga-base.yaml2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "lattice,ice40-fpga-base"
8 include: spi-device.yaml
11 cdone-gpios:
12 type: phandle-array
17 cdone-gpios = <&gpio0 0 0>;
18 creset-gpios:
19 type: phandle-array
22 Configuration Reset input on iCE40.
24 creset-gpios = <&gpio0 1 GPIO_PUSH_PULL);
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/Zephyr-latest/dts/bindings/led_strip/
Dws2812.yaml4 # SPDX-License-Identifier: Apache-2.0
13 https://wp.josh.com/2014/05/13/ws2812-neopixels-are-not-so-finicky-once-you-get-to-know-them/
19 MOSI line. Use the worldsemi,ws2812-spi.yaml or
20 worldsemi,ws2812-gpio.yaml bindings instead of this file after
26 For the control signal (waveform) each bit is described with a 1.2 us pulse:
31 There is a +/- 80 ns tolerance for each timing.
33 The latch/reset delay is 250 us and it must be set using the reset-delay
35 using the color-mapping property.
37 include: led-strip.yaml
40 reset-delay:
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/Zephyr-latest/dts/bindings/mfd/
Dinfineon,tle9104.yaml4 # SPDX-License-Identifier: Apache-2.0
7 description: Infineon TLE9104 4-channel powertrain switch
11 include: spi-device.yaml
16 en-gpios:
17 type: phandle-array
20 resn-gpios:
21 type: phandle-array
22 description: "GPIO for reset"
24 in1-gpios:
25 type: phandle-array
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/Zephyr-latest/dts/bindings/regulator/
Dnxp,vref.yaml1 # Copyright 2023-2024 NXP
2 # SPDX-License-Identifier: Apache-2.0
9 - name: base.yaml
10 - name: regulator.yaml
11 property-allowlist:
12 - regulator-name
13 - regulator-init-microvolt
14 - regulator-min-microvolt
15 - regulator-max-microvolt
16 - regulator-initial-mode
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/Zephyr-latest/soc/espressif/esp32/
DKconfig2 # SPDX-License-Identifier: Apache-2.0
35 int "Extra delay in deep sleep wake stub (in us)"
43 without any extra delay, this time is approximately 900us, although
46 By default extra delay is set to 2000us. When optimizing startup time
50 console after deep sleep reset, try increasing this value.
/Zephyr-latest/dts/bindings/sensor/
Dti,ina237.yaml4 # SPDX-License-Identifier: Apache-2.0
9 The <zephyr/dt-bindings/sensor/ina237.h> file should be included in the
15 include: ti,ina23x-common.yaml
26 delay for initial ADC conversion, shunt full scale range
31 adc-config:
41 alert-config:
43 description: Diag alert register, default matches the power-on reset value
45 adc-mode:
49 Default is the power-on reset value.
52 - "Shutdown single shot"
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/Zephyr-latest/boards/renesas/da1469x_dk_pro/dts/
Dda1469x_dk_pro_psram.overlay4 * SPDX-License-Identifier: Apache-2.0
9 sram-ext = &memc;
17 /* QSPIC settings for the APS6404L-3SQR QSPI PSRAM memory in QPI mode. */
20 is-ram;
21 dev-size = <DT_SIZE_M(64)>;
22 dev-type = <0x5D>;
23 dev-id = <0x0D>;
24 dev-density = <0xE040>;
25 reset-delay-us = <50>;
26 read-cs-idle-min-ns = <18>;
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/Zephyr-latest/drivers/led_strip/
DKconfig.ws28124 # SPDX-License-Identifier: Apache-2.0
8 # https://wp.josh.com/2014/05/13/ws2812-neopixels-are-not-so-finicky-once-you-get-to-know-them/
29 delay. The reset delay has a coarse resolution of ~20us.
33 # Only an Cortex-M inline assembly implementation for the nRF91, nRF51,
41 controlling with GPIO. The GPIO driver does bit-banging with inline
49 DT_CHOSEN_LED_STRIP := zephyr,led-strip
53 int "Delay 1 bit high pulse"
54 default $(dt_node_int_prop_int,$(DT_CHOSEN_LED_STRIP_PATH),delay-t1h) \
55 if $(dt_node_has_prop,$(DT_CHOSEN_LED_STRIP_PATH),delay-t1h)
56 default $(div,$(mul,700,$(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)),1000000000) \
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/Zephyr-latest/drivers/fpga/
Dfpga_ice40_bitbang.c5 * SPDX-License-Identifier: Apache-2.0
30 * restore the default pinctrl settings. On some higher-end microcontrollers
34 * However, on lower-end microcontrollers, the amount of time that elapses
36 * leaves us with the bitbanging option. Of course, on lower-end
40 * in order to bitbang on lower-end microcontrollers, we actually require
56 * This is a calibrated delay loop used to achieve a 1 MHz SPI_CLK frequency
61 * lattice,ice40-fpga.yaml for details.
65 for (; n > 0; --n) { in fpga_ice40_delay()
70 static void fpga_ice40_send_clocks(size_t delay, volatile gpio_port_pins_t *set, in fpga_ice40_send_clocks() argument
73 for (; n > 0; --n) { in fpga_ice40_send_clocks()
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Dfpga_ice40_spi.c4 * SPDX-License-Identifier: Apache-2.0
30 struct fpga_ice40_data *data = dev->data; in fpga_ice40_load()
32 const struct fpga_ice40_config *config = dev->config; in fpga_ice40_load()
35 memcpy(&bus, &config->bus, sizeof(bus)); in fpga_ice40_load()
45 if (data->loaded && crc == data->crc) { in fpga_ice40_load()
46 LOG_WRN("already loaded with image CRC32c: 0x%08x", data->crc); in fpga_ice40_load()
49 key = k_spin_lock(&data->lock); in fpga_ice40_load()
52 data->crc = 0; in fpga_ice40_load()
53 data->loaded = false; in fpga_ice40_load()
54 fpga_ice40_crc_to_str(0, data->info); in fpga_ice40_load()
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/Zephyr-latest/tests/drivers/build_all/input/
Dapp.overlay4 * SPDX-License-Identifier: Apache-2.0
7 #include <zephyr/dt-bindings/input/input-event-codes.h>
11 #address-cells = <1>;
12 #size-cells = <1>;
17 #io-channel-cells = <1>;
18 #address-cells = <1>;
19 #size-cells = <0>;
26 zephyr,acquisition-time = <ADC_ACQ_TIME_DEFAULT>;
32 gpio-controller;
34 #gpio-cells = <0x2>;
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/Zephyr-latest/tests/drivers/timer/nrf_rtc_timer/src/
Dmain.c4 * SPDX-License-Identifier: Apache-2.0
15 uint32_t delay; member
62 while (overflow_count--) { in inject_overflow()
75 uint64_t diff = (now - expire_time); in timeout_handler()
77 zassert_true(diff <= data->delay, in timeout_handler()
80 now, data->target_time, expire_time); in timeout_handler()
82 if ((expire_time >= data->target_time) && in timeout_handler()
83 (expire_time <= (data->target_time + data->window))) { in timeout_handler()
84 data->err = 0; in timeout_handler()
95 .delay = ext_window ? 100 : 2, in test_timeout()
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/Zephyr-latest/drivers/timer/
Darcv2_timer0.c2 * Copyright (c) 2014-2015 Wind River Systems, Inc.
5 * SPDX-License-Identifier: Apache-2.0
51 #define MAX_TICKS ((COUNTER_MAX / CYC_PER_TICK) - 1)
98 * the overflow_cycles must be reset to zero.
168 * - reprogramming of LIMIT must be clearing the COUNT
169 * - ISR must be clearing the 'overflow_cycles' counter.
170 * - no more than one counter-wrap has occurred between
171 * - the timer reset or the last time the function was called
172 * - and until the current call of the function is completed.
173 * - the function is invoked with interrupts disabled.
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Dcortex_m_systick.c4 * SPDX-License-Identifier: Apache-2.0
20 #define MAX_TICKS ((k_ticks_t)(COUNTER_MAX / CYC_PER_TICK) - 1)
25 * reliably" -- it becomes the minimum value of the LOAD register, and
61 * Additions/subtractions/comparisons of 64-bits values on 32-bits systems
63 * cycle_count and announced_cycles is stored in a 32-bit variable before
75 * the overflow_cyc must be reset to zero.
84 * case because the Cortex-m SysTick is not clocked in the low power
102 * re-program the SysTick.LOAD register, in sys_clock_set_timeout().
109 * - reprogramming of SysTick.LOAD must be clearing the SysTick.COUNTER
111 * - ISR must be clearing the 'overflow_cyc' counter.
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/Zephyr-latest/drivers/bluetooth/hci/
Dspi.c1 /* spi.c - SPI based Bluetooth driver */
8 * SPDX-License-Identifier: Apache-2.0
54 #define SPI_MAX_MSG_LEN 255 /* As defined by X-NUCLEO-IDB04A1 BSP */
62 #define MAX_MTU (SPI_MAX_MSG_LEN - H4_HDR_SIZE - BT_L2CAP_HDR_SIZE - BT_HCI_ACL_HDR_SIZE)
156 return -EINVAL; in bt_spi_get_header()
244 struct bt_spi_data *hci = dev->data; in bt_spi_rx_thread()
265 /* Delay here is rounded up to next tick */ in bt_spi_rx_thread()
273 /* Consider increasing controller-data-delay-us in bt_spi_rx_thread()
297 hci->recv(dev, buf); in bt_spi_rx_thread()
313 if (buf->len >= SPI_MAX_MSG_LEN) { in bt_spi_send()
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/Zephyr-latest/drivers/ethernet/
Deth_w5500_priv.h1 /* W5500 Stand-alone Ethernet Controller with SPI
6 * SPDX-License-Identifier: Apache-2.0
21 #define MR_RST 0x80 /* S/W reset */
23 #define MR_AI 0x02 /* Address Auto-Increment */
67 #define W5500_RTR 0x0019 /* Retry Time-value Register */
80 /* Delay for PHY write/read operations (25.6 us) */
85 struct gpio_dt_spec reset; member
/Zephyr-latest/boards/st/st25dv_mb1283_disco/
Dst25dv_mb1283_disco.dts4 * SPDX-License-Identifier: Apache-2.0
7 /dts-v1/;
9 #include "st/f4/stm32f405vgtx-pinctrl.dtsi"
10 #include <zephyr/dt-bindings/input/input-event-codes.h>
11 #include <zephyr/dt-bindings/display/ili9xxx.h>
19 zephyr,shell-uart = &usart6;
26 compatible = "gpio-leds";
36 compatible = "gpio-keys";
69 compatible = "zephyr,mipi-dbi-spi";
70 reset-gpios = <&gpioc 1 GPIO_ACTIVE_HIGH>;
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/Zephyr-latest/dts/bindings/memory-controllers/
Drenesas,smartbond-nor-psram.yaml2 # SPDX-License-Identifier: Apache-2.0
8 compatible: "renesas,smartbond-nor-psram"
14 is-ram:
19 dev-size:
25 dev-type:
31 dev-density:
40 dev-id:
46 reset-delay-us:
50 Time in microseconds (us) the memory device can accept the next command following a SW reset.
52 read-cs-idle-min-ns:
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/Zephyr-latest/subsys/bluetooth/controller/ll_sw/nordic/hal/nrf5/radio/
Dradio.c2 * Copyright (c) 2016 - 2020 Nordic Semiconductor ASA
5 * SPDX-License-Identifier: Apache-2.0
9 #include <zephyr/dt-bindings/gpio/gpio.h>
84 /* These headers require the above gpiote-related variables to be declared. */
131 NRF_DT_CHECK_GPIO_CTLR_IS_SOC(FEM_NODE, pdn_gpios, "pdn-gpios");
171 NRF_GPIO_PA->DIRSET = BIT(NRF_GPIO_PA_PIN); in radio_setup()
173 NRF_GPIO_PA->OUTSET = BIT(NRF_GPIO_PA_PIN); in radio_setup()
175 NRF_GPIO_PA->OUTCLR = BIT(NRF_GPIO_PA_PIN); in radio_setup()
180 NRF_GPIO_LNA->DIRSET = BIT(NRF_GPIO_LNA_PIN); in radio_setup()
186 NRF_GPIO_PDN->DIRSET = BIT(NRF_GPIO_PDN_PIN); in radio_setup()
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/Zephyr-latest/subsys/sd/
Dsd.c4 * SPDX-License-Identifier: Apache-2.0
26 /* Reset card with CMD0 */ in sd_idle()
32 return sdhc_request(card->sdhc, &cmd, NULL); in sd_idle()
38 * - CMD0 (SD reset)
39 * - CMD8 (SD voltage check)
47 /* Reset card with CMD0 */ in sd_send_interface_condition()
60 ret = sdhc_request(card->sdhc, &cmd, NULL); in sd_send_interface_condition()
66 if (card->host_props.is_spi) { in sd_send_interface_condition()
78 return -ENOTSUP; in sd_send_interface_condition()
81 card->flags |= SD_SDHC_FLAG; in sd_send_interface_condition()
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/Zephyr-latest/drivers/display/
Ddisplay_hx8394.c4 * SPDX-License-Identifier: Apache-2.0
149 0x73, /* SPON delay */
150 0x74, /* SPOFF delay */
151 0x73, /* CON delay */
152 0x74, /* COFF delay */
153 0x73, /* CON1 delay */
154 0x74, /* COFF1 delay */
161 0x73, /* SPON_MPU delay */
162 0x74, /* SPOFF_MPU delay */
163 0x73, /* CON_MPU delay */
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/Zephyr-latest/samples/drivers/jesd216/src/
Dmain.c4 * SPDX-License-Identifier: Apache-2.0
40 [JESD216_MODE_111] = "1-1-1",
41 [JESD216_MODE_112] = "1-1-2",
42 [JESD216_MODE_114] = "1-1-4",
43 [JESD216_MODE_118] = "1-1-8",
44 [JESD216_MODE_122] = "1-2-2",
45 [JESD216_MODE_144] = "1-4-4",
46 [JESD216_MODE_188] = "1-8-8",
47 [JESD216_MODE_222] = "2-2-2",
48 [JESD216_MODE_444] = "4-4-4",
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/Zephyr-latest/dts/arm/nxp/
Dnxp_lpc55S3x_common.dtsi4 * SPDX-License-Identifier: Apache-2.0
7 #include <arm/armv8-m.dtsi>
8 #include <zephyr/dt-bindings/adc/adc.h>
9 #include <zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h>
10 #include <zephyr/dt-bindings/gpio/gpio.h>
11 #include <zephyr/dt-bindings/i2c/i2c.h>
12 #include <zephyr/dt-bindings/inputmux/inputmux_trigger_ports.h>
14 #include <zephyr/dt-bindings/reset/nxp_syscon_reset_common.h>
18 #address-cells = <1>;
19 #size-cells = <0>;
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