1# Copyright (c) 2022 Meta
2# SPDX-License-Identifier: Apache-2.0
3
4description: Lattice iCE40 FPGA base
5
6compatible: "lattice,ice40-fpga-base"
7
8include: spi-device.yaml
9
10properties:
11  cdone-gpios:
12    type: phandle-array
13    required: true
14    description: |
15      Configuration Done output from iCE40.
16      Example usage:
17      cdone-gpios = <&gpio0 0 0>;
18  creset-gpios:
19    type: phandle-array
20    required: true
21    description: |
22      Configuration Reset input on iCE40.
23      Example usage:
24      creset-gpios = <&gpio0 1 GPIO_PUSH_PULL);
25  creset-delay-us:
26    type: int
27    default: 1
28    description: |
29      Delay (in microseconds) between asserting CRESET_B and releasing CRESET_B.
30      The datasheet specifies a minimum of 200ns, therefore the default is set
31      to 1us.
32  config-delay-us:
33    type: int
34    default: 1200
35    description: |
36      Delay (in microseconds) after releasing CRESET_B to clear internal configuration memory.
37      The datasheet specifies a minimum of 1200us, which is the default.
38  leading-clocks:
39    type: int
40    default: 8
41    description: |
42      Prior to sending the bitstream, issue this number of leading clocks with SPI_CS pulled high.
43      The datasheet specifies 8 dummy cycles, which is the default.
44  trailing-clocks:
45    type: int
46    default: 49
47    description: |
48      After sending the bitstream, issue this number of trailing clocks with SPI_CS pulled high.
49      The datasheet specifies 49 dummy cycles, which is the default.
50