| /Zephyr-Core-3.5.0/dts/arm/cypress/ |
| D | psoc6-pinctrl.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
13 DT_CYPRESS_HSIOM(spi0, mosi, 0, 2, act_8, drive-push-pull);
14 DT_CYPRESS_HSIOM(spi0, miso, 0, 3, act_8, input-enable);
15 DT_CYPRESS_HSIOM(spi0, clk, 0, 4, act_8, drive-push-pull);
16 DT_CYPRESS_HSIOM(spi0, sel0, 0, 5, act_8, drive-push-pull);
17 DT_CYPRESS_HSIOM(spi0, sel1, 0, 0, act_8, drive-push-pull);
18 DT_CYPRESS_HSIOM(spi0, sel2, 0, 1, act_8, drive-push-pull);
19 DT_CYPRESS_HSIOM(spi1, mosi, 10, 0, act_8, drive-push-pull);
20 DT_CYPRESS_HSIOM(spi1, miso, 10, 1, act_8, input-enable);
21 DT_CYPRESS_HSIOM(spi1, clk, 10, 2, act_8, drive-push-pull);
[all …]
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| /Zephyr-Core-3.5.0/boards/arm/apollo4p_evb/ |
| D | apollo4p_evb-pinctrl.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
7 #include <dt-bindings/pinctrl/ambiq-apollo4-pinctrl.h>
16 input-enable;
22 drive-open-drain;
23 drive-strength = "0.5";
24 bias-pull-up;
30 drive-open-drain;
31 drive-strength = "0.5";
32 bias-pull-up;
38 drive-open-drain;
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| /Zephyr-Core-3.5.0/boards/arm/apollo4p_blue_kxr_evb/ |
| D | apollo4p_blue_kxr_evb-pinctrl.dtsi | 4 * SPDX-License-Identifier: Apache-2.0
7 #include <dt-bindings/pinctrl/ambiq-apollo4-pinctrl.h>
16 input-enable;
22 drive-open-drain;
23 drive-strength = "0.5";
24 bias-pull-up;
30 drive-open-drain;
31 drive-strength = "0.5";
32 bias-pull-up;
38 drive-open-drain;
[all …]
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| /Zephyr-Core-3.5.0/boards/arm/xmc47_relax_kit/ |
| D | xmc47_relax_kit-pinctrl.dtsi | 3 * SPDX-License-Identifier: Apache-2.0
6 #include <infineon/xmc4700_F144x2048-pinctrl.dtsi>
9 drive-strength = "strong-soft-edge";
10 drive-push-pull;
15 drive-strength = "strong-soft-edge";
20 drive-strength = "strong-soft-edge";
21 drive-push-pull;
26 drive-strength = "strong-soft-edge";
31 drive-strength = "strong-soft-edge";
32 drive-push-pull;
[all …]
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| /Zephyr-Core-3.5.0/boards/arm/cy8cproto_062_4343w/ |
| D | cy8cproto_062_4343w-pinctrl.dtsi | 3 * SPDX-License-Identifier: Apache-2.0
8 drive-push-pull;
12 input-enable;
16 drive-push-pull;
20 input-enable;
25 drive-push-pull;
29 input-enable;
|
| /Zephyr-Core-3.5.0/boards/arm/xmc45_relax_kit/ |
| D | xmc45_relax_kit-pinctrl.dtsi | 3 * SPDX-License-Identifier: Apache-2.0
6 #include <infineon/xmc4500_F100x1024-pinctrl.dtsi>
9 drive-strength = "strong-soft-edge";
10 drive-push-pull;
15 drive-strength = "strong-soft-edge";
20 drive-strength = "strong-medium-edge";
21 drive-push-pull;
26 drive-strength = "strong-medium-edge";
27 drive-push-pull;
|
| /Zephyr-Core-3.5.0/dts/bindings/pinctrl/ |
| D | infineon,cat1-pinctrl.yaml | 4 # SPDX-License-Identifier: Apache-2.0
11 UART0 RX to a particular port/pin and enable the pull-up resistor on that
22 'bias-pull-up' property. Here is a list of the supported standard pin
24 * bias-high-impedance
25 * bias-pull-up
26 * bias-pull-down
27 * drive-open-drain
28 * drive-open-source
29 * drive-push-pull (strong)
30 * input-enable (input-buffer)
[all …]
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| D | ti,cc32xx-pinctrl.yaml | 2 # SPDX-License-Identifier: Apache-2.0
7 use this node to route UART0 RX to pin 55 and enable the pull-up resistor
20 /* You can put this in places like a board-pinctrl.dtsi file in
24 /* include pre-defined combinations for the SoC variant used by the board */
25 #include <dt-bindings/pinctrl/gd32f450i(g-i-k)xx-pinctrl.h>
39 /* both pin 57 and 62 have pull-up enabled */
40 bias-pull-up;
53 pins, such as the 'bias-pull-up' property in group 2. Here is a list of
56 - drive-push-pull: Push-pull drive mode (default, not required).
57 - drive-open-drain: Open-drain drive mode.
[all …]
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| D | microchip,xec-pinctrl.yaml | 3 # SPDX-License-Identifier: Apache-2.0
7 Based on pincfg-node.yaml binding.
23 pins, such as the 'bias-pull-up' property in group 2. Here is a list of
26 - bias-disable: Disable pull-up/down (default behavior, not required).
27 - bias-pull-down: Enable pull-down resistor.
28 - bias-pull-up: Enable pull-up resistor.
29 - drive-push-pull: Output driver is push-pull (default, not required).
30 - drive-open-drain: Output driver is open-drain.
31 - output-high: Set output state high when pin configured.
32 - output-low: Set output state low when pin configured.
[all …]
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| D | ite,it8xxx2-pinctrl-func.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 compatible: "ite,it8xxx2-pinctrl-func"
11 func3-gcr:
14 func3-en-mask:
17 func3-ext:
21 the setting of func3-gcr, some pins require external setting.
23 func3-ext-mask:
26 func4-gcr:
29 func4-en-mask:
32 volt-sel:
[all …]
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| D | gd,gd32-pinctrl-common.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 child-binding:
7 child-binding:
9 - name: pincfg-node.yaml
10 property-allowlist:
11 - drive-push-pull
12 - drive-open-drain
13 - bias-disable
14 - bias-pull-down
15 - bias-pull-up
[all …]
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| D | infineon,xmc4xxx-pinctrl.yaml | 2 # SPDX-License-Identifier: Apache-2.0
12 compatible = "infineon,xmc4xxx-uart";
13 pinctrl-0 = <&uart_tx_p0_1_u1c1 &uart_rx_p0_0_u1c1>;
14 pinctrl-names = "default";
15 input-src = "DX0D";
19 pinctrl-0 is the phandle that stores the pin settings for two pins: &uart_tx_p0_1_u1c1
20 and &uart_rx_p0_0_u1c1. These nodes are pre-defined and their naming convention is designed
24 The pre-defined nodes only set the alternate function of the output pin. The
27 to the inherited property-allowlist list from pincfg-node.yaml).
31 #include <zephyr/dt-bindings/pinctrl/xmc4xxx-pinctrl.h>
[all …]
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| D | gd,gd32-pinctrl-af.yaml | 2 # SPDX-License-Identifier: Apache-2.0
7 use this node to route USART0 RX to pin PA10 and enable the pull-up resistor
20 /* You can put this in places like a board-pinctrl.dtsi file in
24 /* include pre-defined combinations for the SoC variant used by the board */
25 #include <dt-bindings/pinctrl/gd32f450i(g-i-k)xx-pinctrl.h>
39 /* both PA10 and PA12 have pull-up enabled */
40 bias-pull-up;
56 is used for low power states because it disconnects the pin pull-up/down
64 pins, such as the 'bias-pull-up' property in group 2. Here is a list of
67 - drive-push-pull: Push-pull drive mode (default, not required).
[all …]
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| D | cypress,psoc6-pinctrl.yaml | 3 # SPDX-License-Identifier: Apache-2.0
6 Cypress PSoC-6 Pinctrl container node
8 The Cypress PSoC-6 pins implements following pin configuration option:
10 * bias-pull-up
11 * bias-pull-down
12 * drive-open-drain
13 * drive-open-source
14 * drive-push-pull (strong)
15 * input-enable (input-buffer)
20 compatible: "cypress,psoc6-pinctrl"
[all …]
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| D | gd,gd32-pinctrl-afio.yaml | 2 # SPDX-License-Identifier: Apache-2.0
7 use this node to route USART0 RX to pin PA10 and enable the pull-up resistor
20 /* You can put this in places like a board-pinctrl.dtsi file in
24 /* include pre-defined combinations for the SoC variant used by the board */
25 #include <dt-bindings/pinctrl/gd32f403z(k-i-g-e-c-b)xx-pinctrl.h>
39 /* both PA10 and PA12 have pull-up enabled */
40 bias-pull-up;
56 is used for low power states because it disconnects the pin pull-up/down
64 pins, such as the 'bias-pull-up' property in group 2. Here is a list of
67 - drive-push-pull: Push-pull drive mode (default, not required). Only
[all …]
|
| D | nxp,lpc-iocon-pinctrl.yaml | 2 # SPDX-License-Identifier: Apache-2.0
16 slew-rate = "standard";
24 IOCON_SLEW=<slew-rate selection>,
38 drive-open-drain: IOCON_OD=1
39 bias-pull-up: IOCON_MODE=2
40 bias-pull-down: IOCON_MODE=1
41 drive-push-pull: IOCON_MODE=3
44 IOCON_HYS- set by input-schmitt-enable
45 IOCON_S_MODE- set by nxp,digital-filter
46 IOCON_CLKDIV- set by nxp,filter-clock-div
[all …]
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| D | st,stm32-pinctrl.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 Based on pincfg-node.yaml binding.
8 Note: `bias-disable` and `drive-push-pull` are default pin configurations.
9 They will be applied in case no `bias-foo` or `driver-bar` properties
12 compatible: "st,stm32-pinctrl"
20 remap-pa11:
25 remap-pa12:
30 remap-pa11-pa12:
35 child-binding:
40 - name: pincfg-node.yaml
[all …]
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| /Zephyr-Core-3.5.0/soc/riscv/riscv-ite/common/ |
| D | pinctrl_soc.h | 4 * SPDX-License-Identifier: Apache-2.0
11 #include <zephyr/dt-bindings/pinctrl/it8xxx2-pinctrl.h>
22 * kSI[7:0] and KSO[15:0] pins only support pull-up, push-pull/open-drain.
24 * pull-up/down, voltage selection, input.
41 * Pin pull-up/down config [ 4 : 5 ]
44 * Pin push-pull/open-drain [ 16 ]
56 /* Pin tri-state mode. */
59 /* Pin pull-up or pull-down */
69 /* Pin push-pull/open-drain mode */
74 * @brief Utility macro to obtain configuration of tri-state.
[all …]
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| /Zephyr-Core-3.5.0/tests/drivers/w1/w1_api/boards/ |
| D | nucleo_g0b1re.overlay | 4 * SPDX-License-Identifier: Apache-2.0
9 * enable open-drain drive such that no external push-pull to
10 * open-drain converter is required. An external pull-up resistor
14 drive-open-drain;
15 bias-pull-up;
|
| /Zephyr-Core-3.5.0/tests/drivers/spi/spi_loopback/boards/ |
| D | cy8cproto_062_4343w.overlay | 2 compatible = "infineon,cat1-spi";
5 pinctrl-0 = <&p6_0_scb3_spi_m_mosi &p6_1_scb3_spi_m_miso &p6_2_scb3_spi_m_clk>;
6 pinctrl-names = "default";
7 cs-gpios = <&gpio_prt6 3 GPIO_ACTIVE_LOW>;
10 compatible = "test-spi-loopback-slow";
12 spi-max-frequency = <2000000>;
15 compatible = "test-spi-loopback-fast";
17 spi-max-frequency = <3000000>;
29 drive-push-pull;
34 input-enable;
[all …]
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| D | cy8cproto_063_ble.overlay | 5 drive-push-pull;
10 input-enable;
15 drive-push-pull;
20 compatible = "infineon,cat1-spi";
23 pinctrl-0 = <&p10_0_scb1_spi_m_mosi &p10_1_scb1_spi_m_miso &p10_2_scb1_spi_m_clk>;
24 pinctrl-names = "default";
25 cs-gpios = <&gpio_prt10 3 GPIO_ACTIVE_LOW>;
28 compatible = "test-spi-loopback-slow";
30 spi-max-frequency = <200000>;
34 compatible = "test-spi-loopback-fast";
[all …]
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| D | xmc47_relax_kit.overlay | 4 * SPDX-License-Identifier: Apache-2.0
8 drive-strength = "strong-soft-edge";
9 drive-push-pull;
14 drive-strength = "strong-soft-edge";
19 drive-strength = "strong-soft-edge";
20 drive-push-pull;
25 compatible = "infineon,xmc4xxx-spi";
26 pinctrl-0 = <&spi_mosi_p3_8_u2c0 &spi_miso_p3_7_u2c0 &spi_sclk_p3_9_u2c0>;
27 pinctrl-names = "default";
28 miso-src = "DX0C";
[all …]
|
| /Zephyr-Core-3.5.0/dts/bindings/sensor/ |
| D | bosch,bmi08x-gyro.yaml | 2 # SPDX-License-Identifier: Apache-2.0
6 include: sensor-device.yaml
9 int-gpios:
10 type: phandle-array
16 int3-4-map-io:
24 int3-4-conf-io:
28 Bit[1]: if set to 1, INT3 is open-drain, otherwise it's push-pull
30 Bit[3]: if set to 1, INT4 is open-drain, otherwise it's push-pull
32 gyro-hz:
36 Default frequency of accelerometer. (Unit - Hz)
[all …]
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| /Zephyr-Core-3.5.0/drivers/pinctrl/ |
| D | pinctrl_ite_it8xxx2.c | 4 * SPDX-License-Identifier: Apache-2.0
50 * KSO push-pull/open-drain bit of KSO[15:0] control register
71 const struct pinctrl_it8xxx2_config *pinctrl_config = pins->pinctrls->config; in pinctrl_it8xxx2_set()
72 const struct pinctrl_it8xxx2_gpio *gpio = &(pinctrl_config->gpio); in pinctrl_it8xxx2_set()
73 uint32_t pincfg = pins->pincfg; in pinctrl_it8xxx2_set()
74 uint8_t pin = pins->pin; in pinctrl_it8xxx2_set()
75 volatile uint8_t *reg_gpcr = (uint8_t *)gpio->reg_gpcr + pin; in pinctrl_it8xxx2_set()
76 volatile uint8_t *reg_volt_sel = (uint8_t *)(gpio->volt_sel[pin]); in pinctrl_it8xxx2_set()
78 /* Setting pull-up or pull-down. */ in pinctrl_it8xxx2_set()
81 /* No pull-up or pull-down */ in pinctrl_it8xxx2_set()
[all …]
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| /Zephyr-Core-3.5.0/doc/connectivity/bluetooth/api/mesh/ |
| D | blob.rst | 13 bytes). The BLOB transfer protocol has built-in recovery procedures for packet losses, and sets up
19 BLOB to be transferred in 10-15 minutes. However, network conditions, transfer capabilities and
52 The BLOB transfer protocol does not provide any built-in integrity checks, encryption or
58 ------
68 ------
74 When operating in Push BLOB Transfer Mode, the chunks are sent as unacknowledged packets from the
80 When operating in Pull BLOB Transfer Mode, the BLOB Transfer Server will request a small number of
92 In the BLOB Transfer models' APIs, the BLOB data handling is separated from the high-level transfer
104 -----------
119 ---------------
[all …]
|
