1/*
2 * Copyright (c) 2023 Antmicro <www.antmicro.com>
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6
7#include <dt-bindings/pinctrl/ambiq-apollo4-pinctrl.h>
8
9&pinctrl {
10	uart0_default: uart0_default {
11		group1 {
12			pinmux = <UART0TX_P60>;
13		};
14		group2 {
15			pinmux = <UART0RX_P47>;
16			input-enable;
17		};
18	};
19	i2c0_default: i2c0_default {
20		group1 {
21			pinmux = <M0SCL_P5>, <M0SDAWIR3_P6>;
22			drive-open-drain;
23			drive-strength = "0.5";
24			bias-pull-up;
25		};
26	};
27	i2c1_default: i2c1_default {
28		group1 {
29			pinmux = <M1SCL_P8>, <M1SDAWIR3_P9>;
30			drive-open-drain;
31			drive-strength = "0.5";
32			bias-pull-up;
33		};
34	};
35	i2c2_default: i2c2_default {
36		group1 {
37			pinmux = <M2SCL_P25>, <M2SDAWIR3_P26>;
38			drive-open-drain;
39			drive-strength = "0.5";
40			bias-pull-up;
41		};
42	};
43	i2c3_default: i2c3_default {
44		group1 {
45			pinmux = <M3SCL_P31>, <M3SDAWIR3_P32>;
46			drive-open-drain;
47			drive-strength = "0.5";
48			bias-pull-up;
49		};
50	};
51	i2c4_default: i2c4_default {
52		group1 {
53			pinmux = <M4SCL_P34>, <M4SDAWIR3_P35>;
54			drive-open-drain;
55			drive-strength = "0.5";
56			bias-pull-up;
57		};
58	};
59	i2c5_default: i2c5_default {
60		group1 {
61			pinmux = <M5SCL_P47>, <M5SDAWIR3_P48>;
62			drive-open-drain;
63			drive-strength = "0.5";
64			bias-pull-up;
65		};
66	};
67	i2c6_default: i2c6_default {
68		group1 {
69			pinmux = <M6SCL_P61>, <M6SDAWIR3_P62>;
70			drive-open-drain;
71			drive-strength = "0.5";
72			bias-pull-up;
73		};
74	};
75	i2c7_default: i2c7_default {
76		group1 {
77			pinmux = <M7SCL_P22>, <M7SDAWIR3_P23>;
78			drive-open-drain;
79			drive-strength = "0.5";
80			bias-pull-up;
81		};
82	};
83
84	spi0_default: spi0_default {
85		group1 {
86			pinmux = <M0SCK_P5>, <M0MISO_P7>, <M0MOSI_P6>;
87		};
88		group2 {
89			pinmux = <NCE72_P72>;
90			drive-push-pull;
91			ambiq,iom-nce-module = <0>;
92		};
93	};
94	spi1_default: spi1_default {
95		group1 {
96			pinmux = <M1SCK_P8>, <M1MISO_P10>, <M1MOSI_P9>;
97		};
98		group2 {
99			pinmux = <NCE11_P11>;
100			drive-push-pull;
101			ambiq,iom-nce-module = <4>;
102		};
103	};
104	spi2_default: spi2_default {
105		group1 {
106			pinmux = <M2SCK_P25>, <M2MISO_P27>, <M2MOSI_P26>;
107		};
108		group2 {
109			pinmux = <NCE37_P37>;
110			drive-push-pull;
111			ambiq,iom-nce-module = <8>;
112		};
113	};
114	spi3_default: spi3_default {
115		group1 {
116			pinmux = <M3SCK_P31>, <M3MISO_P33>, <M3MOSI_P32>;
117		};
118		group2 {
119			pinmux = <NCE85_P85>;
120			drive-push-pull;
121			ambiq,iom-nce-module = <12>;
122		};
123	};
124	spi4_default: spi4_default {
125		group1 {
126			pinmux = <M4SCK_P34>, <M4MISO_P36>, <M4MOSI_P35>;
127		};
128		group2 {
129			pinmux = <NCE79_P79>;
130			drive-push-pull;
131			ambiq,iom-nce-module = <16>;
132		};
133	};
134	spi5_default: spi5_default {
135		group1 {
136			pinmux = <M5SCK_P47>, <M5MISO_P49>, <M5MOSI_P48>;
137		};
138		group2 {
139			pinmux = <NCE60_P60>;
140			drive-push-pull;
141			ambiq,iom-nce-module = <20>;
142		};
143	};
144	spi6_default: spi6_default {
145		group1 {
146			pinmux = <M6SCK_P61>, <M6MISO_P63>, <M6MOSI_P62>;
147		};
148		group2 {
149			pinmux = <NCE30_P30>;
150			drive-push-pull;
151			ambiq,iom-nce-module = <24>;
152		};
153	};
154	spi7_default: spi7_default {
155		group1 {
156			pinmux = <M7SCK_P22>, <M7MISO_P24>, <M7MOSI_P23>;
157		};
158		group2 {
159			pinmux = <NCE88_P88>;
160			drive-push-pull;
161			ambiq,iom-nce-module = <28>;
162		};
163	};
164	mspi0_default: mspi0_default{
165		group1 {
166			pinmux = <MSPI0_0_P64>,
167				 <MSPI0_1_P65>,
168				 <MSPI0_8_P72>;
169		};
170		group2 {
171			pinmux = <NCE57_P57>;
172			drive-push-pull;
173			drive-strength = "0.5";
174			ambiq,iom-nce-module = <32>;
175		};
176	};
177	mspi1_default: mspi1_default{
178		group1 {
179			pinmux = <MSPI1_0_P37>,
180				 <MSPI1_1_P38>,
181				 <MSPI1_8_P45>;
182		};
183		group2 {
184			pinmux = <NCE56_P56>;
185			drive-push-pull;
186			drive-strength = "0.5";
187			ambiq,iom-nce-module = <34>;
188		};
189	};
190	mspi2_default: mspi2_default{
191		group1 {
192			pinmux = <MSPI2_0_P74>,
193				 <MSPI2_1_P75>,
194				 <MSPI2_8_P82>;
195		};
196		group2 {
197			pinmux = <NCE0_P0>;
198			drive-push-pull;
199			drive-strength = "0.5";
200			ambiq,iom-nce-module = <36>;
201		};
202	};
203};
204