Searched full:latch (Results 1 – 25 of 61) sorted by relevance
123
| /Zephyr-latest/dts/bindings/gpio/ |
| D | ti,tca9538.yaml | 27 input-latch:
30 Input latch register bit is 0 by default and the input pin state
31 is not latched. When input latch register bit is 1 and the input
|
| D | adi,max22190-gpio.yaml | 33 latch-gpios = <&gpioj 13 GPIO_ACTIVE_LOW>; /* SDP-GPIO6 - PMOD-PIN9 */
59 latch-gpios:
61 Latch the data so it could be read (partially duplicate CS)
|
| /Zephyr-latest/dts/bindings/serial/ |
| D | zephyr,uart-emul.yaml | 29 latch-buffer-size:
33 Size of the virtual UART latch buffer.
|
| D | ns16550.yaml | 19 description: divisor latch fraction (DLF, if supported)
|
| /Zephyr-latest/soc/microchip/mec/common/reg/ |
| D | mec_vci.h | 31 /* VCI Latch Enable register */
32 /* VCI Latch Reset register */
|
| D | mec_kbc.h | 74 * GATEA20 latch to be set.
82 * the GATEA20 latch to be reset
|
| D | mec_tach.h | 32 /* Select read mode. Latch data on rising edge of selected trigger */
|
| /Zephyr-latest/modules/nrf_wifi/bus/ |
| D | spi_nor.h | 21 #define SPI_NOR_WEL_BIT BIT(1) /* Write enable latch */
|
| /Zephyr-latest/dts/bindings/led_strip/ |
| D | ws2812.yaml | 33 The latch/reset delay is 250 us and it must be set using the reset-delay
|
| /Zephyr-latest/include/zephyr/net/ |
| D | mdio.h | 212 /** 10BASE-T1L Remote Receiver Status OK Latch Low */
220 /** 10BASE-T1L Descrambler Status OK Latch Low */
224 /** 10BASE-T1L Link Status OK Latch Low */
|
| /Zephyr-latest/drivers/eeprom/ |
| D | eeprom_mb85rsxx.c | 24 #define EEPROM_MB85RSXX_WREN 0x06U /* Set Write Enable Latch */
25 #define EEPROM_MB85RSXX_WRDI 0x04U /* Reset Write Enable Latch */
38 #define EEPROM_MB85RSXX_STATUS_WEL BIT(1) /* Write Enable Latch (RO) */
|
| /Zephyr-latest/include/zephyr/drivers/gpio/ |
| D | gpio_cmsdk_ahb.h | 19 /* Offset: 0x004 (r/w) data output latch register */
|
| /Zephyr-latest/drivers/led_strip/ |
| D | ws2812_spi.c | 71 * Latch current color values on strip and reset its state machines.
198 /* Get the latch/reset delay from the "reset-delay" DT property. */
|
| /Zephyr-latest/drivers/counter/ |
| D | counter_cmos.c | 20 /* The "CMOS" device is accessed via an address latch and data port. */
70 * Read a value from the CMOS. Because of the address latch,
|
| /Zephyr-latest/dts/bindings/sensor/ |
| D | st,lis2dh-common.yaml | 77 anym-no-latch:
|
| /Zephyr-latest/dts/bindings/pinctrl/ |
| D | nxp,mcux-rt11xx-pinctrl.yaml | 20 Both pins will be configured with a weak latch, high drive strength,
|
| D | pincfg-node.yaml | 29 description: latch weakly
|
| D | nxp,mcux-rt-pinctrl.yaml | 21 Both pins will be configured with a weak latch, drive strength of "r0-6",
|
| /Zephyr-latest/drivers/gpio/ |
| D | gpio_smartbond.c | 27 * data access, bit access, mode, latch and wake-up controller are defined in
40 uint32_t latch; member
410 DT_INST_REG_ADDR_BY_NAME(id, latch), \
|
| /Zephyr-latest/drivers/serial/ |
| D | uart_lpc11u6x.h | 100 volatile uint32_t dll; /* Divisor latch LSB */
103 volatile uint32_t dlm; /* Divisor latch MSB */
|
| /Zephyr-latest/samples/drivers/led/apa102c_bitbang/src/ |
| D | main.c | 58 /* Latch data into LED */ in send_rgb()
|
| /Zephyr-latest/drivers/timer/ |
| D | leon_gptimer.c | 28 uint32_t latch; member
|
| /Zephyr-latest/soc/mediatek/mt8xxx/ |
| D | mbox.c | 13 * command register and will latch an interrupt if any of the bits are
|
| D | cpuclk.c | 109 * presumably to latch the input.
|
| /Zephyr-latest/drivers/flash/ |
| D | flash_andes_qspi.h | 27 #define FLASH_ANDES_WEL_BIT BIT(1) /* Write enable latch */
|
123
